Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging

pc, pci, virtio: new features, cleanups, fixes

This includes some infrastructure for ipmi smbios tables.
Beginning of acpi hotplug rework by Igor for supporting >255 CPUs.
Misc cleanups and fixes.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Tue 07 Jun 2016 13:55:22 BST
# gpg:                using RSA key 0x281F0DB8D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"

* remotes/mst/tags/for_upstream: (25 commits)
  virtio: move bi-endian target support to a single location
  pc-dimm: introduce realize callback
  pc-dimm: get memory region from ->get_memory_region()
  acpi: make bios_linker_loader_add_checksum() API offset based
  acpi: make bios_linker_loader_add_pointer() API offset based
  tpm: apci: cleanup TCPA table initialization
  acpi: cleanup bios_linker_loader_cleanup()
  acpi: simplify bios_linker API by removing redundant 'table' argument
  acpi: convert linker from GArray to BIOSLinker structure
  pc: use AcpiDeviceIfClass.send_event to issue GPE events
  acpi: extend ACPI interface to provide send_event hook
  pc: Postpone SMBIOS table installation to post machine init
  ipmi: rework the fwinfo to be fetched from the interface
  tests: acpi: update tables with consolidated legacy cpu-hotplug AML
  pc: acpi: cpuhp-legacy: switch ProcessorID to possible_cpus idx
  pc: acpi: simplify build_legacy_cpu_hotplug_aml() signature
  pc: acpi: consolidate legacy CPU hotplug in one file
  pc: acpi: mark current CPU hotplug functions as legacy
  pc: acpi: cpu-hotplug: make AML CPU_foo defines local to cpu_hotplug_acpi_table.c
  pc: acpi: consolidate \GPE._E02 with the rest of CPU hotplug AML
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --combined target-ppc/cpu.h
index c2962d7f553047629ff4f65e2ceea23519affaf0,db7ee0c74d8559fa466b0fb0a474168e397c99a9..cb8b9122f38e4f6f3535be823e2ef9bb923e953e
--- 1/target-ppc/cpu.h
--- 2/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@@ -28,8 -28,6 +28,6 @@@
  #define TARGET_LONG_BITS 64
  #define TARGET_PAGE_BITS 12
  
- #define TARGET_IS_BIENDIAN 1
- 
  /* Note that the official physical address space bits is 62-M where M
     is implementation dependent.  I've not looked up M for the set of
     cpus we emulate at the system level.  */
@@@ -959,6 -957,7 +957,6 @@@ struct CPUPPCState 
      ppc_slb_t slb[MAX_SLB_ENTRIES];
      int32_t slb_nr;
      /* tcg TLB needs flush (deferred slb inval instruction typically) */
 -    uint32_t tlb_need_flush;
  #endif
      /* segment registers */
      hwaddr htab_base;
@@@ -984,7 -983,6 +982,7 @@@
      target_ulong pb[4];
      bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
      bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
 +    uint32_t tlb_need_flush; /* Delayed flush needed */
  #endif
  
      /* Other registers */
@@@ -1050,10 -1048,6 +1048,10 @@@
      hwaddr mpic_iack;
      /* true when the external proxy facility mode is enabled */
      bool mpic_proxy;
 +    /* set when the processor has an HV mode, thus HV priv
 +     * instructions and SPRs are diallowed if MSR:HV is 0
 +     */
 +    bool has_hv_mode;
  #endif
  
      /* Those resources are used only during code translation */