drm: rcar-du: Allow DU groups to work with hardware indexing

The group objects assume linear indexing, and more so always assume that
channel 0 of any active group is used.

Now that the CRTC objects support non-linear indexing, adapt the groups
to remove assumptions that channel 0 is utilised in each group by using
the channel mask provided in the device structures.

Finally ensure that the RGB routing is determined from the index of the
CRTC object (which represents the hardware DU channel index).

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index eead202c95c7b8873460d28ecb61fe2dc52e2f0e..d539cb290a3518af3ca8561cd0dc735f5f02dd77 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -46,9 +46,12 @@ void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
 
 static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
 {
-       u32 defr6 = DEFR6_CODE | DEFR6_ODPM02_DISP;
+       u32 defr6 = DEFR6_CODE;
 
-       if (rgrp->num_crtcs > 1)
+       if (rgrp->channels_mask & BIT(0))
+               defr6 |= DEFR6_ODPM02_DISP;
+
+       if (rgrp->channels_mask & BIT(1))
                defr6 |= DEFR6_ODPM12_DISP;
 
        rcar_du_group_write(rgrp, DEFR6, defr6);
@@ -80,10 +83,11 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
                 * On Gen3 VSPD routing can't be configured, but DPAD routing
                 * needs to be set despite having a single option available.
                 */
-               u32 crtc = ffs(possible_crtcs) - 1;
+               unsigned int rgb_crtc = ffs(possible_crtcs) - 1;
+               struct rcar_du_crtc *crtc = &rcdu->crtcs[rgb_crtc];
 
-               if (crtc / 2 == rgrp->index)
-                       defr8 |= DEFR8_DRGBS_DU(crtc);
+               if (crtc->index / 2 == rgrp->index)
+                       defr8 |= DEFR8_DRGBS_DU(crtc->index);
        }
 
        rcar_du_group_write(rgrp, DEFR8, defr8);

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.h b/drivers/gpu/drm/rcar-du/rcar_du_group.h
index 5e3adc6b31b56356a6fba3aea129bf9653829b7d..42105aedecc865f08ca78c2ae1b6f875ec6a143d 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.h
@@ -25,6 +25,7 @@ struct rcar_du_device;
  * @dev: the DU device
  * @mmio_offset: registers offset in the device memory map
  * @index: group index
+ * @channels_mask: bitmask of populated DU channels in this group
  * @num_crtcs: number of CRTCs in this group (1 or 2)
  * @use_count: number of users of the group (rcar_du_group_(get|put))
  * @used_crtcs: number of CRTCs currently in use
@@ -39,6 +40,7 @@ struct rcar_du_group {
        unsigned int mmio_offset;
        unsigned int index;
 
+       unsigned int channels_mask;
        unsigned int num_crtcs;
        unsigned int use_count;
        unsigned int used_crtcs;

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index b5e331cb0d1c1d5ea79488c1bdf95c2e2bd46fee..34f1c27e9cf92845f9bb3dc5e54c711d39832ea3 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -559,7 +559,10 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
                rgrp->dev = rcdu;
                rgrp->mmio_offset = mmio_offsets[i];
                rgrp->index = i;
-               rgrp->num_crtcs = min(rcdu->num_crtcs - 2 * i, 2U);
+               /* Extract the channel mask for this group only. */
+               rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
+                                  & GENMASK(1, 0);
+               rgrp->num_crtcs = hweight8(rgrp->channels_mask);
 
                /*
                 * If we have more than one CRTCs in this group pre-associate