]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/commitdiff
ASoC: cs42l42: Fix Bitclock polarity inversion
authorLucas Tanure <tanureal@opensource.cirrus.com>
Fri, 5 Mar 2021 17:34:28 +0000 (17:34 +0000)
committerSeth Forshee <seth.forshee@canonical.com>
Thu, 8 Apr 2021 20:42:44 +0000 (15:42 -0500)
BugLink: https://bugs.launchpad.net/bugs/1923069
[ Upstream commit e793c965519b8b7f2fea51a48398405e2a501729 ]

The driver was setting bit clock polarity opposite to intended polarity.
Also simplify the code by grouping ADC and DAC clock configurations into
a single field.

Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210305173442.195740-2-tanureal@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Andrea Righi <andrea.righi@canonical.com>
sound/soc/codecs/cs42l42.c
sound/soc/codecs/cs42l42.h

index 210fcbedf2413b41464e1c42759cab2433081ab6..df0d5fec0287a452c8da6095170c4740fade5a88 100644 (file)
@@ -797,27 +797,23 @@ static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
        /* Bitclock/frame inversion */
        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
        case SND_SOC_DAIFMT_NB_NF:
+               asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
                break;
        case SND_SOC_DAIFMT_NB_IF:
-               asp_cfg_val |= CS42L42_ASP_POL_INV <<
-                               CS42L42_ASP_LCPOL_IN_SHIFT;
+               asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
+               asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
                break;
        case SND_SOC_DAIFMT_IB_NF:
-               asp_cfg_val |= CS42L42_ASP_POL_INV <<
-                               CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
                break;
        case SND_SOC_DAIFMT_IB_IF:
-               asp_cfg_val |= CS42L42_ASP_POL_INV <<
-                               CS42L42_ASP_LCPOL_IN_SHIFT;
-               asp_cfg_val |= CS42L42_ASP_POL_INV <<
-                               CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
+               asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
                break;
        }
 
-       snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG,
-                               CS42L42_ASP_MODE_MASK |
-                               CS42L42_ASP_SCPOL_IN_DAC_MASK |
-                               CS42L42_ASP_LCPOL_IN_MASK, asp_cfg_val);
+       snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
+                                                                     CS42L42_ASP_SCPOL_MASK |
+                                                                     CS42L42_ASP_LCPOL_MASK,
+                                                                     asp_cfg_val);
 
        return 0;
 }
index 9e3cc528dcff0838e4ab0645909708b558ef6a01..1f0d67c95a9adcdbb491870f7f1f46601ccc4559 100644 (file)
 #define CS42L42_ASP_SLAVE_MODE         0x00
 #define CS42L42_ASP_MODE_SHIFT         4
 #define CS42L42_ASP_MODE_MASK          (1 << CS42L42_ASP_MODE_SHIFT)
-#define CS42L42_ASP_SCPOL_IN_DAC_SHIFT 2
-#define CS42L42_ASP_SCPOL_IN_DAC_MASK  (1 << CS42L42_ASP_SCPOL_IN_DAC_SHIFT)
-#define CS42L42_ASP_LCPOL_IN_SHIFT     0
-#define CS42L42_ASP_LCPOL_IN_MASK      (1 << CS42L42_ASP_LCPOL_IN_SHIFT)
-#define CS42L42_ASP_POL_INV            1
+#define CS42L42_ASP_SCPOL_SHIFT                2
+#define CS42L42_ASP_SCPOL_MASK         (3 << CS42L42_ASP_SCPOL_SHIFT)
+#define CS42L42_ASP_SCPOL_NOR          3
+#define CS42L42_ASP_LCPOL_SHIFT                0
+#define CS42L42_ASP_LCPOL_MASK         (3 << CS42L42_ASP_LCPOL_SHIFT)
+#define CS42L42_ASP_LCPOL_INV          3
 
 #define CS42L42_ASP_FRM_CFG            (CS42L42_PAGE_12 + 0x08)
 #define CS42L42_ASP_STP_SHIFT          4