drm/i915/tgl/dsi: Do not override TA_SURE

Do not override TA_SURE timing parameter to
zero for DSI 8X frequency 800MHz or below on
TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190730073648.5157-4-vandita.kulkarni@intel.com

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 3185cb0bae41b7a0303b2aacb3281e09f944fa43..c6cda529c5bb95092b1e1ddbac8376bebb73414c 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -530,18 +530,20 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
         * a value '0' inside TA_PARAM_REGISTERS otherwise
         * leave all fields at HW default values.
         */
-       if (intel_dsi_bitrate(intel_dsi) <= 800000) {
-               for_each_dsi_port(port, intel_dsi->ports) {
-                       tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
-                       tmp &= ~TA_SURE_MASK;
-                       tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
-                       I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
-
-                       /* shadow register inside display core */
-                       tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
-                       tmp &= ~TA_SURE_MASK;
-                       tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
-                       I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+       if (IS_GEN(dev_priv, 11)) {
+               if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+                       for_each_dsi_port(port, intel_dsi->ports) {
+                               tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+                               tmp &= ~TA_SURE_MASK;
+                               tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+                               I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+                               /* shadow register inside display core */
+                               tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+                               tmp &= ~TA_SURE_MASK;
+                               tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+                               I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+                       }
                }
        }