struct clk_div4_table {
struct clk_div_mult_table *div_mult_table;
+ void (*kick)(struct clk *clk);
};
int sh_clk_div4_register(struct clk *clks, int nr,
static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
{
+ struct clk_div4_table *d4t = clk->priv;
unsigned long value;
int idx = clk_rate_table_find(clk, clk->freq_table, rate);
if (idx < 0)
value |= (idx << clk->enable_bit);
__raw_writel(value, clk->enable_reg);
+ if (d4t->kick)
+ d4t->kick(clk);
+
return 0;
}
&div3_clk,
};
+static void div4_kick(struct clk *clk)
+{
+ unsigned long value;
+
+ /* set KICK bit in FRQCRA to update hardware setting */
+ value = __raw_readl(FRQCRA);
+ value |= (1 << 31);
+ __raw_writel(value, FRQCRA);
+}
+
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
static struct clk_div_mult_table div4_div_mult_table = {
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
+ .kick = div4_kick,
};
enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };