drm/amd/powerplay: init vega20 uvd/vce powergate status on dpm setup

This is essentially necessary when uvd/vce dpm is not enabled yet.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 06471d1a5765257cbd0364fdd9492ad8ea95b4ad..a82a3df0e8d95211a17a5447a0d3bd286f1e45e6 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -932,6 +932,21 @@ static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
+static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
+{
+       struct vega20_hwmgr *data =
+               (struct vega20_hwmgr *)(hwmgr->backend);
+
+       data->uvd_power_gated = true;
+       data->vce_power_gated = true;
+
+       if (data->smu_features[GNLD_DPM_UVD].enabled)
+               data->uvd_power_gated = false;
+
+       if (data->smu_features[GNLD_DPM_VCE].enabled)
+               data->vce_power_gated = false;
+}
+
 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
        int result = 0;
@@ -954,6 +969,9 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
                        "[EnableDPMTasks] Failed to enable all smu features!",
                        return result);
 
+       /* Initialize UVD/VCE powergating state */
+       vega20_init_powergate_state(hwmgr);
+
        result = vega20_setup_default_dpm_tables(hwmgr);
        PP_ASSERT_WITH_CODE(!result,
                        "[EnableDPMTasks] Failed to setup default DPM tables!",