cpu: 8
memory: 8G
install_script: ASSUME_ALWAYS_YES=yes pkg bootstrap -f ; pkg install -y
- bash bison curl cyrus-sasl git glib gmake gnutls gsed
+ bash curl cyrus-sasl git glib gmake gnutls gsed
nettle perl5 pixman pkgconf png usbredir
script:
- mkdir build
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <arikalo@wavecomp.com>
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <aleksandar.rikalo@rt-rk.com>
Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
+Filip Bozuta <filip.bozuta@syrmia.com> <filip.bozuta@rt-rk.com.com>
+Frederic Konrad <konrad@adacore.com> <fred.konrad@greensocs.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>
Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>
Philippe Mathieu-Daudé <philmd@redhat.com> <f4bug@amsat.org>
+Stefan Brankovic <stefan.brankovic@syrmia.com> <stefan.brankovic@rt-rk.com.com>
Yongbok Kim <yongbok.kim@mips.com> <yongbok.kim@imgtec.com>
# Also list preferred name forms where people have changed their
global:
- LC_ALL=C
matrix:
- - IMAGE=debian-amd64
- TARGET_LIST=x86_64-softmmu,x86_64-linux-user
+ # - IMAGE=debian-amd64
+ # TARGET_LIST=x86_64-softmmu,x86_64-linux-user
- IMAGE=debian-win32-cross
TARGET_LIST=arm-softmmu,i386-softmmu,lm32-softmmu
- IMAGE=debian-win64-cross
TARGET_LIST=aarch64-softmmu,aarch64-linux-user
- IMAGE=debian-s390x-cross
TARGET_LIST=s390x-softmmu,s390x-linux-user
- - IMAGE=debian-mips-cross
- TARGET_LIST=mips-softmmu,mipsel-linux-user
- - IMAGE=debian-mips64el-cross
- TARGET_LIST=mips64el-softmmu,mips64el-linux-user
+ # - IMAGE=debian-mips-cross
+ # TARGET_LIST=mips-softmmu,mipsel-linux-user
+ # - IMAGE=debian-mips64el-cross
+ # TARGET_LIST=mips64el-softmmu,mips64el-linux-user
- IMAGE=debian-ppc64el-cross
TARGET_LIST=ppc64-softmmu,ppc64-linux-user,ppc64abi32-linux-user
build:
env:
- TEST_CMD="make check check-tcg V=1"
- CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}"
+ - UNRELIABLE=true
- name: "[ppc64] GCC check-tcg"
arch: ppc64le
env:
- TEST_CMD="make check check-tcg V=1"
- CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS},s390x-linux-user"
+ - UNRELIABLE=true
script:
- ( cd ${SRC_DIR} ; git submodule update --init roms/SLOF )
- BUILD_RC=0 && make -j${JOBS} || BUILD_RC=$?
- TEST_CMD="make check-unit"
- CONFIG="--disable-containers --disable-tcg --enable-kvm
--disable-tools --host-cc=clang --cxx=clang++"
+ - UNRELIABLE=true
# Release builds
# The make-release script expect a QEMU version, so our tag must start with a 'v'.
- mkdir -p release-build && cd release-build
- ../configure ${BASE_CONFIG} ${CONFIG} || { cat config.log && exit 1; }
- make install
+ allow_failures:
+ - env: UNRELIABLE=true
F: hw/smbios/*
F: hw/i386/acpi-build.[hc]
F: hw/arm/virt-acpi-build.c
-F: tests/qtest/bios-tables-test.c
+F: tests/qtest/bios-tables-test*
F: tests/qtest/acpi-utils.[hc]
F: tests/data/acpi/
F: qtest.c
F: accel/qtest.c
F: tests/qtest/
+X: tests/qtest/bios-tables-test-allowed-diff.h
Device Fuzzing
M: Alexander Bulekov <alxndr@bu.edu>
pstrcpy(bs->filename, sizeof(bs->filename), bs->exact_filename);
} else {
QString *json = qobject_to_json(QOBJECT(bs->full_open_options));
- snprintf(bs->filename, sizeof(bs->filename), "json:%s",
- qstring_get_str(json));
+ if (snprintf(bs->filename, sizeof(bs->filename), "json:%s",
+ qstring_get_str(json)) >= sizeof(bs->filename)) {
+ /* Give user a hint if we truncated things. */
+ strcpy(bs->filename + sizeof(bs->filename) - 4, "...");
+ }
qobject_unref(json);
}
}
{
BDRVNBDState *s = bs->opaque;
const char *host = NULL, *port = NULL, *path = NULL;
+ size_t len = 0;
if (s->saddr->type == SOCKET_ADDRESS_TYPE_INET) {
const InetSocketAddress *inet = &s->saddr->u.inet;
} /* else can't represent as pseudo-filename */
if (path && s->export) {
- snprintf(bs->exact_filename, sizeof(bs->exact_filename),
- "nbd+unix:///%s?socket=%s", s->export, path);
+ len = snprintf(bs->exact_filename, sizeof(bs->exact_filename),
+ "nbd+unix:///%s?socket=%s", s->export, path);
} else if (path && !s->export) {
- snprintf(bs->exact_filename, sizeof(bs->exact_filename),
- "nbd+unix://?socket=%s", path);
+ len = snprintf(bs->exact_filename, sizeof(bs->exact_filename),
+ "nbd+unix://?socket=%s", path);
} else if (host && s->export) {
- snprintf(bs->exact_filename, sizeof(bs->exact_filename),
- "nbd://%s:%s/%s", host, port, s->export);
+ len = snprintf(bs->exact_filename, sizeof(bs->exact_filename),
+ "nbd://%s:%s/%s", host, port, s->export);
} else if (host && !s->export) {
- snprintf(bs->exact_filename, sizeof(bs->exact_filename),
- "nbd://%s:%s", host, port);
+ len = snprintf(bs->exact_filename, sizeof(bs->exact_filename),
+ "nbd://%s:%s", host, port);
+ }
+ if (len > sizeof(bs->exact_filename)) {
+ /* Name is too long to represent exactly, so leave it empty. */
+ bs->exact_filename[0] = '\0';
}
}
if (ret < 0 && errno != EAGAIN) {
if (tcp_chr_read_poll(chr) <= 0) {
+ /* Perform disconnect and return error. */
tcp_chr_disconnect_locked(chr);
- return len;
} /* else let the read handler finish it properly */
}
return ret;
} else {
- /* XXX: indicate an error ? */
- return len;
+ /* Indicate an error. */
+ errno = EIO;
+ return -1;
}
}
fi
if test "$vhost_vsock" = "yes" ; then
echo "CONFIG_VHOST_VSOCK=y" >> $config_host_mak
+ if test "$vhost_user" = "yes" ; then
+ echo "CONFIG_VHOST_USER_VSOCK=y" >> $config_host_mak
+ fi
fi
if test "$vhost_kernel" = "yes" ; then
echo "CONFIG_VHOST_KERNEL=y" >> $config_host_mak
REQ(VHOST_USER_SET_INFLIGHT_FD),
REQ(VHOST_USER_GPU_SET_SOCKET),
REQ(VHOST_USER_VRING_KICK),
+ REQ(VHOST_USER_GET_MAX_MEM_SLOTS),
+ REQ(VHOST_USER_ADD_MEM_REG),
+ REQ(VHOST_USER_REM_MEM_REG),
REQ(VHOST_USER_MAX),
};
#undef REQ
static bool
vu_message_read(VuDev *dev, int conn_fd, VhostUserMsg *vmsg)
{
- char control[CMSG_SPACE(VHOST_MEMORY_MAX_NREGIONS * sizeof(int))] = { };
+ char control[CMSG_SPACE(VHOST_MEMORY_BASELINE_NREGIONS * sizeof(int))] = {};
struct iovec iov = {
.iov_base = (char *)vmsg,
.iov_len = VHOST_USER_HDR_SIZE,
{
int rc;
uint8_t *p = (uint8_t *)vmsg;
- char control[CMSG_SPACE(VHOST_MEMORY_MAX_NREGIONS * sizeof(int))] = { };
+ char control[CMSG_SPACE(VHOST_MEMORY_BASELINE_NREGIONS * sizeof(int))] = {};
struct iovec iov = {
.iov_base = (char *)vmsg,
.iov_len = VHOST_USER_HDR_SIZE,
struct cmsghdr *cmsg;
memset(control, 0, sizeof(control));
- assert(vmsg->fd_num <= VHOST_MEMORY_MAX_NREGIONS);
+ assert(vmsg->fd_num <= VHOST_MEMORY_BASELINE_NREGIONS);
if (vmsg->fd_num > 0) {
size_t fdsize = vmsg->fd_num * sizeof(int);
msg.msg_controllen = CMSG_SPACE(fdsize);
vu_get_features_exec(VuDev *dev, VhostUserMsg *vmsg)
{
vmsg->payload.u64 =
+ /*
+ * The following VIRTIO feature bits are supported by our virtqueue
+ * implementation:
+ */
+ 1ULL << VIRTIO_F_NOTIFY_ON_EMPTY |
+ 1ULL << VIRTIO_RING_F_INDIRECT_DESC |
+ 1ULL << VIRTIO_RING_F_EVENT_IDX |
+ 1ULL << VIRTIO_F_VERSION_1 |
+
+ /* vhost-user feature bits */
1ULL << VHOST_F_LOG_ALL |
1ULL << VHOST_USER_F_PROTOCOL_FEATURES;
return !(vq->vring.desc && vq->vring.used && vq->vring.avail);
}
+static bool
+generate_faults(VuDev *dev) {
+ int i;
+ for (i = 0; i < dev->nregions; i++) {
+ VuDevRegion *dev_region = &dev->regions[i];
+ int ret;
+#ifdef UFFDIO_REGISTER
+ /*
+ * We should already have an open ufd. Mark each memory
+ * range as ufd.
+ * Discard any mapping we have here; note I can't use MADV_REMOVE
+ * or fallocate to make the hole since I don't want to lose
+ * data that's already arrived in the shared process.
+ * TODO: How to do hugepage
+ */
+ ret = madvise((void *)(uintptr_t)dev_region->mmap_addr,
+ dev_region->size + dev_region->mmap_offset,
+ MADV_DONTNEED);
+ if (ret) {
+ fprintf(stderr,
+ "%s: Failed to madvise(DONTNEED) region %d: %s\n",
+ __func__, i, strerror(errno));
+ }
+ /*
+ * Turn off transparent hugepages so we dont get lose wakeups
+ * in neighbouring pages.
+ * TODO: Turn this backon later.
+ */
+ ret = madvise((void *)(uintptr_t)dev_region->mmap_addr,
+ dev_region->size + dev_region->mmap_offset,
+ MADV_NOHUGEPAGE);
+ if (ret) {
+ /*
+ * Note: This can happen legally on kernels that are configured
+ * without madvise'able hugepages
+ */
+ fprintf(stderr,
+ "%s: Failed to madvise(NOHUGEPAGE) region %d: %s\n",
+ __func__, i, strerror(errno));
+ }
+ struct uffdio_register reg_struct;
+ reg_struct.range.start = (uintptr_t)dev_region->mmap_addr;
+ reg_struct.range.len = dev_region->size + dev_region->mmap_offset;
+ reg_struct.mode = UFFDIO_REGISTER_MODE_MISSING;
+
+ if (ioctl(dev->postcopy_ufd, UFFDIO_REGISTER, ®_struct)) {
+ vu_panic(dev, "%s: Failed to userfault region %d "
+ "@%p + size:%zx offset: %zx: (ufd=%d)%s\n",
+ __func__, i,
+ dev_region->mmap_addr,
+ dev_region->size, dev_region->mmap_offset,
+ dev->postcopy_ufd, strerror(errno));
+ return false;
+ }
+ if (!(reg_struct.ioctls & ((__u64)1 << _UFFDIO_COPY))) {
+ vu_panic(dev, "%s Region (%d) doesn't support COPY",
+ __func__, i);
+ return false;
+ }
+ DPRINT("%s: region %d: Registered userfault for %"
+ PRIx64 " + %" PRIx64 "\n", __func__, i,
+ (uint64_t)reg_struct.range.start,
+ (uint64_t)reg_struct.range.len);
+ /* Now it's registered we can let the client at it */
+ if (mprotect((void *)(uintptr_t)dev_region->mmap_addr,
+ dev_region->size + dev_region->mmap_offset,
+ PROT_READ | PROT_WRITE)) {
+ vu_panic(dev, "failed to mprotect region %d for postcopy (%s)",
+ i, strerror(errno));
+ return false;
+ }
+ /* TODO: Stash 'zero' support flags somewhere */
+#endif
+ }
+
+ return true;
+}
+
+static bool
+vu_add_mem_reg(VuDev *dev, VhostUserMsg *vmsg) {
+ int i;
+ bool track_ramblocks = dev->postcopy_listening;
+ VhostUserMemoryRegion m = vmsg->payload.memreg.region, *msg_region = &m;
+ VuDevRegion *dev_region = &dev->regions[dev->nregions];
+ void *mmap_addr;
+
+ /*
+ * If we are in postcopy mode and we receive a u64 payload with a 0 value
+ * we know all the postcopy client bases have been recieved, and we
+ * should start generating faults.
+ */
+ if (track_ramblocks &&
+ vmsg->size == sizeof(vmsg->payload.u64) &&
+ vmsg->payload.u64 == 0) {
+ (void)generate_faults(dev);
+ return false;
+ }
+
+ DPRINT("Adding region: %d\n", dev->nregions);
+ DPRINT(" guest_phys_addr: 0x%016"PRIx64"\n",
+ msg_region->guest_phys_addr);
+ DPRINT(" memory_size: 0x%016"PRIx64"\n",
+ msg_region->memory_size);
+ DPRINT(" userspace_addr 0x%016"PRIx64"\n",
+ msg_region->userspace_addr);
+ DPRINT(" mmap_offset 0x%016"PRIx64"\n",
+ msg_region->mmap_offset);
+
+ dev_region->gpa = msg_region->guest_phys_addr;
+ dev_region->size = msg_region->memory_size;
+ dev_region->qva = msg_region->userspace_addr;
+ dev_region->mmap_offset = msg_region->mmap_offset;
+
+ /*
+ * We don't use offset argument of mmap() since the
+ * mapped address has to be page aligned, and we use huge
+ * pages.
+ */
+ if (track_ramblocks) {
+ /*
+ * In postcopy we're using PROT_NONE here to catch anyone
+ * accessing it before we userfault.
+ */
+ mmap_addr = mmap(0, dev_region->size + dev_region->mmap_offset,
+ PROT_NONE, MAP_SHARED,
+ vmsg->fds[0], 0);
+ } else {
+ mmap_addr = mmap(0, dev_region->size + dev_region->mmap_offset,
+ PROT_READ | PROT_WRITE, MAP_SHARED, vmsg->fds[0],
+ 0);
+ }
+
+ if (mmap_addr == MAP_FAILED) {
+ vu_panic(dev, "region mmap error: %s", strerror(errno));
+ } else {
+ dev_region->mmap_addr = (uint64_t)(uintptr_t)mmap_addr;
+ DPRINT(" mmap_addr: 0x%016"PRIx64"\n",
+ dev_region->mmap_addr);
+ }
+
+ close(vmsg->fds[0]);
+
+ if (track_ramblocks) {
+ /*
+ * Return the address to QEMU so that it can translate the ufd
+ * fault addresses back.
+ */
+ msg_region->userspace_addr = (uintptr_t)(mmap_addr +
+ dev_region->mmap_offset);
+
+ /* Send the message back to qemu with the addresses filled in. */
+ vmsg->fd_num = 0;
+ if (!vu_send_reply(dev, dev->sock, vmsg)) {
+ vu_panic(dev, "failed to respond to add-mem-region for postcopy");
+ return false;
+ }
+
+ DPRINT("Successfully added new region in postcopy\n");
+ dev->nregions++;
+ return false;
+
+ } else {
+ for (i = 0; i < dev->max_queues; i++) {
+ if (dev->vq[i].vring.desc) {
+ if (map_ring(dev, &dev->vq[i])) {
+ vu_panic(dev, "remapping queue %d for new memory region",
+ i);
+ }
+ }
+ }
+
+ DPRINT("Successfully added new region\n");
+ dev->nregions++;
+ vmsg_set_reply_u64(vmsg, 0);
+ return true;
+ }
+}
+
+static inline bool reg_equal(VuDevRegion *vudev_reg,
+ VhostUserMemoryRegion *msg_reg)
+{
+ if (vudev_reg->gpa == msg_reg->guest_phys_addr &&
+ vudev_reg->qva == msg_reg->userspace_addr &&
+ vudev_reg->size == msg_reg->memory_size) {
+ return true;
+ }
+
+ return false;
+}
+
+static bool
+vu_rem_mem_reg(VuDev *dev, VhostUserMsg *vmsg) {
+ int i, j;
+ bool found = false;
+ VuDevRegion shadow_regions[VHOST_USER_MAX_RAM_SLOTS] = {};
+ VhostUserMemoryRegion m = vmsg->payload.memreg.region, *msg_region = &m;
+
+ DPRINT("Removing region:\n");
+ DPRINT(" guest_phys_addr: 0x%016"PRIx64"\n",
+ msg_region->guest_phys_addr);
+ DPRINT(" memory_size: 0x%016"PRIx64"\n",
+ msg_region->memory_size);
+ DPRINT(" userspace_addr 0x%016"PRIx64"\n",
+ msg_region->userspace_addr);
+ DPRINT(" mmap_offset 0x%016"PRIx64"\n",
+ msg_region->mmap_offset);
+
+ for (i = 0, j = 0; i < dev->nregions; i++) {
+ if (!reg_equal(&dev->regions[i], msg_region)) {
+ shadow_regions[j].gpa = dev->regions[i].gpa;
+ shadow_regions[j].size = dev->regions[i].size;
+ shadow_regions[j].qva = dev->regions[i].qva;
+ shadow_regions[j].mmap_offset = dev->regions[i].mmap_offset;
+ j++;
+ } else {
+ found = true;
+ VuDevRegion *r = &dev->regions[i];
+ void *m = (void *) (uintptr_t) r->mmap_addr;
+
+ if (m) {
+ munmap(m, r->size + r->mmap_offset);
+ }
+ }
+ }
+
+ if (found) {
+ memcpy(dev->regions, shadow_regions,
+ sizeof(VuDevRegion) * VHOST_USER_MAX_RAM_SLOTS);
+ DPRINT("Successfully removed a region\n");
+ dev->nregions--;
+ vmsg_set_reply_u64(vmsg, 0);
+ } else {
+ vu_panic(dev, "Specified region not found\n");
+ }
+
+ return true;
+}
+
static bool
vu_set_mem_table_exec_postcopy(VuDev *dev, VhostUserMsg *vmsg)
{
}
/* OK, now we can go and register the memory and generate faults */
- for (i = 0; i < dev->nregions; i++) {
- VuDevRegion *dev_region = &dev->regions[i];
- int ret;
-#ifdef UFFDIO_REGISTER
- /* We should already have an open ufd. Mark each memory
- * range as ufd.
- * Discard any mapping we have here; note I can't use MADV_REMOVE
- * or fallocate to make the hole since I don't want to lose
- * data that's already arrived in the shared process.
- * TODO: How to do hugepage
- */
- ret = madvise((void *)(uintptr_t)dev_region->mmap_addr,
- dev_region->size + dev_region->mmap_offset,
- MADV_DONTNEED);
- if (ret) {
- fprintf(stderr,
- "%s: Failed to madvise(DONTNEED) region %d: %s\n",
- __func__, i, strerror(errno));
- }
- /* Turn off transparent hugepages so we dont get lose wakeups
- * in neighbouring pages.
- * TODO: Turn this backon later.
- */
- ret = madvise((void *)(uintptr_t)dev_region->mmap_addr,
- dev_region->size + dev_region->mmap_offset,
- MADV_NOHUGEPAGE);
- if (ret) {
- /* Note: This can happen legally on kernels that are configured
- * without madvise'able hugepages
- */
- fprintf(stderr,
- "%s: Failed to madvise(NOHUGEPAGE) region %d: %s\n",
- __func__, i, strerror(errno));
- }
- struct uffdio_register reg_struct;
- reg_struct.range.start = (uintptr_t)dev_region->mmap_addr;
- reg_struct.range.len = dev_region->size + dev_region->mmap_offset;
- reg_struct.mode = UFFDIO_REGISTER_MODE_MISSING;
-
- if (ioctl(dev->postcopy_ufd, UFFDIO_REGISTER, ®_struct)) {
- vu_panic(dev, "%s: Failed to userfault region %d "
- "@%p + size:%zx offset: %zx: (ufd=%d)%s\n",
- __func__, i,
- dev_region->mmap_addr,
- dev_region->size, dev_region->mmap_offset,
- dev->postcopy_ufd, strerror(errno));
- return false;
- }
- if (!(reg_struct.ioctls & ((__u64)1 << _UFFDIO_COPY))) {
- vu_panic(dev, "%s Region (%d) doesn't support COPY",
- __func__, i);
- return false;
- }
- DPRINT("%s: region %d: Registered userfault for %"
- PRIx64 " + %" PRIx64 "\n", __func__, i,
- (uint64_t)reg_struct.range.start,
- (uint64_t)reg_struct.range.len);
- /* Now it's registered we can let the client at it */
- if (mprotect((void *)(uintptr_t)dev_region->mmap_addr,
- dev_region->size + dev_region->mmap_offset,
- PROT_READ | PROT_WRITE)) {
- vu_panic(dev, "failed to mprotect region %d for postcopy (%s)",
- i, strerror(errno));
- return false;
- }
- /* TODO: Stash 'zero' support flags somewhere */
-#endif
- }
+ (void)generate_faults(dev);
return false;
}
1ULL << VHOST_USER_PROTOCOL_F_SLAVE_REQ |
1ULL << VHOST_USER_PROTOCOL_F_HOST_NOTIFIER |
1ULL << VHOST_USER_PROTOCOL_F_SLAVE_SEND_FD |
- 1ULL << VHOST_USER_PROTOCOL_F_REPLY_ACK;
+ 1ULL << VHOST_USER_PROTOCOL_F_REPLY_ACK |
+ 1ULL << VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS;
if (have_userfault()) {
features |= 1ULL << VHOST_USER_PROTOCOL_F_PAGEFAULT;
return false;
}
+static bool vu_handle_get_max_memslots(VuDev *dev, VhostUserMsg *vmsg)
+{
+ vmsg->flags = VHOST_USER_REPLY_MASK | VHOST_USER_VERSION;
+ vmsg->size = sizeof(vmsg->payload.u64);
+ vmsg->payload.u64 = VHOST_USER_MAX_RAM_SLOTS;
+ vmsg->fd_num = 0;
+
+ if (!vu_message_write(dev, dev->sock, vmsg)) {
+ vu_panic(dev, "Failed to send max ram slots: %s\n", strerror(errno));
+ }
+
+ DPRINT("u64: 0x%016"PRIx64"\n", (uint64_t) VHOST_USER_MAX_RAM_SLOTS);
+
+ return false;
+}
+
static bool
vu_process_message(VuDev *dev, VhostUserMsg *vmsg)
{
return vu_set_inflight_fd(dev, vmsg);
case VHOST_USER_VRING_KICK:
return vu_handle_vring_kick(dev, vmsg);
+ case VHOST_USER_GET_MAX_MEM_SLOTS:
+ return vu_handle_get_max_memslots(dev, vmsg);
+ case VHOST_USER_ADD_MEM_REG:
+ return vu_add_mem_reg(dev, vmsg);
+ case VHOST_USER_REM_MEM_REG:
+ return vu_rem_mem_reg(dev, vmsg);
default:
vmsg_close_fds(vmsg);
vu_panic(dev, "Unhandled request: %d", vmsg->request);
#define VIRTQUEUE_MAX_SIZE 1024
-#define VHOST_MEMORY_MAX_NREGIONS 8
+#define VHOST_MEMORY_BASELINE_NREGIONS 8
+
+/*
+ * Set a reasonable maximum number of ram slots, which will be supported by
+ * any architecture.
+ */
+#define VHOST_USER_MAX_RAM_SLOTS 32
typedef enum VhostSetConfigType {
VHOST_SET_CONFIG_TYPE_MASTER = 0,
VHOST_USER_PROTOCOL_F_HOST_NOTIFIER = 11,
VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD = 12,
VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS = 14,
+ VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS = 15,
VHOST_USER_PROTOCOL_F_MAX
};
VHOST_USER_SET_INFLIGHT_FD = 32,
VHOST_USER_GPU_SET_SOCKET = 33,
VHOST_USER_VRING_KICK = 35,
+ VHOST_USER_GET_MAX_MEM_SLOTS = 36,
+ VHOST_USER_ADD_MEM_REG = 37,
+ VHOST_USER_REM_MEM_REG = 38,
VHOST_USER_MAX
} VhostUserRequest;
typedef struct VhostUserMemory {
uint32_t nregions;
uint32_t padding;
- VhostUserMemoryRegion regions[VHOST_MEMORY_MAX_NREGIONS];
+ VhostUserMemoryRegion regions[VHOST_MEMORY_BASELINE_NREGIONS];
} VhostUserMemory;
+typedef struct VhostUserMemRegMsg {
+ uint32_t padding;
+ VhostUserMemoryRegion region;
+} VhostUserMemRegMsg;
+
typedef struct VhostUserLog {
uint64_t mmap_size;
uint64_t mmap_offset;
struct vhost_vring_state state;
struct vhost_vring_addr addr;
VhostUserMemory memory;
+ VhostUserMemRegMsg memreg;
VhostUserLog log;
VhostUserConfig config;
VhostUserVringArea area;
VhostUserInflight inflight;
} payload;
- int fds[VHOST_MEMORY_MAX_NREGIONS];
+ int fds[VHOST_MEMORY_BASELINE_NREGIONS];
int fd_num;
uint8_t *data;
} VU_PACKED VhostUserMsg;
struct VuDev {
int sock;
uint32_t nregions;
- VuDevRegion regions[VHOST_MEMORY_MAX_NREGIONS];
+ VuDevRegion regions[VHOST_USER_MAX_RAM_SLOTS];
VuVirtq *vq;
VuDevInflightInfo inflight_info;
int log_call_fd;
1ull << VIRTIO_BLK_F_DISCARD |
1ull << VIRTIO_BLK_F_WRITE_ZEROES |
#endif
- 1ull << VIRTIO_BLK_F_CONFIG_WCE |
- 1ull << VIRTIO_F_VERSION_1 |
- 1ull << VHOST_USER_F_PROTOCOL_FEATURES;
+ 1ull << VIRTIO_BLK_F_CONFIG_WCE;
if (vdev_blk->enable_ro) {
features |= 1ull << VIRTIO_BLK_F_RO;
# Boards:
#
CONFIG_PUV3=y
+CONFIG_SEMIHOSTING=y
#define VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD 12
#define VHOST_USER_PROTOCOL_F_RESET_DEVICE 13
#define VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS 14
+ #define VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS 15
Master message types
--------------------
The state.num field is currently reserved and must be set to 0.
+``VHOST_USER_GET_MAX_MEM_SLOTS``
+ :id: 36
+ :equivalent ioctl: N/A
+ :slave payload: u64
+
+ When the ``VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS`` protocol
+ feature has been successfully negotiated, this message is submitted
+ by master to the slave. The slave should return the message with a
+ u64 payload containing the maximum number of memory slots for
+ QEMU to expose to the guest. The value returned by the backend
+ will be capped at the maximum number of ram slots which can be
+ supported by the target platform.
+
+``VHOST_USER_ADD_MEM_REG``
+ :id: 37
+ :equivalent ioctl: N/A
+ :slave payload: memory region
+
+ When the ``VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS`` protocol
+ feature has been successfully negotiated, this message is submitted
+ by the master to the slave. The message payload contains a memory
+ region descriptor struct, describing a region of guest memory which
+ the slave device must map in. When the
+ ``VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS`` protocol feature has
+ been successfully negotiated, along with the
+ ``VHOST_USER_REM_MEM_REG`` message, this message is used to set and
+ update the memory tables of the slave device.
+
+``VHOST_USER_REM_MEM_REG``
+ :id: 38
+ :equivalent ioctl: N/A
+ :slave payload: memory region
+
+ When the ``VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS`` protocol
+ feature has been successfully negotiated, this message is submitted
+ by the master to the slave. The message payload contains a memory
+ region descriptor struct, describing a region of guest memory which
+ the slave device must unmap. When the
+ ``VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS`` protocol feature has
+ been successfully negotiated, along with the
+ ``VHOST_USER_ADD_MEM_REG`` message, this message is used to set and
+ update the memory tables of the slave device.
+
Slave message types
-------------------
``--disable`` to change *BITMAP* to stop recording future edits.
- ``--merge`` to merge the contents of *SOURCE_BITMAP* into *BITMAP*.
+ ``--merge`` to merge the contents of the *SOURCE* bitmap into *BITMAP*.
Additional options include ``-g`` which sets a non-default
*GRANULARITY* for ``--add``, and ``-b`` and ``-F`` which select an
int flags, CPUWatchpoint **watchpoint)
{
CPUWatchpoint *wp;
+ vaddr in_page;
/* forbid ranges which are empty or run off the end of the address space */
if (len == 0 || (addr + len - 1) < addr) {
QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
}
- tlb_flush_page(cpu, addr);
+ in_page = -(addr | TARGET_PAGE_MASK);
+ if (len <= in_page) {
+ tlb_flush_page(cpu, addr);
+ } else {
+ tlb_flush(cpu);
+ }
if (watchpoint)
*watchpoint = wp;
#include "qemu/bitops.h"
#include "sysemu/numa.h"
#include "hw/boards.h"
+#include "hw/acpi/tpm.h"
static GArray *build_alloc_array(void)
{
}
/* SLEEP_CONTROL_REG */
- build_append_gas(tbl, AML_AS_SYSTEM_MEMORY, 0 , 0, 0, 0);
+ build_append_gas_from_struct(tbl, &f->sleep_ctl);
/* SLEEP_STATUS_REG */
- build_append_gas(tbl, AML_AS_SYSTEM_MEMORY, 0 , 0, 0, 0);
+ build_append_gas_from_struct(tbl, &f->sleep_sts);
/* TODO: extra fields need to be added to support revisions above rev5 */
assert(f->rev == 5);
"FACP", tbl->len - fadt_start, f->rev, oem_id, oem_table_id);
}
+void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
+{
+ Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof(AcpiTableHeader));
+ unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
+ unsigned log_addr_offset =
+ (char *)&tpm2_ptr->log_area_start_address - table_data->data;
+ uint8_t start_method_params[12] = {};
+ TPMIf *tpmif = tpm_find();
+
+ /* platform class */
+ build_append_int_noprefix(table_data, TPM2_ACPI_CLASS_CLIENT, 2);
+ /* reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ if (TPM_IS_TIS_ISA(tpmif) || TPM_IS_TIS_SYSBUS(tpmif)) {
+ /* address of control area */
+ build_append_int_noprefix(table_data, 0, 8);
+ /* start method */
+ build_append_int_noprefix(table_data, TPM2_START_METHOD_MMIO, 4);
+ } else if (TPM_IS_CRB(tpmif)) {
+ build_append_int_noprefix(table_data, TPM_CRB_ADDR_CTRL, 8);
+ build_append_int_noprefix(table_data, TPM2_START_METHOD_CRB, 4);
+ } else {
+ g_warn_if_reached();
+ }
+
+ /* platform specific parameters */
+ g_array_append_vals(table_data, &start_method_params, 12);
+
+ /* log area minimum length */
+ build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
+
+ acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
+ bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
+ false);
+
+ /* log area start address to be filled by Guest linker */
+ build_append_int_noprefix(table_data, 0, 8);
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+ log_addr_offset, log_addr_size,
+ ACPI_BUILD_TPMLOG_FILE, 0);
+ build_header(linker, table_data,
+ (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
+}
+
/* ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors */
static Aml *aml_serial_bus_device(uint8_t serial_bus_type, uint8_t flags,
uint16_t type_flags,
}
/* Memory read by the GED _EVT AML dynamic method */
-static uint64_t ged_read(void *opaque, hwaddr addr, unsigned size)
+static uint64_t ged_evt_read(void *opaque, hwaddr addr, unsigned size)
{
uint64_t val = 0;
GEDState *ged_st = opaque;
}
/* Nothing is expected to be written to the GED memory region */
-static void ged_write(void *opaque, hwaddr addr, uint64_t data,
- unsigned int size)
+static void ged_evt_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
{
}
-static const MemoryRegionOps ged_ops = {
- .read = ged_read,
- .write = ged_write,
+static const MemoryRegionOps ged_evt_ops = {
+ .read = ged_evt_read,
+ .write = ged_evt_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
GEDState *ged_st = &s->ged_state;
- memory_region_init_io(&ged_st->io, obj, &ged_ops, ged_st,
+ memory_region_init_io(&ged_st->evt, obj, &ged_evt_ops, ged_st,
TYPE_ACPI_GED, ACPI_GED_EVT_SEL_LEN);
- sysbus_init_mmio(sbd, &ged_st->io);
+ sysbus_init_mmio(sbd, &ged_st->evt);
sysbus_init_irq(sbd, &s->irq);
#include "qemu/osdep.h"
#include "qemu/uuid.h"
+#include "qapi/error.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/bios-linker-loader.h"
free_aml_allocator();
}
+void nvdimm_build_srat(GArray *table_data)
+{
+ GSList *device_list = nvdimm_get_device_list();
+
+ for (; device_list; device_list = device_list->next) {
+ AcpiSratMemoryAffinity *numamem = NULL;
+ DeviceState *dev = device_list->data;
+ Object *obj = OBJECT(dev);
+ uint64_t addr, size;
+ int node;
+
+ node = object_property_get_int(obj, PC_DIMM_NODE_PROP, &error_abort);
+ addr = object_property_get_uint(obj, PC_DIMM_ADDR_PROP, &error_abort);
+ size = object_property_get_uint(obj, PC_DIMM_SIZE_PROP, &error_abort);
+
+ numamem = acpi_data_push(table_data, sizeof *numamem);
+ build_srat_memory(numamem, addr, size, node,
+ MEM_AFFINITY_ENABLED | MEM_AFFINITY_NON_VOLATILE);
+ }
+ g_slist_free(device_list);
+}
+
void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, NVDIMMState *state,
uint32_t ram_slots)
bmc = g_new0(AspeedBoardState, 1);
memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
- UINT32_MAX);
+ 4 * GiB);
memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
#include "hw/acpi/pci.h"
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/generic_event_device.h"
+#include "hw/acpi/tpm.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci.h"
#include "hw/arm/virt.h"
#include "hw/mem/nvdimm.h"
#include "sysemu/numa.h"
#include "sysemu/reset.h"
+#include "sysemu/tpm.h"
#include "kvm_arm.h"
#include "migration/vmstate.h"
#include "hw/acpi/ghes.h"
}
}
+ if (ms->nvdimms_state->is_enabled) {
+ nvdimm_build_srat(table_data);
+ }
+
if (ms->device_memory) {
numamem = acpi_data_push(table_data, sizeof *numamem);
build_srat_memory(numamem, ms->device_memory->base,
build_iort(tables_blob, tables->linker, vms);
}
+ if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_tpm2(tables_blob, tables->linker, tables->tcpalog);
+ }
+
/* XSDT is pointed to by RSDP */
xsdt = tables_blob->len;
build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
vhost_dev_cleanup(&s->dev);
}
+static void vhost_user_blk_event(void *opaque, QEMUChrEvent event);
+
+static void vhost_user_blk_chr_closed_bh(void *opaque)
+{
+ DeviceState *dev = opaque;
+ VirtIODevice *vdev = VIRTIO_DEVICE(dev);
+ VHostUserBlk *s = VHOST_USER_BLK(vdev);
+
+ vhost_user_blk_disconnect(dev);
+ qemu_chr_fe_set_handlers(&s->chardev, NULL, NULL, vhost_user_blk_event,
+ NULL, opaque, NULL, true);
+}
+
static void vhost_user_blk_event(void *opaque, QEMUChrEvent event)
{
DeviceState *dev = opaque;
}
break;
case CHR_EVENT_CLOSED:
- vhost_user_blk_disconnect(dev);
+ /*
+ * A close event may happen during a read/write, but vhost
+ * code assumes the vhost_dev remains setup, so delay the
+ * stop & clear. There are two possible paths to hit this
+ * disconnect event:
+ * 1. When VM is in the RUN_STATE_PRELAUNCH state. The
+ * vhost_user_blk_device_realize() is a caller.
+ * 2. In tha main loop phase after VM start.
+ *
+ * For p2 the disconnect event will be delayed. We can't
+ * do the same for p1, because we are not running the loop
+ * at this moment. So just skip this step and perform
+ * disconnect in the caller function.
+ *
+ * TODO: maybe it is a good idea to make the same fix
+ * for other vhost-user devices.
+ */
+ if (runstate_is_running()) {
+ AioContext *ctx = qemu_get_current_aio_context();
+
+ qemu_chr_fe_set_handlers(&s->chardev, NULL, NULL, NULL, NULL,
+ NULL, NULL, false);
+ aio_bh_schedule_oneshot(ctx, vhost_user_blk_chr_closed_bh, opaque);
+ }
break;
case CHR_EVENT_BREAK:
case CHR_EVENT_MUX_IN:
#include "qemu/module.h"
#include "chardev/char-parallel.h"
#include "chardev/char-fe.h"
+#include "hw/acpi/aml-build.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
s, "parallel");
}
+static void parallel_isa_build_aml(ISADevice *isadev, Aml *scope)
+{
+ ISAParallelState *isa = ISA_PARALLEL(isadev);
+ Aml *dev;
+ Aml *crs;
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_io(AML_DECODE16, isa->iobase, isa->iobase, 0x08, 0x08));
+ aml_append(crs, aml_irq_no_flags(isa->isairq));
+
+ dev = aml_device("LPT%d", isa->index + 1);
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(isa->index + 1)));
+ aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ aml_append(scope, dev);
+}
+
/* Memory mapped interface */
static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size)
{
static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
dc->realize = parallel_isa_realizefn;
dc->vmsd = &vmstate_parallel_isa;
+ isa->build_aml = parallel_isa_build_aml;
device_class_set_props(dc, parallel_isa_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/sysemu.h"
+#include "hw/acpi/aml-build.h"
#include "hw/char/serial.h"
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
isa_register_ioport(isadev, &s->io, isa->iobase);
}
+static void serial_isa_build_aml(ISADevice *isadev, Aml *scope)
+{
+ ISASerialState *isa = ISA_SERIAL(isadev);
+ Aml *dev;
+ Aml *crs;
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_io(AML_DECODE16, isa->iobase, isa->iobase, 0x00, 0x08));
+ aml_append(crs, aml_irq_no_flags(isa->isairq));
+
+ dev = aml_device("COM%d", isa->index + 1);
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(isa->index + 1)));
+ aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ aml_append(scope, dev);
+}
+
static const VMStateDescription vmstate_isa_serial = {
.name = "serial",
.version_id = 3,
static void serial_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
dc->realize = serial_isa_realizefn;
dc->vmsd = &vmstate_isa_serial;
+ isa->build_aml = serial_isa_build_aml;
device_class_set_props(dc, serial_isa_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
#include "hw/mem/nvdimm.h"
#include "migration/vmstate.h"
-GlobalProperty hw_compat_5_0[] = {};
+GlobalProperty hw_compat_5_0[] = {
+ { "virtio-balloon-device", "page-poison", "false" },
+};
const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0);
GlobalProperty hw_compat_4_2[] = {
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define PUV3_DMA_CH_NR (6)
#define PUV3_DMA_CH_MASK (0xff)
ret = s->reg_CFG[PUV3_DMA_CH(offset)];
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
s->reg_CFG[PUV3_DMA_CH(offset)] = value;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
}
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define TYPE_PUV3_GPIO "puv3_gpio"
#define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO)
ret = s->reg_GPIR;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
if (s->reg_GPDR & value) {
s->reg_GPLR |= value;
} else {
- DPRINTF("Write gpio input port error!");
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
+ __func__);
}
break;
case 0x0c:
if (s->reg_GPDR & value) {
s->reg_GPLR &= ~value;
} else {
- DPRINTF("Write gpio input port error!");
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
+ __func__);
}
break;
case 0x10: /* GRER */
s->reg_GPIR = value;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
}
&s->parent_obj.data_mem);
/* Dino PCI bus memory. */
- memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32);
+ memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 4 * GiB);
b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
&s->pci_mem, get_system_io(),
}
/* Set up PCI view of memory: Bus master address space. */
- memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32);
+ memory_region_init(&s->bm, OBJECT(s), "bm-dino", 4 * GiB);
memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
"bm-system", addr_space, 0,
0xf0000000 + DINO_MEM_CHUNK_SIZE);
obj-$(CONFIG_PC) += port92.o
obj-y += kvmvapic.o
+obj-$(CONFIG_ACPI) += acpi-common.o
obj-$(CONFIG_PC) += acpi-build.o
#include "qapi/error.h"
#include "qapi/qmp/qnum.h"
#include "acpi-build.h"
+#include "acpi-common.h"
#include "qemu/bitmap.h"
#include "qemu/error-report.h"
#include "hw/pci/pci.h"
#define ACPI_BUILD_DPRINTF(fmt, ...)
#endif
-/* Default IOAPIC ID */
-#define ACPI_BUILD_IOAPIC_ID 0x0
-
typedef struct AcpiPmInfo {
bool s3_disabled;
bool s4_disabled;
facs->length = cpu_to_le32(sizeof(*facs));
}
-void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
- const CPUArchIdList *apic_ids, GArray *entry)
-{
- uint32_t apic_id = apic_ids->cpus[uid].arch_id;
-
- /* ACPI spec says that LAPIC entry for non present
- * CPU may be omitted from MADT or it must be marked
- * as disabled. However omitting non present CPU from
- * MADT breaks hotplug on linux. So possible CPUs
- * should be put in MADT but kept disabled.
- */
- if (apic_id < 255) {
- AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
-
- apic->type = ACPI_APIC_PROCESSOR;
- apic->length = sizeof(*apic);
- apic->processor_id = uid;
- apic->local_apic_id = apic_id;
- if (apic_ids->cpus[uid].cpu != NULL) {
- apic->flags = cpu_to_le32(1);
- } else {
- apic->flags = cpu_to_le32(0);
- }
- } else {
- AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
-
- apic->type = ACPI_APIC_LOCAL_X2APIC;
- apic->length = sizeof(*apic);
- apic->uid = cpu_to_le32(uid);
- apic->x2apic_id = cpu_to_le32(apic_id);
- if (apic_ids->cpus[uid].cpu != NULL) {
- apic->flags = cpu_to_le32(1);
- } else {
- apic->flags = cpu_to_le32(0);
- }
- }
-}
-
-static void
-build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
-{
- MachineClass *mc = MACHINE_GET_CLASS(pcms);
- X86MachineState *x86ms = X86_MACHINE(pcms);
- const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
- int madt_start = table_data->len;
- AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
- AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
- bool x2apic_mode = false;
-
- AcpiMultipleApicTable *madt;
- AcpiMadtIoApic *io_apic;
- AcpiMadtIntsrcovr *intsrcovr;
- int i;
-
- madt = acpi_data_push(table_data, sizeof *madt);
- madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
- madt->flags = cpu_to_le32(1);
-
- for (i = 0; i < apic_ids->len; i++) {
- adevc->madt_cpu(adev, i, apic_ids, table_data);
- if (apic_ids->cpus[i].arch_id > 254) {
- x2apic_mode = true;
- }
- }
-
- io_apic = acpi_data_push(table_data, sizeof *io_apic);
- io_apic->type = ACPI_APIC_IO;
- io_apic->length = sizeof(*io_apic);
- io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
- io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
- io_apic->interrupt = cpu_to_le32(0);
-
- if (x86ms->apic_xrupt_override) {
- intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
- intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
- intsrcovr->length = sizeof(*intsrcovr);
- intsrcovr->source = 0;
- intsrcovr->gsi = cpu_to_le32(2);
- intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
- }
- for (i = 1; i < 16; i++) {
-#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
- if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
- /* No need for a INT source override structure. */
- continue;
- }
- intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
- intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
- intsrcovr->length = sizeof(*intsrcovr);
- intsrcovr->source = i;
- intsrcovr->gsi = cpu_to_le32(i);
- intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
- }
-
- if (x2apic_mode) {
- AcpiMadtLocalX2ApicNmi *local_nmi;
-
- local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
- local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
- local_nmi->length = sizeof(*local_nmi);
- local_nmi->uid = 0xFFFFFFFF; /* all processors */
- local_nmi->flags = cpu_to_le16(0);
- local_nmi->lint = 1; /* ACPI_LINT1 */
- } else {
- AcpiMadtLocalNmi *local_nmi;
-
- local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
- local_nmi->type = ACPI_APIC_LOCAL_NMI;
- local_nmi->length = sizeof(*local_nmi);
- local_nmi->processor_id = 0xff; /* all processors */
- local_nmi->flags = cpu_to_le16(0);
- local_nmi->lint = 1; /* ACPI_LINT1 */
- }
-
- build_header(linker, table_data,
- (void *)(table_data->data + madt_start), "APIC",
- table_data->len - madt_start, 1, NULL, NULL);
-}
-
static void build_append_pcihp_notify_entry(Aml *method, int slot)
{
Aml *if_ctx;
return dev;
}
-static Aml *build_rtc_device_aml(void)
-{
- Aml *dev;
- Aml *crs;
-
- dev = aml_device("RTC");
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
- crs = aml_resource_template();
- aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
- aml_append(crs, aml_irq_no_flags(8));
- aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- return dev;
-}
-
static Aml *build_kbd_device_aml(void)
{
Aml *dev;
return dev;
}
-static Aml *build_lpt_device_aml(void)
-{
- Aml *dev;
- Aml *crs;
- Aml *method;
- Aml *if_ctx;
- Aml *else_ctx;
- Aml *zero = aml_int(0);
- Aml *is_present = aml_local(0);
-
- dev = aml_device("LPT");
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
-
- method = aml_method("_STA", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_store(aml_name("LPEN"), is_present));
- if_ctx = aml_if(aml_equal(is_present, zero));
- {
- aml_append(if_ctx, aml_return(aml_int(0x00)));
- }
- aml_append(method, if_ctx);
- else_ctx = aml_else();
- {
- aml_append(else_ctx, aml_return(aml_int(0x0f)));
- }
- aml_append(method, else_ctx);
- aml_append(dev, method);
-
- crs = aml_resource_template();
- aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
- aml_append(crs, aml_irq_no_flags(7));
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- return dev;
-}
-
-static Aml *build_com_device_aml(uint8_t uid)
-{
- Aml *dev;
- Aml *crs;
- Aml *method;
- Aml *if_ctx;
- Aml *else_ctx;
- Aml *zero = aml_int(0);
- Aml *is_present = aml_local(0);
- const char *enabled_field = "CAEN";
- uint8_t irq = 4;
- uint16_t io_port = 0x03F8;
-
- assert(uid == 1 || uid == 2);
- if (uid == 2) {
- enabled_field = "CBEN";
- irq = 3;
- io_port = 0x02F8;
- }
-
- dev = aml_device("COM%d", uid);
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
- aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
-
- method = aml_method("_STA", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
- if_ctx = aml_if(aml_equal(is_present, zero));
- {
- aml_append(if_ctx, aml_return(aml_int(0x00)));
- }
- aml_append(method, if_ctx);
- else_ctx = aml_else();
- {
- aml_append(else_ctx, aml_return(aml_int(0x0f)));
- }
- aml_append(method, else_ctx);
- aml_append(dev, method);
-
- crs = aml_resource_template();
- aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
- aml_append(crs, aml_irq_no_flags(irq));
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- return dev;
-}
-
static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
{
Aml *dev;
Aml *scope = aml_scope("_SB.PCI0.ISA");
Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
- aml_append(scope, build_rtc_device_aml());
aml_append(scope, build_kbd_device_aml());
aml_append(scope, build_mouse_device_aml());
if (fdc) {
aml_append(scope, build_fdc_device_aml(fdc));
}
- aml_append(scope, build_lpt_device_aml());
- aml_append(scope, build_com_device_aml(1));
- aml_append(scope, build_com_device_aml(2));
if (ambiguous) {
error_report("Multiple ISA busses, unable to define IPMI ACPI data");
(void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
}
-static void
-build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
-{
- Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
- unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
- unsigned log_addr_offset =
- (char *)&tpm2_ptr->log_area_start_address - table_data->data;
-
- tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
- if (TPM_IS_TIS_ISA(tpm_find())) {
- tpm2_ptr->control_area_address = cpu_to_le64(0);
- tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
- } else if (TPM_IS_CRB(tpm_find())) {
- tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
- tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
- } else {
- g_warn_if_reached();
- }
-
- tpm2_ptr->log_area_minimum_length =
- cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
-
- /* log area start address to be filled by Guest linker */
- bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
- log_addr_offset, log_addr_size,
- ACPI_BUILD_TPMLOG_FILE, 0);
- build_header(linker, table_data,
- (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
-}
-
#define HOLE_640K_START (640 * KiB)
#define HOLE_640K_END (1 * MiB)
MEM_AFFINITY_ENABLED);
}
}
+
+ if (machine->nvdimms_state->is_enabled) {
+ nvdimm_build_srat(table_data);
+ }
+
slots = (table_data->len - numa_start) / sizeof *numamem;
for (; slots < pcms->numa_nodes + 2; slots++) {
numamem = acpi_data_push(table_data, sizeof *numamem);
aml_len += tables_blob->len - fadt;
acpi_add_table(table_offsets, tables_blob);
- build_madt(tables_blob, tables->linker, pcms);
+ acpi_build_madt(tables_blob, tables->linker, x86ms,
+ ACPI_DEVICE_IF(pcms->acpi_dev), true);
vmgenid_dev = find_vmgenid_dev();
if (vmgenid_dev) {
build_hpet(tables_blob, tables->linker);
}
if (misc.tpm_version != TPM_VERSION_UNSPEC) {
- acpi_add_table(table_offsets, tables_blob);
- build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
-
- if (misc.tpm_version == TPM_VERSION_2_0) {
+ if (misc.tpm_version == TPM_VERSION_1_2) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
+ } else { /* TPM_VERSION_2_0 */
acpi_add_table(table_offsets, tables_blob);
build_tpm2(tables_blob, tables->linker, tables->tcpalog);
}
--- /dev/null
+/* Support for generating ACPI tables and passing them to Guests
+ *
+ * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
+ * Copyright (C) 2006 Fabrice Bellard
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+
+#include "exec/memory.h"
+#include "hw/acpi/acpi.h"
+#include "hw/acpi/aml-build.h"
+#include "hw/acpi/utils.h"
+#include "hw/i386/pc.h"
+#include "target/i386/cpu.h"
+
+#include "acpi-build.h"
+#include "acpi-common.h"
+
+void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
+ const CPUArchIdList *apic_ids, GArray *entry)
+{
+ uint32_t apic_id = apic_ids->cpus[uid].arch_id;
+
+ /* ACPI spec says that LAPIC entry for non present
+ * CPU may be omitted from MADT or it must be marked
+ * as disabled. However omitting non present CPU from
+ * MADT breaks hotplug on linux. So possible CPUs
+ * should be put in MADT but kept disabled.
+ */
+ if (apic_id < 255) {
+ AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
+
+ apic->type = ACPI_APIC_PROCESSOR;
+ apic->length = sizeof(*apic);
+ apic->processor_id = uid;
+ apic->local_apic_id = apic_id;
+ if (apic_ids->cpus[uid].cpu != NULL) {
+ apic->flags = cpu_to_le32(1);
+ } else {
+ apic->flags = cpu_to_le32(0);
+ }
+ } else {
+ AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
+
+ apic->type = ACPI_APIC_LOCAL_X2APIC;
+ apic->length = sizeof(*apic);
+ apic->uid = cpu_to_le32(uid);
+ apic->x2apic_id = cpu_to_le32(apic_id);
+ if (apic_ids->cpus[uid].cpu != NULL) {
+ apic->flags = cpu_to_le32(1);
+ } else {
+ apic->flags = cpu_to_le32(0);
+ }
+ }
+}
+
+void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
+ X86MachineState *x86ms, AcpiDeviceIf *adev,
+ bool has_pci)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(x86ms);
+ const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(x86ms));
+ int madt_start = table_data->len;
+ AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(adev);
+ bool x2apic_mode = false;
+
+ AcpiMultipleApicTable *madt;
+ AcpiMadtIoApic *io_apic;
+ AcpiMadtIntsrcovr *intsrcovr;
+ int i;
+
+ madt = acpi_data_push(table_data, sizeof *madt);
+ madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
+ madt->flags = cpu_to_le32(1);
+
+ for (i = 0; i < apic_ids->len; i++) {
+ adevc->madt_cpu(adev, i, apic_ids, table_data);
+ if (apic_ids->cpus[i].arch_id > 254) {
+ x2apic_mode = true;
+ }
+ }
+
+ io_apic = acpi_data_push(table_data, sizeof *io_apic);
+ io_apic->type = ACPI_APIC_IO;
+ io_apic->length = sizeof(*io_apic);
+ io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
+ io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
+ io_apic->interrupt = cpu_to_le32(0);
+
+ if (x86ms->apic_xrupt_override) {
+ intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
+ intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
+ intsrcovr->length = sizeof(*intsrcovr);
+ intsrcovr->source = 0;
+ intsrcovr->gsi = cpu_to_le32(2);
+ intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
+ }
+
+ if (has_pci) {
+ for (i = 1; i < 16; i++) {
+#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
+ if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
+ /* No need for a INT source override structure. */
+ continue;
+ }
+ intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
+ intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
+ intsrcovr->length = sizeof(*intsrcovr);
+ intsrcovr->source = i;
+ intsrcovr->gsi = cpu_to_le32(i);
+ intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
+ }
+ }
+
+ if (x2apic_mode) {
+ AcpiMadtLocalX2ApicNmi *local_nmi;
+
+ local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
+ local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
+ local_nmi->length = sizeof(*local_nmi);
+ local_nmi->uid = 0xFFFFFFFF; /* all processors */
+ local_nmi->flags = cpu_to_le16(0);
+ local_nmi->lint = 1; /* ACPI_LINT1 */
+ } else {
+ AcpiMadtLocalNmi *local_nmi;
+
+ local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
+ local_nmi->type = ACPI_APIC_LOCAL_NMI;
+ local_nmi->length = sizeof(*local_nmi);
+ local_nmi->processor_id = 0xff; /* all processors */
+ local_nmi->flags = cpu_to_le16(0);
+ local_nmi->lint = 1; /* ACPI_LINT1 */
+ }
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + madt_start), "APIC",
+ table_data->len - madt_start, 1, NULL, NULL);
+}
+
--- /dev/null
+#ifndef HW_I386_ACPI_COMMON_H
+#define HW_I386_ACPI_COMMON_H
+#include "include/hw/acpi/acpi_dev_interface.h"
+
+#include "include/hw/acpi/bios-linker-loader.h"
+#include "include/hw/i386/x86.h"
+
+/* Default IOAPIC ID */
+#define ACPI_BUILD_IOAPIC_ID 0x0
+
+void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
+ X86MachineState *x86ms, AcpiDeviceIf *adev,
+ bool has_pci);
+
+#endif
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "cpu.h"
#include "hw/pci/pci.h"
* Xen does not allocate the memory continuously, it keeps a
* hole of the size computed above or passed in.
*/
- block_len = (1ULL << 32) + x86ms->above_4g_mem_size;
+ block_len = (4 * GiB) + x86ms->above_4g_mem_size;
}
memory_region_init_ram(&ram_memory, NULL, "xen.ram", block_len,
&error_fatal);
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define TYPE_PUV3_INTC "puv3_intc"
#define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
ret = s->reg_ICPR; /* the same value with ICPR */
break;
default:
- DPRINTF("Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
return ret;
s->reg_ICMR = value;
break;
default:
- DPRINTF("Bad offset 0x%x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
return;
}
puv3_intc_update(s);
#include "hw/isa/apm.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
+#include "trace.h"
-//#define DEBUG
-
-#ifdef DEBUG
-# define APM_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
-#else
-# define APM_DPRINTF(format, ...) do { } while (0)
-#endif
/* fixed I/O location */
#define APM_STS_IOPORT 0xb3
{
APMState *apm = opaque;
addr &= 1;
- APM_DPRINTF("apm_ioport_writeb addr=0x%" HWADDR_PRIx
- " val=0x%02" PRIx64 "\n", addr, val);
+
+ trace_apm_io_write(addr, val);
if (addr == 0) {
apm->apmc = val;
} else {
val = apm->apms;
}
- APM_DPRINTF("apm_ioport_readb addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, val);
+ trace_apm_io_read(addr, val);
+
return val;
}
# pc87312.c
pc87312_io_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
pc87312_io_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
+
+# apm.c
+apm_io_read(uint8_t addr, uint8_t val) "read addr=0x%x val=0x%02x"
+apm_io_write(uint8_t addr, uint8_t val) "write addr=0x%x val=0x%02x"
}
break;
default:
- DPRINTF("Not implemented!\n");
+ qemu_log_mask(LOG_UNIMP, "AUX cmd=%u not implemented\n", cmd);
return AUX_NACK;
}
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define TYPE_PUV3_PM "puv3_pm"
#define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)
ret = 0x7;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
case 0x38:
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
}
int n;
unsigned int smp_cpus = machine->smp.cpus;
+ assert(smp_cpus >= 1 && smp_cpus <= 2);
for (n = 0; n < smp_cpus; n++) {
cpu = OPENRISC_CPU(cpu_create(machine->cpu_type));
if (cpu == NULL) {
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qemu/range.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
memory_region_set_enabled(&f->smram_region, true);
/* smram, as seen by SMM CPUs */
- memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
+ memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB);
memory_region_set_enabled(&f->smram, true);
memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
f->ram_memory, 0xa0000, 0x20000);
&s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
/* Bus master address space */
- memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
+ memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
&s->pci_memory, 0,
memory_region_size(&s->pci_memory));
memory_region_set_enabled(&mch->open_high_smram, false);
/* smram, as seen by SMM CPUs */
- memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32);
+ memory_region_init(&mch->smram, OBJECT(mch), "smram", 4 * GiB);
memory_region_set_enabled(&mch->smram, true);
memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/irq.h"
pci_map_irq_fn mapfn;
int i;
- memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 1ULL << 32);
- memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 1ULL << 32);
+ memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 4 * GiB);
+ memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 4 * GiB);
pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
&s->pci_mem_space, &s->pci_io_space,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
+ .max_access_size = 8,
+ },
+ .impl = {
.max_access_size = 4,
},
};
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
+ .max_access_size = 8,
+ },
+ .impl = {
.max_access_size = 4,
},
};
{
uint32_t val = 0;
+ assert(address + len <= pci_config_size(d));
+
if (pci_is_express_downstream_port(d) &&
ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) {
pcie_sync_bridge_lnk(d);
int i, was_irq_disabled = pci_irq_disabled(d);
uint32_t val = val_in;
+ assert(addr + l <= pci_config_size(d));
+
for (i = 0; i < l; val >>= 8, ++i) {
uint8_t wmask = d->wmask[addr + i];
uint8_t w1cmask = d->w1cmask[addr + i];
info->regions = qmp_query_pci_regions(dev);
info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
+ info->irq_pin = dev->config[PCI_INTERRUPT_PIN];
if (dev->config[PCI_INTERRUPT_PIN] != 0) {
info->has_irq = true;
info->irq = dev->config[PCI_INTERRUPT_LINE];
if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) &&
dc->user_creatable) {
const char *name = object_class_get_name(list->data);
- g_ptr_array_add(pci_nic_models, (gpointer)name);
+ /*
+ * A network device might also be something else than a NIC, see
+ * e.g. the "rocker" device. Thus we have to look for the "netdev"
+ * property, too. Unfortunately, some devices like virtio-net only
+ * create this property during instance_init, so we have to create
+ * a temporary instance here to be able to check it.
+ */
+ Object *obj = object_new_with_class(OBJECT_CLASS(dc));
+ if (object_property_find(obj, "netdev", NULL)) {
+ g_ptr_array_add(pci_nic_models, (gpointer)name);
+ }
+ object_unref(obj);
}
next = list->next;
g_slist_free_1(list);
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "qemu/module.h"
memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
sec_bus->address_space_io = &br->address_space_io;
memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
- UINT32_MAX);
+ 4 * GiB);
br->windows = pci_bridge_region_init(br);
QLIST_INIT(&sec_bus->child);
QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
}
if (res_reserve.mem_non_pref != (uint64_t)-1 &&
- res_reserve.mem_non_pref >= (1ULL << 32)) {
+ res_reserve.mem_non_pref >= 4 * GiB) {
error_setg(errp,
"PCI resource reserve cap: mem-reserve must be less than 4G");
return -EINVAL;
}
if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
- res_reserve.mem_pref_32 >= (1ULL << 32)) {
+ res_reserve.mem_pref_32 >= 4 * GiB) {
error_setg(errp,
"PCI resource reserve cap: pref32-reserve must be less than 4G");
return -EINVAL;
void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
+ PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
+ uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
+ uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP);
+
+ /* Check if hot-plug is disabled on the slot */
+ if (dev->hotplugged && (sltcap & PCI_EXP_SLTCAP_HPC) == 0) {
+ error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'",
+ DEVICE(hotplug_pdev)->id);
+ return;
+ }
+
pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp);
}
{
PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
- uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP);
PCIDevice *pci_dev = PCI_DEVICE(dev);
/* Don't send event when device is enabled during qemu machine creation:
return;
}
- /* Check if hot-plug is disabled on the slot */
- if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) {
- error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'",
- DEVICE(hotplug_pdev)->id);
- return;
- }
-
/* To enable multifunction hot-plug, we just ensure the function
* 0 added last. When function 0 is added, we set the sltsta and
* inform OS via event notification.
#include "qemu/cutils.h"
#include "qemu/module.h"
#include "qemu/bcd.h"
+#include "hw/acpi/aml-build.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qemu/timer.h"
}
}
+static void rtc_build_aml(ISADevice *isadev, Aml *scope)
+{
+ Aml *dev;
+ Aml *crs;
+
+ /*
+ * Reserving 8 io ports here, following what physical hardware
+ * does, even though qemu only responds to the first two ports.
+ */
+ crs = aml_resource_template();
+ aml_append(crs, aml_io(AML_DECODE16, RTC_ISA_BASE, RTC_ISA_BASE,
+ 0x01, 0x08));
+ aml_append(crs, aml_irq_no_flags(RTC_ISA_IRQ));
+
+ dev = aml_device("RTC");
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ aml_append(scope, dev);
+}
+
static void rtc_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
dc->realize = rtc_realizefn;
dc->reset = rtc_resetdev;
dc->vmsd = &vmstate_rtc;
+ isa->build_aml = rtc_build_aml;
device_class_set_props(dc, mc146818rtc_properties);
}
#include "exec/exec-all.h"
#include "qemu/log.h"
#include "chardev/char.h"
-#include <pthread.h>
#include "chardev/char-fe.h"
#include "sysemu/sysemu.h"
#include "qemu/main-loop.h"
#include "hw/irq.h"
#include "hw/ptimer.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
ret = s->reg_OIER;
break;
default:
- DPRINTF("Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
return ret;
s->reg_OIER = value;
break;
default:
- DPRINTF("Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
}
#include "hw/boards.h"
#include "hw/loader.h"
#include "sysemu/qtest.h"
-
-#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "hw/input/i8042.h"
#include "hw/irq.h"
*/
#include "qemu/osdep.h"
+#include "config-devices.h"
#include "exec/memop.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
return 0;
}
-int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp)
-{
- int ret;
-
- ret = vfio_add_nv_gpudirect_cap(vdev, errp);
- if (ret) {
- return ret;
- }
-
- return 0;
-}
-
static void vfio_pci_nvlink2_get_tgt(Object *obj, Visitor *v,
const char *name,
void *opaque, Error **errp)
return ret;
}
+
+/*
+ * The VMD endpoint provides a real PCIe domain to the guest and the guest
+ * kernel performs enumeration of the VMD sub-device domain. Guest transactions
+ * to VMD sub-devices go through MMU translation from guest addresses to
+ * physical addresses. When MMIO goes to an endpoint after being translated to
+ * physical addresses, the bridge rejects the transaction because the window
+ * has been programmed with guest addresses.
+ *
+ * VMD can use the Host Physical Address in order to correctly program the
+ * bridge windows in its PCIe domain. VMD device 28C0 has HPA shadow registers
+ * located at offset 0x2000 in MEMBAR2 (BAR 4). This quirk provides the HPA
+ * shadow registers in a vendor-specific capability register for devices
+ * without native support. The position of 0xE8-0xFF is in the reserved range
+ * of the VMD device capability space following the Power Management
+ * Capability.
+ */
+#define VMD_SHADOW_CAP_VER 1
+#define VMD_SHADOW_CAP_LEN 24
+static int vfio_add_vmd_shadow_cap(VFIOPCIDevice *vdev, Error **errp)
+{
+ uint8_t membar_phys[16];
+ int ret, pos = 0xE8;
+
+ if (!(vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, 0x201D) ||
+ vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, 0x467F) ||
+ vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, 0x4C3D) ||
+ vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, 0x9A0B))) {
+ return 0;
+ }
+
+ ret = pread(vdev->vbasedev.fd, membar_phys, 16,
+ vdev->config_offset + PCI_BASE_ADDRESS_2);
+ if (ret != 16) {
+ error_report("VMD %s cannot read MEMBARs (%d)",
+ vdev->vbasedev.name, ret);
+ return -EFAULT;
+ }
+
+ ret = pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos,
+ VMD_SHADOW_CAP_LEN, errp);
+ if (ret < 0) {
+ error_prepend(errp, "Failed to add VMD MEMBAR Shadow cap: ");
+ return ret;
+ }
+
+ memset(vdev->emulated_config_bits + pos, 0xFF, VMD_SHADOW_CAP_LEN);
+ pos += PCI_CAP_FLAGS;
+ pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_LEN);
+ pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_VER);
+ pci_set_long(vdev->pdev.config + pos, 0x53484457); /* SHDW */
+ memcpy(vdev->pdev.config + pos + 4, membar_phys, 16);
+
+ return 0;
+}
+
+int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp)
+{
+ int ret;
+
+ ret = vfio_add_nv_gpudirect_cap(vdev, errp);
+ if (ret) {
+ return ret;
+ }
+
+ ret = vfio_add_vmd_shadow_cap(vdev, errp);
+ if (ret) {
+ return ret;
+ }
+
+ return 0;
+}
common-obj-$(call land,$(CONFIG_VIRTIO_PMEM),$(CONFIG_VIRTIO_PCI)) += virtio-pmem-pci.o
obj-$(call land,$(CONFIG_VHOST_USER_FS),$(CONFIG_VIRTIO_PCI)) += vhost-user-fs-pci.o
obj-$(CONFIG_VIRTIO_IOMMU) += virtio-iommu.o
-obj-$(CONFIG_VHOST_VSOCK) += vhost-vsock.o
+obj-$(CONFIG_VHOST_VSOCK) += vhost-vsock-common.o vhost-vsock.o
+obj-$(CONFIG_VHOST_USER_VSOCK) += vhost-vsock-common.o vhost-user-vsock.o
ifeq ($(CONFIG_VIRTIO_PCI),y)
obj-$(CONFIG_VHOST_VSOCK) += vhost-vsock-pci.o
+obj-$(CONFIG_VHOST_USER_VSOCK) += vhost-user-vsock-pci.o
obj-$(CONFIG_VHOST_USER_BLK) += vhost-user-blk-pci.o
obj-$(CONFIG_VHOST_USER_INPUT) += vhost-user-input-pci.o
obj-$(CONFIG_VHOST_USER_SCSI) += vhost-user-scsi-pci.o
vhost_region_add_section(const char *name, uint64_t gpa, uint64_t size, uint64_t host) "%s: 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64
vhost_region_add_section_merge(const char *name, uint64_t new_size, uint64_t gpa, uint64_t owr) "%s: size: 0x%"PRIx64 " gpa: 0x%"PRIx64 " owr: 0x%"PRIx64
vhost_region_add_section_aligned(const char *name, uint64_t gpa, uint64_t size, uint64_t host) "%s: 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64
-vhost_section(const char *name, int r) "%s:%d"
+vhost_section(const char *name) "%s"
+vhost_reject_section(const char *name, int d) "%s:%d"
vhost_iotlb_miss(void *dev, int step) "%p step %d"
# vhost-user.c
--- /dev/null
+/*
+ * Vhost-user vsock PCI Bindings
+ *
+ * Copyright 2020 Red Hat, Inc.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version. See the COPYING file in the
+ * top-level directory.
+ */
+
+#include "qemu/osdep.h"
+
+#include "virtio-pci.h"
+#include "hw/qdev-properties.h"
+#include "hw/virtio/vhost-user-vsock.h"
+
+typedef struct VHostUserVSockPCI VHostUserVSockPCI;
+
+/*
+ * vhost-user-vsock-pci: This extends VirtioPCIProxy.
+ */
+#define TYPE_VHOST_USER_VSOCK_PCI "vhost-user-vsock-pci-base"
+#define VHOST_USER_VSOCK_PCI(obj) \
+ OBJECT_CHECK(VHostUserVSockPCI, (obj), TYPE_VHOST_USER_VSOCK_PCI)
+
+struct VHostUserVSockPCI {
+ VirtIOPCIProxy parent_obj;
+ VHostUserVSock vdev;
+};
+
+/* vhost-user-vsock-pci */
+
+static Property vhost_user_vsock_pci_properties[] = {
+ DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void vhost_user_vsock_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
+{
+ VHostUserVSockPCI *dev = VHOST_USER_VSOCK_PCI(vpci_dev);
+ DeviceState *vdev = DEVICE(&dev->vdev);
+
+ qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
+ object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+}
+
+static void vhost_user_vsock_pci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
+ PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
+ k->realize = vhost_user_vsock_pci_realize;
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+ device_class_set_props(dc, vhost_user_vsock_pci_properties);
+ pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
+ pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_VSOCK;
+ pcidev_k->revision = 0x00;
+ pcidev_k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
+}
+
+static void vhost_user_vsock_pci_instance_init(Object *obj)
+{
+ VHostUserVSockPCI *dev = VHOST_USER_VSOCK_PCI(obj);
+
+ virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
+ TYPE_VHOST_USER_VSOCK);
+}
+
+static const VirtioPCIDeviceTypeInfo vhost_user_vsock_pci_info = {
+ .base_name = TYPE_VHOST_USER_VSOCK_PCI,
+ .generic_name = "vhost-user-vsock-pci",
+ .transitional_name = "vhost-user-vsock-pci-transitional",
+ .non_transitional_name = "vhost-user-vsock-pci-non-transitional",
+ .instance_size = sizeof(VHostUserVSockPCI),
+ .instance_init = vhost_user_vsock_pci_instance_init,
+ .class_init = vhost_user_vsock_pci_class_init,
+};
+
+static void virtio_pci_vhost_register(void)
+{
+ virtio_pci_types_register(&vhost_user_vsock_pci_info);
+}
+
+type_init(virtio_pci_vhost_register)
--- /dev/null
+/*
+ * Vhost-user vsock virtio device
+ *
+ * Copyright 2020 Red Hat, Inc.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version. See the COPYING file in the
+ * top-level directory.
+ */
+
+#include "qemu/osdep.h"
+
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "hw/qdev-properties.h"
+#include "hw/virtio/vhost-user-vsock.h"
+
+static const int user_feature_bits[] = {
+ VIRTIO_F_VERSION_1,
+ VIRTIO_RING_F_INDIRECT_DESC,
+ VIRTIO_RING_F_EVENT_IDX,
+ VIRTIO_F_NOTIFY_ON_EMPTY,
+ VHOST_INVALID_FEATURE_BIT
+};
+
+static void vuv_get_config(VirtIODevice *vdev, uint8_t *config)
+{
+ VHostUserVSock *vsock = VHOST_USER_VSOCK(vdev);
+
+ memcpy(config, &vsock->vsockcfg, sizeof(struct virtio_vsock_config));
+}
+
+static int vuv_handle_config_change(struct vhost_dev *dev)
+{
+ VHostUserVSock *vsock = VHOST_USER_VSOCK(dev->vdev);
+ int ret = vhost_dev_get_config(dev, (uint8_t *)&vsock->vsockcfg,
+ sizeof(struct virtio_vsock_config));
+ if (ret < 0) {
+ error_report("get config space failed");
+ return -1;
+ }
+
+ virtio_notify_config(dev->vdev);
+
+ return 0;
+}
+
+const VhostDevConfigOps vsock_ops = {
+ .vhost_dev_config_notifier = vuv_handle_config_change,
+};
+
+static void vuv_set_status(VirtIODevice *vdev, uint8_t status)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+ bool should_start = status & VIRTIO_CONFIG_S_DRIVER_OK;
+
+ if (!vdev->vm_running) {
+ should_start = false;
+ }
+
+ if (vvc->vhost_dev.started == should_start) {
+ return;
+ }
+
+ if (should_start) {
+ int ret = vhost_vsock_common_start(vdev);
+ if (ret < 0) {
+ return;
+ }
+ } else {
+ vhost_vsock_common_stop(vdev);
+ }
+}
+
+static uint64_t vuv_get_features(VirtIODevice *vdev,
+ uint64_t features,
+ Error **errp)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+
+ return vhost_get_features(&vvc->vhost_dev, user_feature_bits, features);
+}
+
+static const VMStateDescription vuv_vmstate = {
+ .name = "vhost-user-vsock",
+ .unmigratable = 1,
+};
+
+static void vuv_device_realize(DeviceState *dev, Error **errp)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(dev);
+ VirtIODevice *vdev = VIRTIO_DEVICE(dev);
+ VHostUserVSock *vsock = VHOST_USER_VSOCK(dev);
+ int ret;
+
+ if (!vsock->conf.chardev.chr) {
+ error_setg(errp, "missing chardev");
+ return;
+ }
+
+ if (!vhost_user_init(&vsock->vhost_user, &vsock->conf.chardev, errp)) {
+ return;
+ }
+
+ vhost_vsock_common_realize(vdev, "vhost-user-vsock");
+
+ vhost_dev_set_config_notifier(&vvc->vhost_dev, &vsock_ops);
+
+ ret = vhost_dev_init(&vvc->vhost_dev, &vsock->vhost_user,
+ VHOST_BACKEND_TYPE_USER, 0);
+ if (ret < 0) {
+ error_setg_errno(errp, -ret, "vhost_dev_init failed");
+ goto err_virtio;
+ }
+
+ ret = vhost_dev_get_config(&vvc->vhost_dev, (uint8_t *)&vsock->vsockcfg,
+ sizeof(struct virtio_vsock_config));
+ if (ret < 0) {
+ error_setg_errno(errp, -ret, "get config space failed");
+ goto err_vhost_dev;
+ }
+
+ return;
+
+err_vhost_dev:
+ vhost_dev_cleanup(&vvc->vhost_dev);
+err_virtio:
+ vhost_vsock_common_unrealize(vdev);
+ vhost_user_cleanup(&vsock->vhost_user);
+ return;
+}
+
+static void vuv_device_unrealize(DeviceState *dev)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(dev);
+ VirtIODevice *vdev = VIRTIO_DEVICE(dev);
+ VHostUserVSock *vsock = VHOST_USER_VSOCK(dev);
+
+ /* This will stop vhost backend if appropriate. */
+ vuv_set_status(vdev, 0);
+
+ vhost_dev_cleanup(&vvc->vhost_dev);
+
+ vhost_vsock_common_unrealize(vdev);
+
+ vhost_user_cleanup(&vsock->vhost_user);
+
+}
+
+static Property vuv_properties[] = {
+ DEFINE_PROP_CHR("chardev", VHostUserVSock, conf.chardev),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void vuv_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
+
+ device_class_set_props(dc, vuv_properties);
+ dc->vmsd = &vuv_vmstate;
+ vdc->realize = vuv_device_realize;
+ vdc->unrealize = vuv_device_unrealize;
+ vdc->get_features = vuv_get_features;
+ vdc->get_config = vuv_get_config;
+ vdc->set_status = vuv_set_status;
+}
+
+static const TypeInfo vuv_info = {
+ .name = TYPE_VHOST_USER_VSOCK,
+ .parent = TYPE_VHOST_VSOCK_COMMON,
+ .instance_size = sizeof(VHostUserVSock),
+ .class_init = vuv_class_init,
+};
+
+static void vuv_register_types(void)
+{
+ type_register_static(&vuv_info);
+}
+
+type_init(vuv_register_types)
#include <linux/userfaultfd.h>
#endif
-#define VHOST_MEMORY_MAX_NREGIONS 8
+#define VHOST_MEMORY_BASELINE_NREGIONS 8
#define VHOST_USER_F_PROTOCOL_FEATURES 30
#define VHOST_USER_SLAVE_MAX_FDS 8
+/*
+ * Set maximum number of RAM slots supported to
+ * the maximum number supported by the target
+ * hardware plaform.
+ */
+#if defined(TARGET_X86) || defined(TARGET_X86_64) || \
+ defined(TARGET_ARM) || defined(TARGET_ARM_64)
+#include "hw/acpi/acpi.h"
+#define VHOST_USER_MAX_RAM_SLOTS ACPI_MAX_RAM_SLOTS
+
+#elif defined(TARGET_PPC) || defined(TARGET_PPC_64)
+#include "hw/ppc/spapr.h"
+#define VHOST_USER_MAX_RAM_SLOTS SPAPR_MAX_RAM_SLOTS
+
+#else
+#define VHOST_USER_MAX_RAM_SLOTS 512
+#endif
+
/*
* Maximum size of virtio device config space
*/
VHOST_USER_PROTOCOL_F_HOST_NOTIFIER = 11,
VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD = 12,
VHOST_USER_PROTOCOL_F_RESET_DEVICE = 13,
+ /* Feature 14 reserved for VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS. */
+ VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS = 15,
VHOST_USER_PROTOCOL_F_MAX
};
VHOST_USER_SET_INFLIGHT_FD = 32,
VHOST_USER_GPU_SET_SOCKET = 33,
VHOST_USER_RESET_DEVICE = 34,
+ /* Message number 35 reserved for VHOST_USER_VRING_KICK. */
+ VHOST_USER_GET_MAX_MEM_SLOTS = 36,
+ VHOST_USER_ADD_MEM_REG = 37,
+ VHOST_USER_REM_MEM_REG = 38,
VHOST_USER_MAX
} VhostUserRequest;
typedef struct VhostUserMemory {
uint32_t nregions;
uint32_t padding;
- VhostUserMemoryRegion regions[VHOST_MEMORY_MAX_NREGIONS];
+ VhostUserMemoryRegion regions[VHOST_MEMORY_BASELINE_NREGIONS];
} VhostUserMemory;
+typedef struct VhostUserMemRegMsg {
+ uint32_t padding;
+ VhostUserMemoryRegion region;
+} VhostUserMemRegMsg;
+
typedef struct VhostUserLog {
uint64_t mmap_size;
uint64_t mmap_offset;
struct vhost_vring_state state;
struct vhost_vring_addr addr;
VhostUserMemory memory;
+ VhostUserMemRegMsg mem_reg;
VhostUserLog log;
struct vhost_iotlb_msg iotlb;
VhostUserConfig config;
int slave_fd;
NotifierWithReturn postcopy_notifier;
struct PostCopyFD postcopy_fd;
- uint64_t postcopy_client_bases[VHOST_MEMORY_MAX_NREGIONS];
+ uint64_t postcopy_client_bases[VHOST_USER_MAX_RAM_SLOTS];
/* Length of the region_rb and region_rb_offset arrays */
size_t region_rb_len;
/* RAMBlock associated with a given region */
/* True once we've entered postcopy_listen */
bool postcopy_listen;
+
+ /* Our current regions */
+ int num_shadow_regions;
+ struct vhost_memory_region shadow_regions[VHOST_USER_MAX_RAM_SLOTS];
+};
+
+struct scrub_regions {
+ struct vhost_memory_region *region;
+ int reg_idx;
+ int fd_idx;
};
static bool ioeventfd_enabled(void)
static int vhost_user_set_log_base(struct vhost_dev *dev, uint64_t base,
struct vhost_log *log)
{
- int fds[VHOST_MEMORY_MAX_NREGIONS];
+ int fds[VHOST_USER_MAX_RAM_SLOTS];
size_t fd_num = 0;
bool shmfd = virtio_has_feature(dev->protocol_features,
VHOST_USER_PROTOCOL_F_LOG_SHMFD);
return 0;
}
+static MemoryRegion *vhost_user_get_mr_data(uint64_t addr, ram_addr_t *offset,
+ int *fd)
+{
+ MemoryRegion *mr;
+
+ assert((uintptr_t)addr == addr);
+ mr = memory_region_from_host((void *)(uintptr_t)addr, offset);
+ *fd = memory_region_get_fd(mr);
+
+ return mr;
+}
+
+static void vhost_user_fill_msg_region(VhostUserMemoryRegion *dst,
+ struct vhost_memory_region *src)
+{
+ assert(src != NULL && dst != NULL);
+ dst->userspace_addr = src->userspace_addr;
+ dst->memory_size = src->memory_size;
+ dst->guest_phys_addr = src->guest_phys_addr;
+}
+
static int vhost_user_fill_set_mem_table_msg(struct vhost_user *u,
struct vhost_dev *dev,
VhostUserMsg *msg,
ram_addr_t offset;
MemoryRegion *mr;
struct vhost_memory_region *reg;
+ VhostUserMemoryRegion region_buffer;
msg->hdr.request = VHOST_USER_SET_MEM_TABLE;
for (i = 0; i < dev->mem->nregions; ++i) {
reg = dev->mem->regions + i;
- assert((uintptr_t)reg->userspace_addr == reg->userspace_addr);
- mr = memory_region_from_host((void *)(uintptr_t)reg->userspace_addr,
- &offset);
- fd = memory_region_get_fd(mr);
+ mr = vhost_user_get_mr_data(reg->userspace_addr, &offset, &fd);
if (fd > 0) {
if (track_ramblocks) {
- assert(*fd_num < VHOST_MEMORY_MAX_NREGIONS);
+ assert(*fd_num < VHOST_MEMORY_BASELINE_NREGIONS);
trace_vhost_user_set_mem_table_withfd(*fd_num, mr->name,
reg->memory_size,
reg->guest_phys_addr,
offset);
u->region_rb_offset[i] = offset;
u->region_rb[i] = mr->ram_block;
- } else if (*fd_num == VHOST_MEMORY_MAX_NREGIONS) {
+ } else if (*fd_num == VHOST_MEMORY_BASELINE_NREGIONS) {
error_report("Failed preparing vhost-user memory table msg");
return -1;
}
- msg->payload.memory.regions[*fd_num].userspace_addr =
- reg->userspace_addr;
- msg->payload.memory.regions[*fd_num].memory_size =
- reg->memory_size;
- msg->payload.memory.regions[*fd_num].guest_phys_addr =
- reg->guest_phys_addr;
+ vhost_user_fill_msg_region(®ion_buffer, reg);
+ msg->payload.memory.regions[*fd_num] = region_buffer;
msg->payload.memory.regions[*fd_num].mmap_offset = offset;
fds[(*fd_num)++] = fd;
} else if (track_ramblocks) {
return 1;
}
+static inline bool reg_equal(struct vhost_memory_region *shadow_reg,
+ struct vhost_memory_region *vdev_reg)
+{
+ return shadow_reg->guest_phys_addr == vdev_reg->guest_phys_addr &&
+ shadow_reg->userspace_addr == vdev_reg->userspace_addr &&
+ shadow_reg->memory_size == vdev_reg->memory_size;
+}
+
+static void scrub_shadow_regions(struct vhost_dev *dev,
+ struct scrub_regions *add_reg,
+ int *nr_add_reg,
+ struct scrub_regions *rem_reg,
+ int *nr_rem_reg, uint64_t *shadow_pcb,
+ bool track_ramblocks)
+{
+ struct vhost_user *u = dev->opaque;
+ bool found[VHOST_USER_MAX_RAM_SLOTS] = {};
+ struct vhost_memory_region *reg, *shadow_reg;
+ int i, j, fd, add_idx = 0, rm_idx = 0, fd_num = 0;
+ ram_addr_t offset;
+ MemoryRegion *mr;
+ bool matching;
+
+ /*
+ * Find memory regions present in our shadow state which are not in
+ * the device's current memory state.
+ *
+ * Mark regions in both the shadow and device state as "found".
+ */
+ for (i = 0; i < u->num_shadow_regions; i++) {
+ shadow_reg = &u->shadow_regions[i];
+ matching = false;
+
+ for (j = 0; j < dev->mem->nregions; j++) {
+ reg = &dev->mem->regions[j];
+
+ mr = vhost_user_get_mr_data(reg->userspace_addr, &offset, &fd);
+
+ if (reg_equal(shadow_reg, reg)) {
+ matching = true;
+ found[j] = true;
+ if (track_ramblocks) {
+ /*
+ * Reset postcopy client bases, region_rb, and
+ * region_rb_offset in case regions are removed.
+ */
+ if (fd > 0) {
+ u->region_rb_offset[j] = offset;
+ u->region_rb[j] = mr->ram_block;
+ shadow_pcb[j] = u->postcopy_client_bases[i];
+ } else {
+ u->region_rb_offset[j] = 0;
+ u->region_rb[j] = NULL;
+ }
+ }
+ break;
+ }
+ }
+
+ /*
+ * If the region was not found in the current device memory state
+ * create an entry for it in the removed list.
+ */
+ if (!matching) {
+ rem_reg[rm_idx].region = shadow_reg;
+ rem_reg[rm_idx++].reg_idx = i;
+ }
+ }
+
+ /*
+ * For regions not marked "found", create entries in the added list.
+ *
+ * Note their indexes in the device memory state and the indexes of their
+ * file descriptors.
+ */
+ for (i = 0; i < dev->mem->nregions; i++) {
+ reg = &dev->mem->regions[i];
+ mr = vhost_user_get_mr_data(reg->userspace_addr, &offset, &fd);
+ if (fd > 0) {
+ ++fd_num;
+ }
+
+ /*
+ * If the region was in both the shadow and device state we don't
+ * need to send a VHOST_USER_ADD_MEM_REG message for it.
+ */
+ if (found[i]) {
+ continue;
+ }
+
+ add_reg[add_idx].region = reg;
+ add_reg[add_idx].reg_idx = i;
+ add_reg[add_idx++].fd_idx = fd_num;
+ }
+ *nr_rem_reg = rm_idx;
+ *nr_add_reg = add_idx;
+
+ return;
+}
+
+static int send_remove_regions(struct vhost_dev *dev,
+ struct scrub_regions *remove_reg,
+ int nr_rem_reg, VhostUserMsg *msg,
+ bool reply_supported)
+{
+ struct vhost_user *u = dev->opaque;
+ struct vhost_memory_region *shadow_reg;
+ int i, fd, shadow_reg_idx, ret;
+ ram_addr_t offset;
+ VhostUserMemoryRegion region_buffer;
+
+ /*
+ * The regions in remove_reg appear in the same order they do in the
+ * shadow table. Therefore we can minimize memory copies by iterating
+ * through remove_reg backwards.
+ */
+ for (i = nr_rem_reg - 1; i >= 0; i--) {
+ shadow_reg = remove_reg[i].region;
+ shadow_reg_idx = remove_reg[i].reg_idx;
+
+ vhost_user_get_mr_data(shadow_reg->userspace_addr, &offset, &fd);
+
+ if (fd > 0) {
+ msg->hdr.request = VHOST_USER_REM_MEM_REG;
+ vhost_user_fill_msg_region(®ion_buffer, shadow_reg);
+ msg->payload.mem_reg.region = region_buffer;
+
+ if (vhost_user_write(dev, msg, &fd, 1) < 0) {
+ return -1;
+ }
+
+ if (reply_supported) {
+ ret = process_message_reply(dev, msg);
+ if (ret) {
+ return ret;
+ }
+ }
+ }
+
+ /*
+ * At this point we know the backend has unmapped the region. It is now
+ * safe to remove it from the shadow table.
+ */
+ memmove(&u->shadow_regions[shadow_reg_idx],
+ &u->shadow_regions[shadow_reg_idx + 1],
+ sizeof(struct vhost_memory_region) *
+ (u->num_shadow_regions - shadow_reg_idx));
+ u->num_shadow_regions--;
+ }
+
+ return 0;
+}
+
+static int send_add_regions(struct vhost_dev *dev,
+ struct scrub_regions *add_reg, int nr_add_reg,
+ VhostUserMsg *msg, uint64_t *shadow_pcb,
+ bool reply_supported, bool track_ramblocks)
+{
+ struct vhost_user *u = dev->opaque;
+ int i, fd, ret, reg_idx, reg_fd_idx;
+ struct vhost_memory_region *reg;
+ MemoryRegion *mr;
+ ram_addr_t offset;
+ VhostUserMsg msg_reply;
+ VhostUserMemoryRegion region_buffer;
+
+ for (i = 0; i < nr_add_reg; i++) {
+ reg = add_reg[i].region;
+ reg_idx = add_reg[i].reg_idx;
+ reg_fd_idx = add_reg[i].fd_idx;
+
+ mr = vhost_user_get_mr_data(reg->userspace_addr, &offset, &fd);
+
+ if (fd > 0) {
+ if (track_ramblocks) {
+ trace_vhost_user_set_mem_table_withfd(reg_fd_idx, mr->name,
+ reg->memory_size,
+ reg->guest_phys_addr,
+ reg->userspace_addr,
+ offset);
+ u->region_rb_offset[reg_idx] = offset;
+ u->region_rb[reg_idx] = mr->ram_block;
+ }
+ msg->hdr.request = VHOST_USER_ADD_MEM_REG;
+ vhost_user_fill_msg_region(®ion_buffer, reg);
+ msg->payload.mem_reg.region = region_buffer;
+ msg->payload.mem_reg.region.mmap_offset = offset;
+
+ if (vhost_user_write(dev, msg, &fd, 1) < 0) {
+ return -1;
+ }
+
+ if (track_ramblocks) {
+ uint64_t reply_gpa;
+
+ if (vhost_user_read(dev, &msg_reply) < 0) {
+ return -1;
+ }
+
+ reply_gpa = msg_reply.payload.mem_reg.region.guest_phys_addr;
+
+ if (msg_reply.hdr.request != VHOST_USER_ADD_MEM_REG) {
+ error_report("%s: Received unexpected msg type."
+ "Expected %d received %d", __func__,
+ VHOST_USER_ADD_MEM_REG,
+ msg_reply.hdr.request);
+ return -1;
+ }
+
+ /*
+ * We're using the same structure, just reusing one of the
+ * fields, so it should be the same size.
+ */
+ if (msg_reply.hdr.size != msg->hdr.size) {
+ error_report("%s: Unexpected size for postcopy reply "
+ "%d vs %d", __func__, msg_reply.hdr.size,
+ msg->hdr.size);
+ return -1;
+ }
+
+ /* Get the postcopy client base from the backend's reply. */
+ if (reply_gpa == dev->mem->regions[reg_idx].guest_phys_addr) {
+ shadow_pcb[reg_idx] =
+ msg_reply.payload.mem_reg.region.userspace_addr;
+ trace_vhost_user_set_mem_table_postcopy(
+ msg_reply.payload.mem_reg.region.userspace_addr,
+ msg->payload.mem_reg.region.userspace_addr,
+ reg_fd_idx, reg_idx);
+ } else {
+ error_report("%s: invalid postcopy reply for region. "
+ "Got guest physical address %" PRIX64 ", expected "
+ "%" PRIX64, __func__, reply_gpa,
+ dev->mem->regions[reg_idx].guest_phys_addr);
+ return -1;
+ }
+ } else if (reply_supported) {
+ ret = process_message_reply(dev, msg);
+ if (ret) {
+ return ret;
+ }
+ }
+ } else if (track_ramblocks) {
+ u->region_rb_offset[reg_idx] = 0;
+ u->region_rb[reg_idx] = NULL;
+ }
+
+ /*
+ * At this point, we know the backend has mapped in the new
+ * region, if the region has a valid file descriptor.
+ *
+ * The region should now be added to the shadow table.
+ */
+ u->shadow_regions[u->num_shadow_regions].guest_phys_addr =
+ reg->guest_phys_addr;
+ u->shadow_regions[u->num_shadow_regions].userspace_addr =
+ reg->userspace_addr;
+ u->shadow_regions[u->num_shadow_regions].memory_size =
+ reg->memory_size;
+ u->num_shadow_regions++;
+ }
+
+ return 0;
+}
+
+static int vhost_user_add_remove_regions(struct vhost_dev *dev,
+ VhostUserMsg *msg,
+ bool reply_supported,
+ bool track_ramblocks)
+{
+ struct vhost_user *u = dev->opaque;
+ struct scrub_regions add_reg[VHOST_USER_MAX_RAM_SLOTS];
+ struct scrub_regions rem_reg[VHOST_USER_MAX_RAM_SLOTS];
+ uint64_t shadow_pcb[VHOST_USER_MAX_RAM_SLOTS] = {};
+ int nr_add_reg, nr_rem_reg;
+
+ msg->hdr.size = sizeof(msg->payload.mem_reg.padding) +
+ sizeof(VhostUserMemoryRegion);
+
+ /* Find the regions which need to be removed or added. */
+ scrub_shadow_regions(dev, add_reg, &nr_add_reg, rem_reg, &nr_rem_reg,
+ shadow_pcb, track_ramblocks);
+
+ if (nr_rem_reg && send_remove_regions(dev, rem_reg, nr_rem_reg, msg,
+ reply_supported) < 0)
+ {
+ goto err;
+ }
+
+ if (nr_add_reg && send_add_regions(dev, add_reg, nr_add_reg, msg,
+ shadow_pcb, reply_supported, track_ramblocks) < 0)
+ {
+ goto err;
+ }
+
+ if (track_ramblocks) {
+ memcpy(u->postcopy_client_bases, shadow_pcb,
+ sizeof(uint64_t) * VHOST_USER_MAX_RAM_SLOTS);
+ /*
+ * Now we've registered this with the postcopy code, we ack to the
+ * client, because now we're in the position to be able to deal with
+ * any faults it generates.
+ */
+ /* TODO: Use this for failure cases as well with a bad value. */
+ msg->hdr.size = sizeof(msg->payload.u64);
+ msg->payload.u64 = 0; /* OK */
+
+ if (vhost_user_write(dev, msg, NULL, 0) < 0) {
+ return -1;
+ }
+ }
+
+ return 0;
+
+err:
+ if (track_ramblocks) {
+ memcpy(u->postcopy_client_bases, shadow_pcb,
+ sizeof(uint64_t) * VHOST_USER_MAX_RAM_SLOTS);
+ }
+
+ return -1;
+}
+
static int vhost_user_set_mem_table_postcopy(struct vhost_dev *dev,
- struct vhost_memory *mem)
+ struct vhost_memory *mem,
+ bool reply_supported,
+ bool config_mem_slots)
{
struct vhost_user *u = dev->opaque;
- int fds[VHOST_MEMORY_MAX_NREGIONS];
+ int fds[VHOST_MEMORY_BASELINE_NREGIONS];
size_t fd_num = 0;
VhostUserMsg msg_reply;
int region_i, msg_i;
u->region_rb_len = dev->mem->nregions;
}
- if (vhost_user_fill_set_mem_table_msg(u, dev, &msg, fds, &fd_num,
+ if (config_mem_slots) {
+ if (vhost_user_add_remove_regions(dev, &msg, reply_supported,
true) < 0) {
- return -1;
- }
+ return -1;
+ }
+ } else {
+ if (vhost_user_fill_set_mem_table_msg(u, dev, &msg, fds, &fd_num,
+ true) < 0) {
+ return -1;
+ }
- if (vhost_user_write(dev, &msg, fds, fd_num) < 0) {
- return -1;
- }
+ if (vhost_user_write(dev, &msg, fds, fd_num) < 0) {
+ return -1;
+ }
- if (vhost_user_read(dev, &msg_reply) < 0) {
- return -1;
- }
+ if (vhost_user_read(dev, &msg_reply) < 0) {
+ return -1;
+ }
- if (msg_reply.hdr.request != VHOST_USER_SET_MEM_TABLE) {
- error_report("%s: Received unexpected msg type."
- "Expected %d received %d", __func__,
- VHOST_USER_SET_MEM_TABLE, msg_reply.hdr.request);
- return -1;
- }
- /* We're using the same structure, just reusing one of the
- * fields, so it should be the same size.
- */
- if (msg_reply.hdr.size != msg.hdr.size) {
- error_report("%s: Unexpected size for postcopy reply "
- "%d vs %d", __func__, msg_reply.hdr.size, msg.hdr.size);
- return -1;
- }
-
- memset(u->postcopy_client_bases, 0,
- sizeof(uint64_t) * VHOST_MEMORY_MAX_NREGIONS);
-
- /* They're in the same order as the regions that were sent
- * but some of the regions were skipped (above) if they
- * didn't have fd's
- */
- for (msg_i = 0, region_i = 0;
- region_i < dev->mem->nregions;
- region_i++) {
- if (msg_i < fd_num &&
- msg_reply.payload.memory.regions[msg_i].guest_phys_addr ==
- dev->mem->regions[region_i].guest_phys_addr) {
- u->postcopy_client_bases[region_i] =
- msg_reply.payload.memory.regions[msg_i].userspace_addr;
- trace_vhost_user_set_mem_table_postcopy(
- msg_reply.payload.memory.regions[msg_i].userspace_addr,
- msg.payload.memory.regions[msg_i].userspace_addr,
- msg_i, region_i);
- msg_i++;
+ if (msg_reply.hdr.request != VHOST_USER_SET_MEM_TABLE) {
+ error_report("%s: Received unexpected msg type."
+ "Expected %d received %d", __func__,
+ VHOST_USER_SET_MEM_TABLE, msg_reply.hdr.request);
+ return -1;
+ }
+
+ /*
+ * We're using the same structure, just reusing one of the
+ * fields, so it should be the same size.
+ */
+ if (msg_reply.hdr.size != msg.hdr.size) {
+ error_report("%s: Unexpected size for postcopy reply "
+ "%d vs %d", __func__, msg_reply.hdr.size,
+ msg.hdr.size);
+ return -1;
+ }
+
+ memset(u->postcopy_client_bases, 0,
+ sizeof(uint64_t) * VHOST_USER_MAX_RAM_SLOTS);
+
+ /*
+ * They're in the same order as the regions that were sent
+ * but some of the regions were skipped (above) if they
+ * didn't have fd's
+ */
+ for (msg_i = 0, region_i = 0;
+ region_i < dev->mem->nregions;
+ region_i++) {
+ if (msg_i < fd_num &&
+ msg_reply.payload.memory.regions[msg_i].guest_phys_addr ==
+ dev->mem->regions[region_i].guest_phys_addr) {
+ u->postcopy_client_bases[region_i] =
+ msg_reply.payload.memory.regions[msg_i].userspace_addr;
+ trace_vhost_user_set_mem_table_postcopy(
+ msg_reply.payload.memory.regions[msg_i].userspace_addr,
+ msg.payload.memory.regions[msg_i].userspace_addr,
+ msg_i, region_i);
+ msg_i++;
+ }
+ }
+ if (msg_i != fd_num) {
+ error_report("%s: postcopy reply not fully consumed "
+ "%d vs %zd",
+ __func__, msg_i, fd_num);
+ return -1;
+ }
+
+ /*
+ * Now we've registered this with the postcopy code, we ack to the
+ * client, because now we're in the position to be able to deal
+ * with any faults it generates.
+ */
+ /* TODO: Use this for failure cases as well with a bad value. */
+ msg.hdr.size = sizeof(msg.payload.u64);
+ msg.payload.u64 = 0; /* OK */
+ if (vhost_user_write(dev, &msg, NULL, 0) < 0) {
+ return -1;
}
- }
- if (msg_i != fd_num) {
- error_report("%s: postcopy reply not fully consumed "
- "%d vs %zd",
- __func__, msg_i, fd_num);
- return -1;
- }
- /* Now we've registered this with the postcopy code, we ack to the client,
- * because now we're in the position to be able to deal with any faults
- * it generates.
- */
- /* TODO: Use this for failure cases as well with a bad value */
- msg.hdr.size = sizeof(msg.payload.u64);
- msg.payload.u64 = 0; /* OK */
- if (vhost_user_write(dev, &msg, NULL, 0) < 0) {
- return -1;
}
return 0;
struct vhost_memory *mem)
{
struct vhost_user *u = dev->opaque;
- int fds[VHOST_MEMORY_MAX_NREGIONS];
+ int fds[VHOST_MEMORY_BASELINE_NREGIONS];
size_t fd_num = 0;
bool do_postcopy = u->postcopy_listen && u->postcopy_fd.handler;
bool reply_supported = virtio_has_feature(dev->protocol_features,
VHOST_USER_PROTOCOL_F_REPLY_ACK);
+ bool config_mem_slots =
+ virtio_has_feature(dev->protocol_features,
+ VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS);
if (do_postcopy) {
- /* Postcopy has enough differences that it's best done in it's own
+ /*
+ * Postcopy has enough differences that it's best done in it's own
* version
*/
- return vhost_user_set_mem_table_postcopy(dev, mem);
+ return vhost_user_set_mem_table_postcopy(dev, mem, reply_supported,
+ config_mem_slots);
}
VhostUserMsg msg = {
msg.hdr.flags |= VHOST_USER_NEED_REPLY_MASK;
}
- if (vhost_user_fill_set_mem_table_msg(u, dev, &msg, fds, &fd_num,
+ if (config_mem_slots) {
+ if (vhost_user_add_remove_regions(dev, &msg, reply_supported,
false) < 0) {
- return -1;
- }
-
- if (vhost_user_write(dev, &msg, fds, fd_num) < 0) {
- return -1;
- }
+ return -1;
+ }
+ } else {
+ if (vhost_user_fill_set_mem_table_msg(u, dev, &msg, fds, &fd_num,
+ false) < 0) {
+ return -1;
+ }
+ if (vhost_user_write(dev, &msg, fds, fd_num) < 0) {
+ return -1;
+ }
- if (reply_supported) {
- return process_message_reply(dev, &msg);
+ if (reply_supported) {
+ return process_message_reply(dev, &msg);
+ }
}
return 0;
VhostUserRequest request,
struct vhost_vring_file *file)
{
- int fds[VHOST_MEMORY_MAX_NREGIONS];
+ int fds[VHOST_USER_MAX_RAM_SLOTS];
size_t fd_num = 0;
VhostUserMsg msg = {
.hdr.request = request,
return 0;
}
+static int vhost_user_get_max_memslots(struct vhost_dev *dev,
+ uint64_t *max_memslots)
+{
+ uint64_t backend_max_memslots;
+ int err;
+
+ err = vhost_user_get_u64(dev, VHOST_USER_GET_MAX_MEM_SLOTS,
+ &backend_max_memslots);
+ if (err < 0) {
+ return err;
+ }
+
+ *max_memslots = backend_max_memslots;
+
+ return 0;
+}
+
static int vhost_user_reset_device(struct vhost_dev *dev)
{
VhostUserMsg msg = {
static int vhost_user_backend_init(struct vhost_dev *dev, void *opaque)
{
- uint64_t features, protocol_features;
+ uint64_t features, protocol_features, ram_slots;
struct vhost_user *u;
int err;
"slave-req protocol features.");
return -1;
}
+
+ /* get max memory regions if backend supports configurable RAM slots */
+ if (!virtio_has_feature(dev->protocol_features,
+ VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS)) {
+ u->user->memory_slots = VHOST_MEMORY_BASELINE_NREGIONS;
+ } else {
+ err = vhost_user_get_max_memslots(dev, &ram_slots);
+ if (err < 0) {
+ return err;
+ }
+
+ if (ram_slots < u->user->memory_slots) {
+ error_report("The backend specified a max ram slots limit "
+ "of %" PRIu64", when the prior validated limit was %d. "
+ "This limit should never decrease.", ram_slots,
+ u->user->memory_slots);
+ return -1;
+ }
+
+ u->user->memory_slots = MIN(ram_slots, VHOST_USER_MAX_RAM_SLOTS);
+ }
}
if (dev->migration_blocker == NULL &&
static int vhost_user_memslots_limit(struct vhost_dev *dev)
{
- return VHOST_MEMORY_MAX_NREGIONS;
+ struct vhost_user *u = dev->opaque;
+
+ return u->user->memory_slots;
}
static bool vhost_user_requires_shm_log(struct vhost_dev *dev)
{
ram_addr_t offset;
int mfd, rfd;
- MemoryRegion *mr;
-
- mr = memory_region_from_host((void *)(uintptr_t)start1, &offset);
- mfd = memory_region_get_fd(mr);
- mr = memory_region_from_host((void *)(uintptr_t)start2, &offset);
- rfd = memory_region_get_fd(mr);
+ (void)vhost_user_get_mr_data(start1, &offset, &mfd);
+ (void)vhost_user_get_mr_data(start2, &offset, &rfd);
return mfd == rfd;
}
return false;
}
user->chr = chr;
+ user->memory_slots = 0;
return true;
}
--- /dev/null
+/*
+ * Parent class for vhost-vsock devices
+ *
+ * Copyright 2015-2020 Red Hat, Inc.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version. See the COPYING file in the
+ * top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "standard-headers/linux/virtio_vsock.h"
+#include "qapi/error.h"
+#include "hw/virtio/virtio-access.h"
+#include "qemu/error-report.h"
+#include "hw/qdev-properties.h"
+#include "hw/virtio/vhost-vsock.h"
+#include "qemu/iov.h"
+#include "monitor/monitor.h"
+
+int vhost_vsock_common_start(VirtIODevice *vdev)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+ BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
+ VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus);
+ int ret;
+ int i;
+
+ if (!k->set_guest_notifiers) {
+ error_report("binding does not support guest notifiers");
+ return -ENOSYS;
+ }
+
+ ret = vhost_dev_enable_notifiers(&vvc->vhost_dev, vdev);
+ if (ret < 0) {
+ error_report("Error enabling host notifiers: %d", -ret);
+ return ret;
+ }
+
+ ret = k->set_guest_notifiers(qbus->parent, vvc->vhost_dev.nvqs, true);
+ if (ret < 0) {
+ error_report("Error binding guest notifier: %d", -ret);
+ goto err_host_notifiers;
+ }
+
+ vvc->vhost_dev.acked_features = vdev->guest_features;
+ ret = vhost_dev_start(&vvc->vhost_dev, vdev);
+ if (ret < 0) {
+ error_report("Error starting vhost: %d", -ret);
+ goto err_guest_notifiers;
+ }
+
+ /*
+ * guest_notifier_mask/pending not used yet, so just unmask
+ * everything here. virtio-pci will do the right thing by
+ * enabling/disabling irqfd.
+ */
+ for (i = 0; i < vvc->vhost_dev.nvqs; i++) {
+ vhost_virtqueue_mask(&vvc->vhost_dev, vdev, i, false);
+ }
+
+ return 0;
+
+err_guest_notifiers:
+ k->set_guest_notifiers(qbus->parent, vvc->vhost_dev.nvqs, false);
+err_host_notifiers:
+ vhost_dev_disable_notifiers(&vvc->vhost_dev, vdev);
+ return ret;
+}
+
+void vhost_vsock_common_stop(VirtIODevice *vdev)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+ BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
+ VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus);
+ int ret;
+
+ if (!k->set_guest_notifiers) {
+ return;
+ }
+
+ vhost_dev_stop(&vvc->vhost_dev, vdev);
+
+ ret = k->set_guest_notifiers(qbus->parent, vvc->vhost_dev.nvqs, false);
+ if (ret < 0) {
+ error_report("vhost guest notifier cleanup failed: %d", ret);
+ return;
+ }
+
+ vhost_dev_disable_notifiers(&vvc->vhost_dev, vdev);
+}
+
+
+static void vhost_vsock_common_handle_output(VirtIODevice *vdev, VirtQueue *vq)
+{
+ /* Do nothing */
+}
+
+static void vhost_vsock_common_guest_notifier_mask(VirtIODevice *vdev, int idx,
+ bool mask)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+
+ vhost_virtqueue_mask(&vvc->vhost_dev, vdev, idx, mask);
+}
+
+static bool vhost_vsock_common_guest_notifier_pending(VirtIODevice *vdev,
+ int idx)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+
+ return vhost_virtqueue_pending(&vvc->vhost_dev, idx);
+}
+
+static void vhost_vsock_common_send_transport_reset(VHostVSockCommon *vvc)
+{
+ VirtQueueElement *elem;
+ VirtQueue *vq = vvc->event_vq;
+ struct virtio_vsock_event event = {
+ .id = cpu_to_le32(VIRTIO_VSOCK_EVENT_TRANSPORT_RESET),
+ };
+
+ elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
+ if (!elem) {
+ error_report("vhost-vsock missed transport reset event");
+ return;
+ }
+
+ if (elem->out_num) {
+ error_report("invalid vhost-vsock event virtqueue element with "
+ "out buffers");
+ goto out;
+ }
+
+ if (iov_from_buf(elem->in_sg, elem->in_num, 0,
+ &event, sizeof(event)) != sizeof(event)) {
+ error_report("vhost-vsock event virtqueue element is too short");
+ goto out;
+ }
+
+ virtqueue_push(vq, elem, sizeof(event));
+ virtio_notify(VIRTIO_DEVICE(vvc), vq);
+
+out:
+ g_free(elem);
+}
+
+static void vhost_vsock_common_post_load_timer_cleanup(VHostVSockCommon *vvc)
+{
+ if (!vvc->post_load_timer) {
+ return;
+ }
+
+ timer_del(vvc->post_load_timer);
+ timer_free(vvc->post_load_timer);
+ vvc->post_load_timer = NULL;
+}
+
+static void vhost_vsock_common_post_load_timer_cb(void *opaque)
+{
+ VHostVSockCommon *vvc = opaque;
+
+ vhost_vsock_common_post_load_timer_cleanup(vvc);
+ vhost_vsock_common_send_transport_reset(vvc);
+}
+
+int vhost_vsock_common_pre_save(void *opaque)
+{
+ VHostVSockCommon *vvc = opaque;
+
+ /*
+ * At this point, backend must be stopped, otherwise
+ * it might keep writing to memory.
+ */
+ assert(!vvc->vhost_dev.started);
+
+ return 0;
+}
+
+int vhost_vsock_common_post_load(void *opaque, int version_id)
+{
+ VHostVSockCommon *vvc = opaque;
+ VirtIODevice *vdev = VIRTIO_DEVICE(vvc);
+
+ if (virtio_queue_get_addr(vdev, 2)) {
+ /*
+ * Defer transport reset event to a vm clock timer so that virtqueue
+ * changes happen after migration has completed.
+ */
+ assert(!vvc->post_load_timer);
+ vvc->post_load_timer =
+ timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ vhost_vsock_common_post_load_timer_cb,
+ vvc);
+ timer_mod(vvc->post_load_timer, 1);
+ }
+ return 0;
+}
+
+void vhost_vsock_common_realize(VirtIODevice *vdev, const char *name)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+
+ virtio_init(vdev, name, VIRTIO_ID_VSOCK,
+ sizeof(struct virtio_vsock_config));
+
+ /* Receive and transmit queues belong to vhost */
+ vvc->recv_vq = virtio_add_queue(vdev, VHOST_VSOCK_QUEUE_SIZE,
+ vhost_vsock_common_handle_output);
+ vvc->trans_vq = virtio_add_queue(vdev, VHOST_VSOCK_QUEUE_SIZE,
+ vhost_vsock_common_handle_output);
+
+ /* The event queue belongs to QEMU */
+ vvc->event_vq = virtio_add_queue(vdev, VHOST_VSOCK_QUEUE_SIZE,
+ vhost_vsock_common_handle_output);
+
+ vvc->vhost_dev.nvqs = ARRAY_SIZE(vvc->vhost_vqs);
+ vvc->vhost_dev.vqs = vvc->vhost_vqs;
+
+ vvc->post_load_timer = NULL;
+}
+
+void vhost_vsock_common_unrealize(VirtIODevice *vdev)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+
+ vhost_vsock_common_post_load_timer_cleanup(vvc);
+
+ virtio_delete_queue(vvc->recv_vq);
+ virtio_delete_queue(vvc->trans_vq);
+ virtio_delete_queue(vvc->event_vq);
+ virtio_cleanup(vdev);
+}
+
+static void vhost_vsock_common_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
+
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+ vdc->guest_notifier_mask = vhost_vsock_common_guest_notifier_mask;
+ vdc->guest_notifier_pending = vhost_vsock_common_guest_notifier_pending;
+}
+
+static const TypeInfo vhost_vsock_common_info = {
+ .name = TYPE_VHOST_VSOCK_COMMON,
+ .parent = TYPE_VIRTIO_DEVICE,
+ .instance_size = sizeof(VHostVSockCommon),
+ .class_init = vhost_vsock_common_class_init,
+ .abstract = true,
+};
+
+static void vhost_vsock_common_register_types(void)
+{
+ type_register_static(&vhost_vsock_common_info);
+}
+
+type_init(vhost_vsock_common_register_types)
*/
#include "qemu/osdep.h"
-#include <sys/ioctl.h>
#include "standard-headers/linux/virtio_vsock.h"
#include "qapi/error.h"
-#include "hw/virtio/virtio-bus.h"
#include "hw/virtio/virtio-access.h"
#include "qemu/error-report.h"
#include "hw/qdev-properties.h"
#include "hw/virtio/vhost-vsock.h"
-#include "qemu/iov.h"
-#include "qemu/module.h"
#include "monitor/monitor.h"
-enum {
- VHOST_VSOCK_SAVEVM_VERSION = 0,
-
- VHOST_VSOCK_QUEUE_SIZE = 128,
-};
-
static void vhost_vsock_get_config(VirtIODevice *vdev, uint8_t *config)
{
VHostVSock *vsock = VHOST_VSOCK(vdev);
memcpy(config, &vsockcfg, sizeof(vsockcfg));
}
-static int vhost_vsock_set_guest_cid(VHostVSock *vsock)
+static int vhost_vsock_set_guest_cid(VirtIODevice *vdev)
{
- const VhostOps *vhost_ops = vsock->vhost_dev.vhost_ops;
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+ VHostVSock *vsock = VHOST_VSOCK(vdev);
+ const VhostOps *vhost_ops = vvc->vhost_dev.vhost_ops;
int ret;
if (!vhost_ops->vhost_vsock_set_guest_cid) {
return -ENOSYS;
}
- ret = vhost_ops->vhost_vsock_set_guest_cid(&vsock->vhost_dev,
+ ret = vhost_ops->vhost_vsock_set_guest_cid(&vvc->vhost_dev,
vsock->conf.guest_cid);
if (ret < 0) {
return -errno;
return 0;
}
-static int vhost_vsock_set_running(VHostVSock *vsock, int start)
+static int vhost_vsock_set_running(VirtIODevice *vdev, int start)
{
- const VhostOps *vhost_ops = vsock->vhost_dev.vhost_ops;
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+ const VhostOps *vhost_ops = vvc->vhost_dev.vhost_ops;
int ret;
if (!vhost_ops->vhost_vsock_set_running) {
return -ENOSYS;
}
- ret = vhost_ops->vhost_vsock_set_running(&vsock->vhost_dev, start);
+ ret = vhost_ops->vhost_vsock_set_running(&vvc->vhost_dev, start);
if (ret < 0) {
return -errno;
}
return 0;
}
-static void vhost_vsock_start(VirtIODevice *vdev)
-{
- VHostVSock *vsock = VHOST_VSOCK(vdev);
- BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
- VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus);
- int ret;
- int i;
-
- if (!k->set_guest_notifiers) {
- error_report("binding does not support guest notifiers");
- return;
- }
-
- ret = vhost_dev_enable_notifiers(&vsock->vhost_dev, vdev);
- if (ret < 0) {
- error_report("Error enabling host notifiers: %d", -ret);
- return;
- }
-
- ret = k->set_guest_notifiers(qbus->parent, vsock->vhost_dev.nvqs, true);
- if (ret < 0) {
- error_report("Error binding guest notifier: %d", -ret);
- goto err_host_notifiers;
- }
-
- vsock->vhost_dev.acked_features = vdev->guest_features;
- ret = vhost_dev_start(&vsock->vhost_dev, vdev);
- if (ret < 0) {
- error_report("Error starting vhost: %d", -ret);
- goto err_guest_notifiers;
- }
-
- ret = vhost_vsock_set_running(vsock, 1);
- if (ret < 0) {
- error_report("Error starting vhost vsock: %d", -ret);
- goto err_dev_start;
- }
-
- /* guest_notifier_mask/pending not used yet, so just unmask
- * everything here. virtio-pci will do the right thing by
- * enabling/disabling irqfd.
- */
- for (i = 0; i < vsock->vhost_dev.nvqs; i++) {
- vhost_virtqueue_mask(&vsock->vhost_dev, vdev, i, false);
- }
-
- return;
-
-err_dev_start:
- vhost_dev_stop(&vsock->vhost_dev, vdev);
-err_guest_notifiers:
- k->set_guest_notifiers(qbus->parent, vsock->vhost_dev.nvqs, false);
-err_host_notifiers:
- vhost_dev_disable_notifiers(&vsock->vhost_dev, vdev);
-}
-
-static void vhost_vsock_stop(VirtIODevice *vdev)
-{
- VHostVSock *vsock = VHOST_VSOCK(vdev);
- BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
- VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus);
- int ret;
-
- if (!k->set_guest_notifiers) {
- return;
- }
-
- ret = vhost_vsock_set_running(vsock, 0);
- if (ret < 0) {
- error_report("vhost vsock set running failed: %d", ret);
- return;
- }
-
- vhost_dev_stop(&vsock->vhost_dev, vdev);
-
- ret = k->set_guest_notifiers(qbus->parent, vsock->vhost_dev.nvqs, false);
- if (ret < 0) {
- error_report("vhost guest notifier cleanup failed: %d", ret);
- return;
- }
-
- vhost_dev_disable_notifiers(&vsock->vhost_dev, vdev);
-}
static void vhost_vsock_set_status(VirtIODevice *vdev, uint8_t status)
{
- VHostVSock *vsock = VHOST_VSOCK(vdev);
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
bool should_start = status & VIRTIO_CONFIG_S_DRIVER_OK;
+ int ret;
if (!vdev->vm_running) {
should_start = false;
}
- if (vsock->vhost_dev.started == should_start) {
+ if (vvc->vhost_dev.started == should_start) {
return;
}
if (should_start) {
- vhost_vsock_start(vdev);
+ ret = vhost_vsock_common_start(vdev);
+ if (ret < 0) {
+ return;
+ }
+
+ ret = vhost_vsock_set_running(vdev, 1);
+ if (ret < 0) {
+ vhost_vsock_common_stop(vdev);
+ error_report("Error starting vhost vsock: %d", -ret);
+ return;
+ }
} else {
- vhost_vsock_stop(vdev);
+ ret = vhost_vsock_set_running(vdev, 0);
+ if (ret < 0) {
+ error_report("vhost vsock set running failed: %d", ret);
+ return;
+ }
+
+ vhost_vsock_common_stop(vdev);
}
}
return requested_features;
}
-static void vhost_vsock_handle_output(VirtIODevice *vdev, VirtQueue *vq)
-{
- /* Do nothing */
-}
-
-static void vhost_vsock_guest_notifier_mask(VirtIODevice *vdev, int idx,
- bool mask)
-{
- VHostVSock *vsock = VHOST_VSOCK(vdev);
-
- vhost_virtqueue_mask(&vsock->vhost_dev, vdev, idx, mask);
-}
-
-static bool vhost_vsock_guest_notifier_pending(VirtIODevice *vdev, int idx)
-{
- VHostVSock *vsock = VHOST_VSOCK(vdev);
-
- return vhost_virtqueue_pending(&vsock->vhost_dev, idx);
-}
-
-static void vhost_vsock_send_transport_reset(VHostVSock *vsock)
-{
- VirtQueueElement *elem;
- VirtQueue *vq = vsock->event_vq;
- struct virtio_vsock_event event = {
- .id = cpu_to_le32(VIRTIO_VSOCK_EVENT_TRANSPORT_RESET),
- };
-
- elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
- if (!elem) {
- error_report("vhost-vsock missed transport reset event");
- return;
- }
-
- if (elem->out_num) {
- error_report("invalid vhost-vsock event virtqueue element with "
- "out buffers");
- goto out;
- }
-
- if (iov_from_buf(elem->in_sg, elem->in_num, 0,
- &event, sizeof(event)) != sizeof(event)) {
- error_report("vhost-vsock event virtqueue element is too short");
- goto out;
- }
-
- virtqueue_push(vq, elem, sizeof(event));
- virtio_notify(VIRTIO_DEVICE(vsock), vq);
-
-out:
- g_free(elem);
-}
-
-static void vhost_vsock_post_load_timer_cleanup(VHostVSock *vsock)
-{
- if (!vsock->post_load_timer) {
- return;
- }
-
- timer_del(vsock->post_load_timer);
- timer_free(vsock->post_load_timer);
- vsock->post_load_timer = NULL;
-}
-
-static void vhost_vsock_post_load_timer_cb(void *opaque)
-{
- VHostVSock *vsock = opaque;
-
- vhost_vsock_post_load_timer_cleanup(vsock);
- vhost_vsock_send_transport_reset(vsock);
-}
-
-static int vhost_vsock_pre_save(void *opaque)
-{
- VHostVSock *vsock = opaque;
-
- /* At this point, backend must be stopped, otherwise
- * it might keep writing to memory. */
- assert(!vsock->vhost_dev.started);
-
- return 0;
-}
-
-static int vhost_vsock_post_load(void *opaque, int version_id)
-{
- VHostVSock *vsock = opaque;
- VirtIODevice *vdev = VIRTIO_DEVICE(vsock);
-
- if (virtio_queue_get_addr(vdev, 2)) {
- /* Defer transport reset event to a vm clock timer so that virtqueue
- * changes happen after migration has completed.
- */
- assert(!vsock->post_load_timer);
- vsock->post_load_timer =
- timer_new_ns(QEMU_CLOCK_VIRTUAL,
- vhost_vsock_post_load_timer_cb,
- vsock);
- timer_mod(vsock->post_load_timer, 1);
- }
- return 0;
-}
-
static const VMStateDescription vmstate_virtio_vhost_vsock = {
.name = "virtio-vhost_vsock",
.minimum_version_id = VHOST_VSOCK_SAVEVM_VERSION,
VMSTATE_VIRTIO_DEVICE,
VMSTATE_END_OF_LIST()
},
- .pre_save = vhost_vsock_pre_save,
- .post_load = vhost_vsock_post_load,
+ .pre_save = vhost_vsock_common_pre_save,
+ .post_load = vhost_vsock_common_post_load,
};
static void vhost_vsock_device_realize(DeviceState *dev, Error **errp)
{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(dev);
VirtIODevice *vdev = VIRTIO_DEVICE(dev);
VHostVSock *vsock = VHOST_VSOCK(dev);
int vhostfd;
}
}
- virtio_init(vdev, "vhost-vsock", VIRTIO_ID_VSOCK,
- sizeof(struct virtio_vsock_config));
-
- /* Receive and transmit queues belong to vhost */
- vsock->recv_vq = virtio_add_queue(vdev, VHOST_VSOCK_QUEUE_SIZE,
- vhost_vsock_handle_output);
- vsock->trans_vq = virtio_add_queue(vdev, VHOST_VSOCK_QUEUE_SIZE,
- vhost_vsock_handle_output);
+ vhost_vsock_common_realize(vdev, "vhost-vsock");
- /* The event queue belongs to QEMU */
- vsock->event_vq = virtio_add_queue(vdev, VHOST_VSOCK_QUEUE_SIZE,
- vhost_vsock_handle_output);
-
- vsock->vhost_dev.nvqs = ARRAY_SIZE(vsock->vhost_vqs);
- vsock->vhost_dev.vqs = vsock->vhost_vqs;
- ret = vhost_dev_init(&vsock->vhost_dev, (void *)(uintptr_t)vhostfd,
+ ret = vhost_dev_init(&vvc->vhost_dev, (void *)(uintptr_t)vhostfd,
VHOST_BACKEND_TYPE_KERNEL, 0);
if (ret < 0) {
error_setg_errno(errp, -ret, "vhost-vsock: vhost_dev_init failed");
goto err_virtio;
}
- ret = vhost_vsock_set_guest_cid(vsock);
+ ret = vhost_vsock_set_guest_cid(vdev);
if (ret < 0) {
error_setg_errno(errp, -ret, "vhost-vsock: unable to set guest cid");
goto err_vhost_dev;
}
- vsock->post_load_timer = NULL;
return;
err_vhost_dev:
- vhost_dev_cleanup(&vsock->vhost_dev);
+ vhost_dev_cleanup(&vvc->vhost_dev);
/* vhost_dev_cleanup() closes the vhostfd passed to vhost_dev_init() */
vhostfd = -1;
err_virtio:
- virtio_delete_queue(vsock->recv_vq);
- virtio_delete_queue(vsock->trans_vq);
- virtio_delete_queue(vsock->event_vq);
- virtio_cleanup(vdev);
+ vhost_vsock_common_unrealize(vdev);
if (vhostfd >= 0) {
close(vhostfd);
}
static void vhost_vsock_device_unrealize(DeviceState *dev)
{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(dev);
VirtIODevice *vdev = VIRTIO_DEVICE(dev);
- VHostVSock *vsock = VHOST_VSOCK(dev);
-
- vhost_vsock_post_load_timer_cleanup(vsock);
/* This will stop vhost backend if appropriate. */
vhost_vsock_set_status(vdev, 0);
- vhost_dev_cleanup(&vsock->vhost_dev);
- virtio_delete_queue(vsock->recv_vq);
- virtio_delete_queue(vsock->trans_vq);
- virtio_delete_queue(vsock->event_vq);
- virtio_cleanup(vdev);
+ vhost_dev_cleanup(&vvc->vhost_dev);
+ vhost_vsock_common_unrealize(vdev);
}
static Property vhost_vsock_properties[] = {
device_class_set_props(dc, vhost_vsock_properties);
dc->vmsd = &vmstate_virtio_vhost_vsock;
- set_bit(DEVICE_CATEGORY_MISC, dc->categories);
vdc->realize = vhost_vsock_device_realize;
vdc->unrealize = vhost_vsock_device_unrealize;
vdc->get_features = vhost_vsock_get_features;
vdc->get_config = vhost_vsock_get_config;
vdc->set_status = vhost_vsock_set_status;
- vdc->guest_notifier_mask = vhost_vsock_guest_notifier_mask;
- vdc->guest_notifier_pending = vhost_vsock_guest_notifier_pending;
}
static const TypeInfo vhost_vsock_info = {
.name = TYPE_VHOST_VSOCK,
- .parent = TYPE_VIRTIO_DEVICE,
+ .parent = TYPE_VHOST_VSOCK_COMMON,
.instance_size = sizeof(VHostVSock),
.class_init = vhost_vsock_class_init,
};
#include "migration/blocker.h"
#include "migration/qemu-file-types.h"
#include "sysemu/dma.h"
+#include "sysemu/tcg.h"
#include "trace.h"
/* enabled until disconnected backend stabilizes */
return r;
}
+/*
+ * vhost_section: identify sections needed for vhost access
+ *
+ * We only care about RAM sections here (where virtqueue and guest
+ * internals accessed by virtio might live). If we find one we still
+ * allow the backend to potentially filter it out of our list.
+ */
static bool vhost_section(struct vhost_dev *dev, MemoryRegionSection *section)
{
- bool result;
- bool log_dirty = memory_region_get_dirty_log_mask(section->mr) &
- ~(1 << DIRTY_MEMORY_MIGRATION);
- result = memory_region_is_ram(section->mr) &&
- !memory_region_is_rom(section->mr);
-
- /* Vhost doesn't handle any block which is doing dirty-tracking other
- * than migration; this typically fires on VGA areas.
- */
- result &= !log_dirty;
+ MemoryRegion *mr = section->mr;
+
+ if (memory_region_is_ram(mr) && !memory_region_is_rom(mr)) {
+ uint8_t dirty_mask = memory_region_get_dirty_log_mask(mr);
+ uint8_t handled_dirty;
+
+ /*
+ * Kernel based vhost doesn't handle any block which is doing
+ * dirty-tracking other than migration for which it has
+ * specific logging support. However for TCG the kernel never
+ * gets involved anyway so we can also ignore it's
+ * self-modiying code detection flags. However a vhost-user
+ * client could still confuse a TCG guest if it re-writes
+ * executable memory that has already been translated.
+ */
+ handled_dirty = (1 << DIRTY_MEMORY_MIGRATION) |
+ (1 << DIRTY_MEMORY_CODE);
- if (result && dev->vhost_ops->vhost_backend_mem_section_filter) {
- result &=
- dev->vhost_ops->vhost_backend_mem_section_filter(dev, section);
- }
+ if (dirty_mask & ~handled_dirty) {
+ trace_vhost_reject_section(mr->name, 1);
+ return false;
+ }
+
+ if (dev->vhost_ops->vhost_backend_mem_section_filter &&
+ !dev->vhost_ops->vhost_backend_mem_section_filter(dev, section)) {
+ trace_vhost_reject_section(mr->name, 2);
+ return false;
+ }
- trace_vhost_section(section->mr->name, result);
- return result;
+ trace_vhost_section(mr->name);
+ return true;
+ } else {
+ trace_vhost_reject_section(mr->name, 3);
+ return false;
+ }
}
static void vhost_begin(MemoryListener *listener)
return r;
}
-static int vhost_migration_log(MemoryListener *listener, int enable)
+static int vhost_migration_log(MemoryListener *listener, bool enable)
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
int r;
- if (!!enable == dev->log_enabled) {
+ if (enable == dev->log_enabled) {
return 0;
}
if (!dev->started) {
balloon_stats_change_timer(s, 0);
}
+static void virtio_balloon_handle_report(VirtIODevice *vdev, VirtQueue *vq)
+{
+ VirtIOBalloon *dev = VIRTIO_BALLOON(vdev);
+ VirtQueueElement *elem;
+
+ while ((elem = virtqueue_pop(vq, sizeof(VirtQueueElement)))) {
+ unsigned int i;
+
+ /*
+ * When we discard the page it has the effect of removing the page
+ * from the hypervisor itself and causing it to be zeroed when it
+ * is returned to us. So we must not discard the page if it is
+ * accessible by another device or process, or if the guest is
+ * expecting it to retain a non-zero value.
+ */
+ if (qemu_balloon_is_inhibited() || dev->poison_val) {
+ goto skip_element;
+ }
+
+ for (i = 0; i < elem->in_num; i++) {
+ void *addr = elem->in_sg[i].iov_base;
+ size_t size = elem->in_sg[i].iov_len;
+ ram_addr_t ram_offset;
+ RAMBlock *rb;
+
+ /*
+ * There is no need to check the memory section to see if
+ * it is ram/readonly/romd like there is for handle_output
+ * below. If the region is not meant to be written to then
+ * address_space_map will have allocated a bounce buffer
+ * and it will be freed in address_space_unmap and trigger
+ * and unassigned_mem_write before failing to copy over the
+ * buffer. If more than one bad descriptor is provided it
+ * will return NULL after the first bounce buffer and fail
+ * to map any resources.
+ */
+ rb = qemu_ram_block_from_host(addr, false, &ram_offset);
+ if (!rb) {
+ trace_virtio_balloon_bad_addr(elem->in_addr[i]);
+ continue;
+ }
+
+ /*
+ * For now we will simply ignore unaligned memory regions, or
+ * regions that overrun the end of the RAMBlock.
+ */
+ if (!QEMU_IS_ALIGNED(ram_offset | size, qemu_ram_pagesize(rb)) ||
+ (ram_offset + size) > qemu_ram_get_used_length(rb)) {
+ continue;
+ }
+
+ ram_block_discard_range(rb, ram_offset, size);
+ }
+
+skip_element:
+ virtqueue_push(vq, elem, 0);
+ virtio_notify(vdev, vq);
+ g_free(elem);
+ }
+}
+
static void virtio_balloon_handle_output(VirtIODevice *vdev, VirtQueue *vq)
{
VirtIOBalloon *s = VIRTIO_BALLOON(vdev);
config.num_pages = cpu_to_le32(dev->num_pages);
config.actual = cpu_to_le32(dev->actual);
+ config.poison_val = cpu_to_le32(dev->poison_val);
if (dev->free_page_report_status == FREE_PAGE_REPORT_S_REQUESTED) {
config.free_page_report_cmd_id =
return size;
}
+static bool virtio_balloon_page_poison_support(void *opaque)
+{
+ VirtIOBalloon *s = opaque;
+ VirtIODevice *vdev = VIRTIO_DEVICE(s);
+
+ return virtio_vdev_has_feature(vdev, VIRTIO_BALLOON_F_PAGE_POISON);
+}
+
static void virtio_balloon_set_config(VirtIODevice *vdev,
const uint8_t *config_data)
{
qapi_event_send_balloon_change(vm_ram_size -
((ram_addr_t) dev->actual << VIRTIO_BALLOON_PFN_SHIFT));
}
+ dev->poison_val = 0;
+ if (virtio_balloon_page_poison_support(dev)) {
+ dev->poison_val = le32_to_cpu(config.poison_val);
+ }
trace_virtio_balloon_set_config(dev->actual, oldactual);
}
}
};
+static const VMStateDescription vmstate_virtio_balloon_page_poison = {
+ .name = "vitio-balloon-device/page-poison",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = virtio_balloon_page_poison_support,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(poison_val, VirtIOBalloon),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_virtio_balloon_device = {
.name = "virtio-balloon-device",
.version_id = 1,
},
.subsections = (const VMStateDescription * []) {
&vmstate_virtio_balloon_free_page_report,
+ &vmstate_virtio_balloon_page_poison,
NULL
}
};
return;
}
+ if (virtio_has_feature(s->host_features, VIRTIO_BALLOON_F_FREE_PAGE_HINT) &&
+ !s->iothread) {
+ error_setg(errp, "'free-page-hint' requires 'iothread' to be set");
+ virtio_cleanup(vdev);
+ return;
+ }
+
s->ivq = virtio_add_queue(vdev, 128, virtio_balloon_handle_output);
s->dvq = virtio_add_queue(vdev, 128, virtio_balloon_handle_output);
s->svq = virtio_add_queue(vdev, 128, virtio_balloon_receive_stats);
VIRTIO_BALLOON_F_FREE_PAGE_HINT)) {
s->free_page_vq = virtio_add_queue(vdev, VIRTQUEUE_MAX_SIZE,
virtio_balloon_handle_free_page_vq);
- s->free_page_report_status = FREE_PAGE_REPORT_S_STOP;
- s->free_page_report_cmd_id =
- VIRTIO_BALLOON_FREE_PAGE_REPORT_CMD_ID_MIN;
- s->free_page_report_notify.notify =
- virtio_balloon_free_page_report_notify;
precopy_add_notifier(&s->free_page_report_notify);
- if (s->iothread) {
- object_ref(OBJECT(s->iothread));
- s->free_page_bh = aio_bh_new(iothread_get_aio_context(s->iothread),
- virtio_ballloon_get_free_page_hints, s);
- qemu_mutex_init(&s->free_page_lock);
- qemu_cond_init(&s->free_page_cond);
- s->block_iothread = false;
- } else {
- /* Simply disable this feature if the iothread wasn't created. */
- s->host_features &= ~(1 << VIRTIO_BALLOON_F_FREE_PAGE_HINT);
- virtio_error(vdev, "iothread is missing");
- }
+
+ object_ref(OBJECT(s->iothread));
+ s->free_page_bh = aio_bh_new(iothread_get_aio_context(s->iothread),
+ virtio_ballloon_get_free_page_hints, s);
}
+
+ if (virtio_has_feature(s->host_features, VIRTIO_BALLOON_F_REPORTING)) {
+ s->reporting_vq = virtio_add_queue(vdev, 32,
+ virtio_balloon_handle_report);
+ }
+
reset_stats(s);
}
VirtIODevice *vdev = VIRTIO_DEVICE(dev);
VirtIOBalloon *s = VIRTIO_BALLOON(dev);
- if (virtio_balloon_free_page_support(s)) {
+ if (s->free_page_bh) {
qemu_bh_delete(s->free_page_bh);
+ object_unref(OBJECT(s->iothread));
virtio_balloon_free_page_stop(s);
precopy_remove_notifier(&s->free_page_report_notify);
}
if (s->free_page_vq) {
virtio_delete_queue(s->free_page_vq);
}
+ if (s->reporting_vq) {
+ virtio_delete_queue(s->reporting_vq);
+ }
virtio_cleanup(vdev);
}
g_free(s->stats_vq_elem);
s->stats_vq_elem = NULL;
}
+
+ s->poison_val = 0;
}
static void virtio_balloon_set_status(VirtIODevice *vdev, uint8_t status)
{
VirtIOBalloon *s = VIRTIO_BALLOON(obj);
+ qemu_mutex_init(&s->free_page_lock);
+ qemu_cond_init(&s->free_page_cond);
+ s->free_page_report_cmd_id = VIRTIO_BALLOON_FREE_PAGE_REPORT_CMD_ID_MIN;
+ s->free_page_report_notify.notify = virtio_balloon_free_page_report_notify;
+
object_property_add(obj, "guest-stats", "guest statistics",
balloon_stats_get_all, NULL, NULL, s);
VIRTIO_BALLOON_F_DEFLATE_ON_OOM, false),
DEFINE_PROP_BIT("free-page-hint", VirtIOBalloon, host_features,
VIRTIO_BALLOON_F_FREE_PAGE_HINT, false),
+ DEFINE_PROP_BIT("page-poison", VirtIOBalloon, host_features,
+ VIRTIO_BALLOON_F_PAGE_POISON, true),
+ DEFINE_PROP_BIT("free-page-reporting", VirtIOBalloon, host_features,
+ VIRTIO_BALLOON_F_REPORTING, false),
/* QEMU 4.0 accidentally changed the config size even when free-page-hint
* is disabled, resulting in QEMU 3.1 migration incompatibility. This
* property retains this quirk for QEMU 4.1 machine types.
virtio_queue_set_vector(vdev, vdev->queue_sel, val);
break;
case VIRTIO_PCI_COMMON_Q_ENABLE:
- virtio_queue_set_num(vdev, vdev->queue_sel,
- proxy->vqs[vdev->queue_sel].num);
- virtio_queue_set_rings(vdev, vdev->queue_sel,
+ if (val == 1) {
+ virtio_queue_set_num(vdev, vdev->queue_sel,
+ proxy->vqs[vdev->queue_sel].num);
+ virtio_queue_set_rings(vdev, vdev->queue_sel,
((uint64_t)proxy->vqs[vdev->queue_sel].desc[1]) << 32 |
proxy->vqs[vdev->queue_sel].desc[0],
((uint64_t)proxy->vqs[vdev->queue_sel].avail[1]) << 32 |
proxy->vqs[vdev->queue_sel].avail[0],
((uint64_t)proxy->vqs[vdev->queue_sel].used[1]) << 32 |
proxy->vqs[vdev->queue_sel].used[0]);
- proxy->vqs[vdev->queue_sel].enabled = 1;
+ proxy->vqs[vdev->queue_sel].enabled = 1;
+ } else {
+ virtio_error(vdev, "wrong value for queue_enable %"PRIx64, val);
+ }
break;
case VIRTIO_PCI_COMMON_Q_DESCLO:
proxy->vqs[vdev->queue_sel].desc[0] = val;
struct AcpiGenericAddress pm_tmr; /* PM_TMR_BLK */
struct AcpiGenericAddress gpe0_blk; /* GPE0_BLK */
struct AcpiGenericAddress reset_reg; /* RESET_REG */
+ struct AcpiGenericAddress sleep_ctl; /* SLEEP_CONTROL_REG */
+ struct AcpiGenericAddress sleep_sts; /* SLEEP_STATUS_REG */
uint8_t reset_val; /* RESET_VALUE */
uint8_t rev; /* Revision */
uint32_t flags; /* Flags */
void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f,
const char *oem_id, const char *oem_table_id);
+
+void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog);
#endif
#define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4
typedef struct GEDState {
- MemoryRegion io;
+ MemoryRegion evt;
uint32_t sel;
} GEDState;
void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io,
struct AcpiGenericAddress dsm_io,
FWCfgState *fw_cfg, Object *owner);
+void nvdimm_build_srat(GArray *table_data);
void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, NVDIMMState *state,
uint32_t ram_slots);
--- /dev/null
+/*
+ * Vhost-user vsock virtio device
+ *
+ * Copyright 2020 Red Hat, Inc.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version. See the COPYING file in the
+ * top-level directory.
+ */
+
+#ifndef _QEMU_VHOST_USER_VSOCK_H
+#define _QEMU_VHOST_USER_VSOCK_H
+
+#include "hw/virtio/vhost-vsock-common.h"
+#include "hw/virtio/vhost-user.h"
+#include "standard-headers/linux/virtio_vsock.h"
+
+#define TYPE_VHOST_USER_VSOCK "vhost-user-vsock-device"
+#define VHOST_USER_VSOCK(obj) \
+ OBJECT_CHECK(VHostUserVSock, (obj), TYPE_VHOST_USER_VSOCK)
+
+typedef struct {
+ CharBackend chardev;
+} VHostUserVSockConf;
+
+typedef struct {
+ /*< private >*/
+ VHostVSockCommon parent;
+ VhostUserState vhost_user;
+ VHostUserVSockConf conf;
+ struct virtio_vsock_config vsockcfg;
+
+ /*< public >*/
+} VHostUserVSock;
+
+#endif /* _QEMU_VHOST_USER_VSOCK_H */
typedef struct VhostUserState {
CharBackend *chr;
VhostUserHostNotifier notifier[VIRTIO_QUEUE_MAX];
+ int memory_slots;
} VhostUserState;
bool vhost_user_init(VhostUserState *user, CharBackend *chr, Error **errp);
--- /dev/null
+/*
+ * Parent class for vhost-vsock devices
+ *
+ * Copyright 2015-2020 Red Hat, Inc.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version. See the COPYING file in the
+ * top-level directory.
+ */
+
+#ifndef _QEMU_VHOST_VSOCK_COMMON_H
+#define _QEMU_VHOST_VSOCK_COMMON_H
+
+#include "hw/virtio/virtio.h"
+#include "hw/virtio/vhost.h"
+
+#define TYPE_VHOST_VSOCK_COMMON "vhost-vsock-common"
+#define VHOST_VSOCK_COMMON(obj) \
+ OBJECT_CHECK(VHostVSockCommon, (obj), TYPE_VHOST_VSOCK_COMMON)
+
+enum {
+ VHOST_VSOCK_SAVEVM_VERSION = 0,
+
+ VHOST_VSOCK_QUEUE_SIZE = 128,
+};
+
+typedef struct {
+ VirtIODevice parent;
+
+ struct vhost_virtqueue vhost_vqs[2];
+ struct vhost_dev vhost_dev;
+
+ VirtQueue *event_vq;
+ VirtQueue *recv_vq;
+ VirtQueue *trans_vq;
+
+ QEMUTimer *post_load_timer;
+} VHostVSockCommon;
+
+int vhost_vsock_common_start(VirtIODevice *vdev);
+void vhost_vsock_common_stop(VirtIODevice *vdev);
+int vhost_vsock_common_pre_save(void *opaque);
+int vhost_vsock_common_post_load(void *opaque, int version_id);
+void vhost_vsock_common_realize(VirtIODevice *vdev, const char *name);
+void vhost_vsock_common_unrealize(VirtIODevice *vdev);
+
+#endif /* _QEMU_VHOST_VSOCK_COMMON_H */
#ifndef QEMU_VHOST_VSOCK_H
#define QEMU_VHOST_VSOCK_H
-#include "hw/virtio/virtio.h"
-#include "hw/virtio/vhost.h"
+#include "hw/virtio/vhost-vsock-common.h"
#define TYPE_VHOST_VSOCK "vhost-vsock-device"
#define VHOST_VSOCK(obj) \
typedef struct {
/*< private >*/
- VirtIODevice parent;
+ VHostVSockCommon parent;
VHostVSockConf conf;
- struct vhost_virtqueue vhost_vqs[2];
- struct vhost_dev vhost_dev;
- VirtQueue *event_vq;
- VirtQueue *recv_vq;
- VirtQueue *trans_vq;
- QEMUTimer *post_load_timer;
/*< public >*/
} VHostVSock;
typedef struct VirtIOBalloon {
VirtIODevice parent_obj;
- VirtQueue *ivq, *dvq, *svq, *free_page_vq;
+ VirtQueue *ivq, *dvq, *svq, *free_page_vq, *reporting_vq;
uint32_t free_page_report_status;
uint32_t num_pages;
uint32_t actual;
uint32_t host_features;
bool qemu_4_0_config_size;
+ uint32_t poison_val;
} VirtIOBalloon;
#endif
#include <inttypes.h>
#include <stdbool.h>
+#include <stddef.h>
/*
* For best performance, build the plugin with -fvisibility=hidden so that
#define TPM_IS_TIS_ISA(chr) \
object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_ISA)
+#define TPM_IS_TIS_SYSBUS(chr) \
+ object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_SYSBUS)
#define TPM_IS_CRB(chr) \
object_dynamic_cast(OBJECT(chr), TYPE_TPM_CRB)
#define TPM_IS_SPAPR(chr) \
{
void *want = g2h(ARM_COMMPAGE & -qemu_host_page_size);
void *addr = mmap(want, qemu_host_page_size, PROT_READ | PROT_WRITE,
- MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
+ MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0);
if (addr == MAP_FAILED) {
perror("Allocating guest commpage");
}
}
+/**
+ * pgd_find_hole_fallback: potential mmap address
+ * @guest_size: size of available space
+ * @brk: location of break
+ * @align: memory alignment
+ *
+ * This is a fallback method for finding a hole in the host address
+ * space if we don't have the benefit of being able to access
+ * /proc/self/map. It can potentially take a very long time as we can
+ * only dumbly iterate up the host address space seeing if the
+ * allocation would work.
+ */
+static uintptr_t pgd_find_hole_fallback(uintptr_t guest_size, uintptr_t brk,
+ long align, uintptr_t offset)
+{
+ uintptr_t base;
+
+ /* Start (aligned) at the bottom and work our way up */
+ base = ROUND_UP(mmap_min_addr, align);
+
+ while (true) {
+ uintptr_t align_start, end;
+ align_start = ROUND_UP(base, align);
+ end = align_start + guest_size + offset;
+
+ /* if brk is anywhere in the range give ourselves some room to grow. */
+ if (align_start <= brk && brk < end) {
+ base = brk + (16 * MiB);
+ continue;
+ } else if (align_start + guest_size < align_start) {
+ /* we have run out of space */
+ return -1;
+ } else {
+ int flags = MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE | MAP_FIXED;
+ void * mmap_start = mmap((void *) align_start, guest_size,
+ PROT_NONE, flags, -1, 0);
+ if (mmap_start != MAP_FAILED) {
+ munmap((void *) align_start, guest_size);
+ return (uintptr_t) mmap_start + offset;
+ }
+ base += qemu_host_page_size;
+ }
+ }
+}
+
/* Return value for guest_base, or -1 if no hole found. */
static uintptr_t pgb_find_hole(uintptr_t guest_loaddr, uintptr_t guest_size,
- long align)
+ long align, uintptr_t offset)
{
GSList *maps, *iter;
uintptr_t this_start, this_end, next_start, brk;
/* Read brk after we've read the maps, which will malloc. */
brk = (uintptr_t)sbrk(0);
+ if (!maps) {
+ return pgd_find_hole_fallback(guest_size, brk, align, offset);
+ }
+
/* The first hole is before the first map entry. */
this_start = mmap_min_addr;
this_end = ((MapInfo *)iter->data)->start;
next_start = ((MapInfo *)iter->data)->end;
- align_start = ROUND_UP(this_start, align);
+ align_start = ROUND_UP(this_start + offset, align);
/* Skip holes that are too small. */
if (align_start >= this_end) {
{
uintptr_t loaddr = orig_loaddr;
uintptr_t hiaddr = orig_hiaddr;
+ uintptr_t offset = 0;
uintptr_t addr;
if (hiaddr != orig_hiaddr) {
if (ARM_COMMPAGE) {
/*
* Extend the allocation to include the commpage.
- * For a 64-bit host, this is just 4GiB; for a 32-bit host,
- * the address arithmetic will wrap around, but the difference
- * will produce the correct allocation size.
+ * For a 64-bit host, this is just 4GiB; for a 32-bit host we
+ * need to ensure there is space bellow the guest_base so we
+ * can map the commpage in the place needed when the address
+ * arithmetic wraps around.
*/
if (sizeof(uintptr_t) == 8 || loaddr >= 0x80000000u) {
- hiaddr = (uintptr_t)4 << 30;
+ hiaddr = (uintptr_t) 4 << 30;
} else {
- loaddr = ARM_COMMPAGE & -align;
+ offset = -(ARM_COMMPAGE & -align);
}
}
- addr = pgb_find_hole(loaddr, hiaddr - loaddr, align);
+ addr = pgb_find_hole(loaddr, hiaddr - loaddr, align, offset);
if (addr == -1) {
/*
* If ARM_COMMPAGE, there *might* be a non-consecutive allocation
* just above that, and maximises the positive guest addresses.
*/
commpage = ARM_COMMPAGE & -align;
- addr = pgb_find_hole(commpage, -commpage, align);
+ addr = pgb_find_hole(commpage, -commpage, align, 0);
assert(addr != -1);
guest_base = addr;
}
* It can fail only on 64-bit host with 32-bit target.
* On any other target/host host mmap() handles this error correctly.
*/
- if (!guest_range_valid(start, len)) {
+ if (end < start || !guest_range_valid(start, len)) {
errno = ENOMEM;
goto fail;
}
}
if (dev->has_irq) {
- monitor_printf(mon, " IRQ %" PRId64 ".\n", dev->irq);
+ monitor_printf(mon, " IRQ %" PRId64 ", pin %c\n",
+ dev->irq, (char)('A' + dev->irq_pin - 1));
}
if (dev->has_pci_bridge) {
msg = g_strdup_vprintf(fmt, va);
len = strlen(msg);
- assert(len < 4096);
+ assert(len < NBD_MAX_STRING_SIZE);
trace_nbd_negotiate_send_rep_err(msg);
ret = nbd_negotiate_send_rep_len(client, type, len, errp);
if (ret < 0) {
return 0;
}
+/*
+ * Return a malloc'd copy of @name suitable for use in an error reply.
+ */
+static char *
+nbd_sanitize_name(const char *name)
+{
+ if (strnlen(name, 80) < 80) {
+ return g_strdup(name);
+ }
+ /* XXX Should we also try to sanitize any control characters? */
+ return g_strdup_printf("%.80s...", name);
+}
+
/* Send an error reply.
* Return -errno on error, 0 on success. */
static int GCC_FMT_ATTR(4, 5)
exp = nbd_export_find(name);
if (!exp) {
+ g_autofree char *sane_name = nbd_sanitize_name(name);
+
return nbd_negotiate_send_rep_err(client, NBD_REP_ERR_UNKNOWN,
errp, "export '%s' not present",
- name);
+ sane_name);
}
/* Don't bother sending NBD_INFO_NAME unless client requested it */
meta->exp = nbd_export_find(export_name);
if (meta->exp == NULL) {
+ g_autofree char *sane_name = nbd_sanitize_name(export_name);
+
return nbd_opt_drop(client, NBD_REP_ERR_UNKNOWN, errp,
- "export '%s' not present", export_name);
+ "export '%s' not present", sane_name);
}
ret = nbd_opt_read(client, &nb_queries, sizeof(nb_queries), errp);
/* Create an ID if the user did not specify one */
nd_id = g_strdup(qemu_opts_id(opts));
if (!nd_id) {
- nd_id = g_strdup_printf("__org.qemu.nic%i\n", idx);
+ nd_id = g_strdup_printf("__org.qemu.nic%i", idx);
qemu_opts_set_id(opts, nd_id);
}
#
# @irq: if an IRQ is assigned to the device, the IRQ number
#
+# @irq_pin: the IRQ pin, zero means no IRQ (since 5.1)
+#
# @qdev_id: the device name of the PCI device
#
# @pci_bridge: if the device is a PCI bridge, the bridge information
{ 'struct': 'PciDeviceInfo',
'data': {'bus': 'int', 'slot': 'int', 'function': 'int',
'class_info': 'PciDeviceClass', 'id': 'PciDeviceId',
- '*irq': 'int', 'qdev_id': 'str', '*pci_bridge': 'PciBridgeInfo',
- 'regions': ['PciMemoryRegion']} }
+ '*irq': 'int', 'irq_pin': 'int', 'qdev_id': 'str',
+ '*pci_bridge': 'PciBridgeInfo', 'regions': ['PciMemoryRegion'] }}
##
# @PciInfo:
;;
*include/qemu/osdep.h | \
*include/qemu/compiler.h | \
+ *include/qemu/qemu-plugin.h | \
*include/glib-compat.h | \
*include/sysemu/os-posix.h | \
*include/sysemu/os-win32.h | \
ENV PACKAGES \
alsa-lib-devel \
bc \
- bison \
brlapi-devel \
bzip2 \
bzip2-devel \
dbus-daemon \
device-mapper-multipath-devel \
findutils \
- flex \
gcc \
gcc-c++ \
gettext \
fields = {}
arguments = {}
formats = {}
-patterns = []
allpatterns = []
anyextern = False
global output_file
global output_fd
+ prefix = ''
+ if file:
+ prefix += '{0}:'.format(file)
if lineno:
- r = '{0}:{1}: error:'.format(file, lineno)
- elif input_file:
- r = '{0}: error:'.format(file)
- else:
- r = 'error:'
- for a in args:
- r += ' ' + str(a)
- r += '\n'
- sys.stderr.write(r)
+ prefix += '{0}:'.format(lineno)
+ if prefix:
+ prefix += ' '
+ print(prefix, end='error: ', file=sys.stderr)
+ print(*args, file=sys.stderr)
+
if output_file and output_fd:
output_fd.close()
os.remove(output_file)
exit(1)
+# end error_with_file
+
def error(lineno, *args):
- error_with_file(input_file, lineno, args)
+ error_with_file(input_file, lineno, *args)
+# end error
+
def output(*args):
global output_fd
def ctz(x):
"""Return the number of times 2 factors into X."""
+ assert x != 0
r = 0
while ((x >> r) & 1) == 0:
r += 1
def is_contiguous(bits):
+ if bits == 0:
+ return -1
shift = ctz(bits)
if is_pow2((bits >> shift) + 1):
return shift
output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n')
output(ind, 'if (', translate_prefix, '_', self.name,
'(ctx, &u.f_', arg, ')) return true;\n')
+
+ # Normal patterns do not have children.
+ def build_tree(self):
+ return
+ def prop_masks(self):
+ return
+ def prop_format(self):
+ return
+ def prop_width(self):
+ return
+
# end Pattern
class MultiPattern(General):
- """Class representing an overlapping set of instruction patterns"""
+ """Class representing a set of instruction patterns"""
- def __init__(self, lineno, pats, fixb, fixm, udfm, w):
+ def __init__(self, lineno):
self.file = input_file
self.lineno = lineno
- self.pats = pats
+ self.pats = []
self.base = None
- self.fixedbits = fixb
- self.fixedmask = fixm
- self.undefmask = udfm
- self.width = w
+ self.fixedbits = 0
+ self.fixedmask = 0
+ self.undefmask = 0
+ self.width = None
def __str__(self):
- r = "{"
- for p in self.pats:
- r = r + ' ' + str(p)
- return r + "}"
+ r = 'group'
+ if self.fixedbits is not None:
+ r += ' ' + str_match_bits(self.fixedbits, self.fixedmask)
+ return r
def output_decl(self):
for p in self.pats:
p.output_decl()
+ def prop_masks(self):
+ global insnmask
+
+ fixedmask = insnmask
+ undefmask = insnmask
+
+ # Collect fixedmask/undefmask for all of the children.
+ for p in self.pats:
+ p.prop_masks()
+ fixedmask &= p.fixedmask
+ undefmask &= p.undefmask
+
+ # Widen fixedmask until all fixedbits match
+ repeat = True
+ fixedbits = 0
+ while repeat and fixedmask != 0:
+ fixedbits = None
+ for p in self.pats:
+ thisbits = p.fixedbits & fixedmask
+ if fixedbits is None:
+ fixedbits = thisbits
+ elif fixedbits != thisbits:
+ fixedmask &= ~(fixedbits ^ thisbits)
+ break
+ else:
+ repeat = False
+
+ self.fixedbits = fixedbits
+ self.fixedmask = fixedmask
+ self.undefmask = undefmask
+
+ def build_tree(self):
+ for p in self.pats:
+ p.build_tree()
+
+ def prop_format(self):
+ for p in self.pats:
+ p.build_tree()
+
+ def prop_width(self):
+ width = None
+ for p in self.pats:
+ p.prop_width()
+ if width is None:
+ width = p.width
+ elif width != p.width:
+ error_with_file(self.file, self.lineno,
+ 'width mismatch in patterns within braces')
+ self.width = width
+
+# end MultiPattern
+
+
+class IncMultiPattern(MultiPattern):
+ """Class representing an overlapping set of instruction patterns"""
+
def output_code(self, i, extracted, outerbits, outermask):
global translate_prefix
ind = str_indent(i)
output(ind, '}\n')
else:
p.output_code(i, extracted, p.fixedbits, p.fixedmask)
-#end MultiPattern
+#end IncMultiPattern
+
+
+class Tree:
+ """Class representing a node in a decode tree"""
+
+ def __init__(self, fm, tm):
+ self.fixedmask = fm
+ self.thismask = tm
+ self.subs = []
+ self.base = None
+
+ def str1(self, i):
+ ind = str_indent(i)
+ r = '{0}{1:08x}'.format(ind, self.fixedmask)
+ if self.format:
+ r += ' ' + self.format.name
+ r += ' [\n'
+ for (b, s) in self.subs:
+ r += '{0} {1:08x}:\n'.format(ind, b)
+ r += s.str1(i + 4) + '\n'
+ r += ind + ']'
+ return r
+
+ def __str__(self):
+ return self.str1(0)
+
+ def output_code(self, i, extracted, outerbits, outermask):
+ ind = str_indent(i)
+
+ # If we identified all nodes below have the same format,
+ # extract the fields now.
+ if not extracted and self.base:
+ output(ind, self.base.extract_name(),
+ '(ctx, &u.f_', self.base.base.name, ', insn);\n')
+ extracted = True
+
+ # Attempt to aid the compiler in producing compact switch statements.
+ # If the bits in the mask are contiguous, extract them.
+ sh = is_contiguous(self.thismask)
+ if sh > 0:
+ # Propagate SH down into the local functions.
+ def str_switch(b, sh=sh):
+ return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
+
+ def str_case(b, sh=sh):
+ return '0x{0:x}'.format(b >> sh)
+ else:
+ def str_switch(b):
+ return 'insn & 0x{0:08x}'.format(b)
+
+ def str_case(b):
+ return '0x{0:08x}'.format(b)
+
+ output(ind, 'switch (', str_switch(self.thismask), ') {\n')
+ for b, s in sorted(self.subs):
+ assert (self.thismask & ~s.fixedmask) == 0
+ innermask = outermask | self.thismask
+ innerbits = outerbits | b
+ output(ind, 'case ', str_case(b), ':\n')
+ output(ind, ' /* ',
+ str_match_bits(innerbits, innermask), ' */\n')
+ s.output_code(i + 4, extracted, innerbits, innermask)
+ output(ind, ' return false;\n')
+ output(ind, '}\n')
+# end Tree
+
+
+class ExcMultiPattern(MultiPattern):
+ """Class representing a non-overlapping set of instruction patterns"""
+
+ def output_code(self, i, extracted, outerbits, outermask):
+ # Defer everything to our decomposed Tree node
+ self.tree.output_code(i, extracted, outerbits, outermask)
+
+ @staticmethod
+ def __build_tree(pats, outerbits, outermask):
+ # Find the intersection of all remaining fixedmask.
+ innermask = ~outermask & insnmask
+ for i in pats:
+ innermask &= i.fixedmask
+
+ if innermask == 0:
+ # Edge condition: One pattern covers the entire insnmask
+ if len(pats) == 1:
+ t = Tree(outermask, innermask)
+ t.subs.append((0, pats[0]))
+ return t
+
+ text = 'overlapping patterns:'
+ for p in pats:
+ text += '\n' + p.file + ':' + str(p.lineno) + ': ' + str(p)
+ error_with_file(pats[0].file, pats[0].lineno, text)
+
+ fullmask = outermask | innermask
+
+ # Sort each element of pats into the bin selected by the mask.
+ bins = {}
+ for i in pats:
+ fb = i.fixedbits & innermask
+ if fb in bins:
+ bins[fb].append(i)
+ else:
+ bins[fb] = [i]
+
+ # We must recurse if any bin has more than one element or if
+ # the single element in the bin has not been fully matched.
+ t = Tree(fullmask, innermask)
+
+ for b, l in bins.items():
+ s = l[0]
+ if len(l) > 1 or s.fixedmask & ~fullmask != 0:
+ s = ExcMultiPattern.__build_tree(l, b | outerbits, fullmask)
+ t.subs.append((b, s))
+
+ return t
+
+ def build_tree(self):
+ super().prop_format()
+ self.tree = self.__build_tree(self.pats, self.fixedbits,
+ self.fixedmask)
+
+ @staticmethod
+ def __prop_format(tree):
+ """Propagate Format objects into the decode tree"""
+
+ # Depth first search.
+ for (b, s) in tree.subs:
+ if isinstance(s, Tree):
+ ExcMultiPattern.__prop_format(s)
+
+ # If all entries in SUBS have the same format, then
+ # propagate that into the tree.
+ f = None
+ for (b, s) in tree.subs:
+ if f is None:
+ f = s.base
+ if f is None:
+ return
+ if f is not s.base:
+ return
+ tree.base = f
+
+ def prop_format(self):
+ super().prop_format()
+ self.__prop_format(self.tree)
+
+# end ExcMultiPattern
def parse_field(lineno, name, toks):
# end infer_format
-def parse_generic(lineno, is_format, name, toks):
+def parse_generic(lineno, parent_pat, name, toks):
"""Parse one instruction format from TOKS at LINENO"""
global fields
global arguments
global formats
- global patterns
global allpatterns
global re_ident
global insnwidth
global insnmask
global variablewidth
+ is_format = parent_pat is None
+
fixedmask = 0
fixedbits = 0
undefmask = 0
error(lineno, 'field {0} not initialized'.format(f))
pat = Pattern(name, lineno, fmt, fixedbits, fixedmask,
undefmask, fieldmask, flds, width)
- patterns.append(pat)
+ parent_pat.pats.append(pat)
allpatterns.append(pat)
# Validate the masks that we have assembled.
.format(allbits ^ insnmask))
# end parse_general
-def build_multi_pattern(lineno, pats):
- """Validate the Patterns going into a MultiPattern."""
- global patterns
- global insnmask
-
- if len(pats) < 2:
- error(lineno, 'less than two patterns within braces')
-
- fixedmask = insnmask
- undefmask = insnmask
-
- # Collect fixed/undefmask for all of the children.
- # Move the defining lineno back to that of the first child.
- for p in pats:
- fixedmask &= p.fixedmask
- undefmask &= p.undefmask
- if p.lineno < lineno:
- lineno = p.lineno
-
- width = None
- for p in pats:
- if width is None:
- width = p.width
- elif width != p.width:
- error(lineno, 'width mismatch in patterns within braces')
-
- repeat = True
- while repeat:
- if fixedmask == 0:
- error(lineno, 'no overlap in patterns within braces')
- fixedbits = None
- for p in pats:
- thisbits = p.fixedbits & fixedmask
- if fixedbits is None:
- fixedbits = thisbits
- elif fixedbits != thisbits:
- fixedmask &= ~(fixedbits ^ thisbits)
- break
- else:
- repeat = False
- mp = MultiPattern(lineno, pats, fixedbits, fixedmask, undefmask, width)
- patterns.append(mp)
-# end build_multi_pattern
-
-def parse_file(f):
+def parse_file(f, parent_pat):
"""Parse all of the patterns within a file"""
- global patterns
-
# Read all of the lines of the file. Concatenate lines
# ending in backslash; discard empty lines and comments.
toks = []
lineno = 0
nesting = 0
- saved_pats = []
+ nesting_pats = []
for line in f:
lineno += 1
del toks[0]
# End nesting?
- if name == '}':
- if nesting == 0:
- error(start_lineno, 'mismatched close brace')
+ if name == '}' or name == ']':
if len(toks) != 0:
error(start_lineno, 'extra tokens after close brace')
+
+ # Make sure { } and [ ] nest properly.
+ if (name == '}') != isinstance(parent_pat, IncMultiPattern):
+ error(lineno, 'mismatched close brace')
+
+ try:
+ parent_pat = nesting_pats.pop()
+ except:
+ error(lineno, 'extra close brace')
+
nesting -= 2
if indent != nesting:
- error(start_lineno, 'indentation ', indent, ' != ', nesting)
- pats = patterns
- patterns = saved_pats.pop()
- build_multi_pattern(lineno, pats)
+ error(lineno, 'indentation ', indent, ' != ', nesting)
+
toks = []
continue
error(start_lineno, 'indentation ', indent, ' != ', nesting)
# Start nesting?
- if name == '{':
+ if name == '{' or name == '[':
if len(toks) != 0:
error(start_lineno, 'extra tokens after open brace')
- saved_pats.append(patterns)
- patterns = []
+
+ if name == '{':
+ nested_pat = IncMultiPattern(start_lineno)
+ else:
+ nested_pat = ExcMultiPattern(start_lineno)
+ parent_pat.pats.append(nested_pat)
+ nesting_pats.append(parent_pat)
+ parent_pat = nested_pat
+
nesting += 2
toks = []
continue
elif name[0] == '&':
parse_arguments(start_lineno, name[1:], toks)
elif name[0] == '@':
- parse_generic(start_lineno, True, name[1:], toks)
+ parse_generic(start_lineno, None, name[1:], toks)
else:
- parse_generic(start_lineno, False, name, toks)
+ parse_generic(start_lineno, parent_pat, name, toks)
toks = []
-# end parse_file
-
-
-class Tree:
- """Class representing a node in a decode tree"""
-
- def __init__(self, fm, tm):
- self.fixedmask = fm
- self.thismask = tm
- self.subs = []
- self.base = None
- def str1(self, i):
- ind = str_indent(i)
- r = '{0}{1:08x}'.format(ind, self.fixedmask)
- if self.format:
- r += ' ' + self.format.name
- r += ' [\n'
- for (b, s) in self.subs:
- r += '{0} {1:08x}:\n'.format(ind, b)
- r += s.str1(i + 4) + '\n'
- r += ind + ']'
- return r
-
- def __str__(self):
- return self.str1(0)
-
- def output_code(self, i, extracted, outerbits, outermask):
- ind = str_indent(i)
-
- # If we identified all nodes below have the same format,
- # extract the fields now.
- if not extracted and self.base:
- output(ind, self.base.extract_name(),
- '(ctx, &u.f_', self.base.base.name, ', insn);\n')
- extracted = True
-
- # Attempt to aid the compiler in producing compact switch statements.
- # If the bits in the mask are contiguous, extract them.
- sh = is_contiguous(self.thismask)
- if sh > 0:
- # Propagate SH down into the local functions.
- def str_switch(b, sh=sh):
- return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
-
- def str_case(b, sh=sh):
- return '0x{0:x}'.format(b >> sh)
- else:
- def str_switch(b):
- return 'insn & 0x{0:08x}'.format(b)
-
- def str_case(b):
- return '0x{0:08x}'.format(b)
-
- output(ind, 'switch (', str_switch(self.thismask), ') {\n')
- for b, s in sorted(self.subs):
- assert (self.thismask & ~s.fixedmask) == 0
- innermask = outermask | self.thismask
- innerbits = outerbits | b
- output(ind, 'case ', str_case(b), ':\n')
- output(ind, ' /* ',
- str_match_bits(innerbits, innermask), ' */\n')
- s.output_code(i + 4, extracted, innerbits, innermask)
- output(ind, ' return false;\n')
- output(ind, '}\n')
-# end Tree
-
-
-def build_tree(pats, outerbits, outermask):
- # Find the intersection of all remaining fixedmask.
- innermask = ~outermask & insnmask
- for i in pats:
- innermask &= i.fixedmask
-
- if innermask == 0:
- text = 'overlapping patterns:'
- for p in pats:
- text += '\n' + p.file + ':' + str(p.lineno) + ': ' + str(p)
- error_with_file(pats[0].file, pats[0].lineno, text)
-
- fullmask = outermask | innermask
-
- # Sort each element of pats into the bin selected by the mask.
- bins = {}
- for i in pats:
- fb = i.fixedbits & innermask
- if fb in bins:
- bins[fb].append(i)
- else:
- bins[fb] = [i]
-
- # We must recurse if any bin has more than one element or if
- # the single element in the bin has not been fully matched.
- t = Tree(fullmask, innermask)
-
- for b, l in bins.items():
- s = l[0]
- if len(l) > 1 or s.fixedmask & ~fullmask != 0:
- s = build_tree(l, b | outerbits, fullmask)
- t.subs.append((b, s))
-
- return t
-# end build_tree
+ if nesting != 0:
+ error(lineno, 'missing close brace')
+# end parse_file
class SizeTree:
# end build_size_tree
-def prop_format(tree):
- """Propagate Format objects into the decode tree"""
-
- # Depth first search.
- for (b, s) in tree.subs:
- if isinstance(s, Tree):
- prop_format(s)
-
- # If all entries in SUBS have the same format, then
- # propagate that into the tree.
- f = None
- for (b, s) in tree.subs:
- if f is None:
- f = s.base
- if f is None:
- return
- if f is not s.base:
- return
- tree.base = f
-# end prop_format
-
-
def prop_size(tree):
"""Propagate minimum widths up the decode size tree"""
def main():
global arguments
global formats
- global patterns
global allpatterns
global translate_scope
global translate_prefix
if len(args) < 1:
error(0, 'missing input file')
+
+ toppat = ExcMultiPattern(0)
+
for filename in args:
input_file = filename
f = open(filename, 'r')
- parse_file(f)
+ parse_file(f, toppat)
f.close()
+ # We do not want to compute masks for toppat, because those masks
+ # are used as a starting point for build_tree. For toppat, we must
+ # insist that decode begins from naught.
+ for i in toppat.pats:
+ i.prop_masks()
+
+ toppat.build_tree()
+ toppat.prop_format()
+
if variablewidth:
- stree = build_size_tree(patterns, 8, 0, 0)
+ for i in toppat.pats:
+ i.prop_width()
+ stree = build_size_tree(toppat.pats, 8, 0, 0)
prop_size(stree)
- dtree = build_tree(patterns, 0, 0)
- prop_format(dtree)
-
if output_file:
output_fd = open(output_file, 'w')
else:
f = arguments[n]
output(i4, i4, f.struct_name(), ' f_', f.name, ';\n')
output(i4, '} u;\n\n')
- dtree.output_code(4, False, 0, 0)
+ toppat.output_code(4, False, 0, 0)
output(i4, 'return false;\n')
output('}\n')
&cps
# Miscellaneous control
- {
+ [
CLREX 1111 0011 1011 1111 1000 1111 0010 1111
DSB 1111 0011 1011 1111 1000 1111 0100 ----
DMB 1111 0011 1011 1111 1000 1111 0101 ----
ISB 1111 0011 1011 1111 1000 1111 0110 ----
SB 1111 0011 1011 1111 1000 1111 0111 0000
- }
+ ]
# Note that the v7m insn overlaps both the normal and banked insn.
{
if (smram) {
cpu->smram = g_new(MemoryRegion, 1);
memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
- smram, 0, 1ull << 32);
+ smram, 0, 4 * GiB);
memory_region_set_enabled(cpu->smram, true);
memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
}
obj-y += translate.o cpu.o gdbstub.o helper.o
obj-y += op_helper.o cp0_helper.o fpu_helper.o
-obj-y += dsp_helper.o lmi_helper.o msa_helper.o
+obj-y += dsp_helper.o lmmi_helper.o msa_helper.o
obj-$(CONFIG_SOFTMMU) += mips-semi.o
obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o
obj-$(CONFIG_KVM) += kvm.o
* 3 Config3 WatchLo3 WatchHi
* 4 Config4 WatchLo4 WatchHi
* 5 Config5 WatchLo5 WatchHi
- * 6 WatchLo6 WatchHi
- * 7 WatchLo7 WatchHi
+ * 6 Config6 WatchLo6 WatchHi
+ * 7 Config7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
#define CP0C5_UFR 2
#define CP0C5_NFExists 0
int32_t CP0_Config6;
+ int32_t CP0_Config6_rw_bitmask;
+#define CP0C6_BPPASS 31
+#define CP0C6_KPOS 24
+#define CP0C6_KE 23
+#define CP0C6_VTLBONLY 22
+#define CP0C6_LASX 21
+#define CP0C6_SSEN 20
+#define CP0C6_DISDRTIME 19
+#define CP0C6_PIXNUEN 18
+#define CP0C6_SCRAND 17
+#define CP0C6_LLEXCEN 16
+#define CP0C6_DISVC 15
+#define CP0C6_VCLRU 14
+#define CP0C6_DCLRU 13
+#define CP0C6_PIXUEN 12
+#define CP0C6_DISBLKLYEN 11
+#define CP0C6_UMEMUALEN 10
+#define CP0C6_SFBEN 8
+#define CP0C6_FLTINT 7
+#define CP0C6_VLTINT 6
+#define CP0C6_DISBTB 5
+#define CP0C6_STPREFCTL 2
+#define CP0C6_INSTPREF 1
+#define CP0C6_DATAPREF 0
int32_t CP0_Config7;
+ int64_t CP0_Config7_rw_bitmask;
+#define CP0C7_NAPCGEN 2
+#define CP0C7_UNIMUEN 1
+#define CP0C7_VFPUCGEN 0
uint64_t CP0_LLAddr;
uint64_t CP0_MAAR[MIPS_MAAR_MAX];
int32_t CP0_MAARI;
}
}
-int ieee_ex_to_mips(int xcpt)
+static inline int ieee_to_mips_xcpt(int ieee_xcpt)
{
- int ret = 0;
- if (xcpt) {
- if (xcpt & float_flag_invalid) {
- ret |= FP_INVALID;
- }
- if (xcpt & float_flag_overflow) {
- ret |= FP_OVERFLOW;
- }
- if (xcpt & float_flag_underflow) {
- ret |= FP_UNDERFLOW;
- }
- if (xcpt & float_flag_divbyzero) {
- ret |= FP_DIV0;
- }
- if (xcpt & float_flag_inexact) {
- ret |= FP_INEXACT;
- }
+ int mips_xcpt = 0;
+
+ if (ieee_xcpt & float_flag_invalid) {
+ mips_xcpt |= FP_INVALID;
+ }
+ if (ieee_xcpt & float_flag_overflow) {
+ mips_xcpt |= FP_OVERFLOW;
+ }
+ if (ieee_xcpt & float_flag_underflow) {
+ mips_xcpt |= FP_UNDERFLOW;
}
- return ret;
+ if (ieee_xcpt & float_flag_divbyzero) {
+ mips_xcpt |= FP_DIV0;
+ }
+ if (ieee_xcpt & float_flag_inexact) {
+ mips_xcpt |= FP_INEXACT;
+ }
+
+ return mips_xcpt;
}
static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
{
- int tmp = ieee_ex_to_mips(get_float_exception_flags(
- &env->active_fpu.fp_status));
+ int ieee_exception_flags = get_float_exception_flags(
+ &env->active_fpu.fp_status);
+ int mips_exception_flags = 0;
- SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
+ if (ieee_exception_flags) {
+ mips_exception_flags = ieee_to_mips_xcpt(ieee_exception_flags);
+ }
- if (tmp) {
+ SET_FP_CAUSE(env->active_fpu.fcr31, mips_exception_flags);
+
+ if (mips_exception_flags) {
set_float_exception_flags(0, &env->active_fpu.fp_status);
- if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
+ if (GET_FP_ENABLE(env->active_fpu.fcr31) & mips_exception_flags) {
do_raise_exception(env, EXCP_FPE, pc);
} else {
- UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
+ UPDATE_FP_FLAGS(env->active_fpu.fcr31, mips_exception_flags);
}
}
}
uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
{
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
- &env->active_fpu.fp_status);
+ fstl2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
+ &env->active_fpu.fp_status);
fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
{
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
+ fstl2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
- fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
+ fstl2 = float32_div(float32_one, fstl2, &env->active_fpu.fp_status);
fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
-#define FLOAT_RINT(name, bits) \
-uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
- uint ## bits ## _t fs) \
-{ \
- uint ## bits ## _t fdret; \
- \
- fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
- update_fcr31(env, GETPC()); \
- return fdret; \
+uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs)
+{
+ uint64_t fdret;
+
+ fdret = float64_round_to_int(fs, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return fdret;
}
-FLOAT_RINT(rint_s, 32)
-FLOAT_RINT(rint_d, 64)
-#undef FLOAT_RINT
+uint32_t helper_float_rint_s(CPUMIPSState *env, uint32_t fs)
+{
+ uint32_t fdret;
+
+ fdret = float32_round_to_int(fs, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return fdret;
+}
#define FLOAT_CLASS_SIGNALING_NAN 0x001
#define FLOAT_CLASS_QUIET_NAN 0x002
#define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
#define FLOAT_CLASS_POSITIVE_ZERO 0x200
-#define FLOAT_CLASS(name, bits) \
-uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \
- float_status *status) \
-{ \
- if (float ## bits ## _is_signaling_nan(arg, status)) { \
- return FLOAT_CLASS_SIGNALING_NAN; \
- } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
- return FLOAT_CLASS_QUIET_NAN; \
- } else if (float ## bits ## _is_neg(arg)) { \
- if (float ## bits ## _is_infinity(arg)) { \
- return FLOAT_CLASS_NEGATIVE_INFINITY; \
- } else if (float ## bits ## _is_zero(arg)) { \
- return FLOAT_CLASS_NEGATIVE_ZERO; \
- } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
- return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
- } else { \
- return FLOAT_CLASS_NEGATIVE_NORMAL; \
- } \
- } else { \
- if (float ## bits ## _is_infinity(arg)) { \
- return FLOAT_CLASS_POSITIVE_INFINITY; \
- } else if (float ## bits ## _is_zero(arg)) { \
- return FLOAT_CLASS_POSITIVE_ZERO; \
- } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
- return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
- } else { \
- return FLOAT_CLASS_POSITIVE_NORMAL; \
- } \
- } \
-} \
- \
-uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
- uint ## bits ## _t arg) \
-{ \
- return float_ ## name(arg, &env->active_fpu.fp_status); \
-}
-
-FLOAT_CLASS(class_s, 32)
-FLOAT_CLASS(class_d, 64)
-#undef FLOAT_CLASS
+uint64_t float_class_d(uint64_t arg, float_status *status)
+{
+ if (float64_is_signaling_nan(arg, status)) {
+ return FLOAT_CLASS_SIGNALING_NAN;
+ } else if (float64_is_quiet_nan(arg, status)) {
+ return FLOAT_CLASS_QUIET_NAN;
+ } else if (float64_is_neg(arg)) {
+ if (float64_is_infinity(arg)) {
+ return FLOAT_CLASS_NEGATIVE_INFINITY;
+ } else if (float64_is_zero(arg)) {
+ return FLOAT_CLASS_NEGATIVE_ZERO;
+ } else if (float64_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_NEGATIVE_NORMAL;
+ }
+ } else {
+ if (float64_is_infinity(arg)) {
+ return FLOAT_CLASS_POSITIVE_INFINITY;
+ } else if (float64_is_zero(arg)) {
+ return FLOAT_CLASS_POSITIVE_ZERO;
+ } else if (float64_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_POSITIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_POSITIVE_NORMAL;
+ }
+ }
+}
+
+uint64_t helper_float_class_d(CPUMIPSState *env, uint64_t arg)
+{
+ return float_class_d(arg, &env->active_fpu.fp_status);
+}
+
+uint32_t float_class_s(uint32_t arg, float_status *status)
+{
+ if (float32_is_signaling_nan(arg, status)) {
+ return FLOAT_CLASS_SIGNALING_NAN;
+ } else if (float32_is_quiet_nan(arg, status)) {
+ return FLOAT_CLASS_QUIET_NAN;
+ } else if (float32_is_neg(arg)) {
+ if (float32_is_infinity(arg)) {
+ return FLOAT_CLASS_NEGATIVE_INFINITY;
+ } else if (float32_is_zero(arg)) {
+ return FLOAT_CLASS_NEGATIVE_ZERO;
+ } else if (float32_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_NEGATIVE_NORMAL;
+ }
+ } else {
+ if (float32_is_infinity(arg)) {
+ return FLOAT_CLASS_POSITIVE_INFINITY;
+ } else if (float32_is_zero(arg)) {
+ return FLOAT_CLASS_POSITIVE_ZERO;
+ } else if (float32_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_POSITIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_POSITIVE_NORMAL;
+ }
+ }
+}
+
+uint32_t helper_float_class_s(CPUMIPSState *env, uint32_t arg)
+{
+ return float_class_s(arg, &env->active_fpu.fp_status);
+}
/* binary operations */
-#define FLOAT_BINOP(name) \
-uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
- uint64_t fdt0, uint64_t fdt1) \
-{ \
- uint64_t dt2; \
- \
- dt2 = float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\
- update_fcr31(env, GETPC()); \
- return dt2; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
- uint32_t fst0, uint32_t fst1) \
-{ \
- uint32_t wt2; \
- \
- wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\
- update_fcr31(env, GETPC()); \
- return wt2; \
-} \
- \
-uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
- uint64_t fdt0, \
- uint64_t fdt1) \
-{ \
- uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
- uint32_t fsth0 = fdt0 >> 32; \
- uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
- uint32_t fsth1 = fdt1 >> 32; \
- uint32_t wt2; \
- uint32_t wth2; \
- \
- wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \
- wth2 = float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \
- update_fcr31(env, GETPC()); \
- return ((uint64_t)wth2 << 32) | wt2; \
-}
-
-FLOAT_BINOP(add)
-FLOAT_BINOP(sub)
-FLOAT_BINOP(mul)
-FLOAT_BINOP(div)
-#undef FLOAT_BINOP
+
+uint64_t helper_float_add_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_add(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_add_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_add_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_add(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_add(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
+uint64_t helper_float_sub_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_sub(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_sub_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_sub_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_sub(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_sub(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
+uint64_t helper_float_mul_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_mul(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_mul_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_mul_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
+uint64_t helper_float_div_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_div(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_div_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_div(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_div_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_div(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_div(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
/* MIPS specific binary operations */
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
uint32_t fsth2 = fdt2 >> 32;
- fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+ fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status);
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_sub(fst2, float32_one,
+ fstl2 = float32_chs(float32_sub(fstl2, float32_one,
&env->active_fpu.fp_status));
fsth2 = float32_chs(float32_sub(fsth2, float32_one,
&env->active_fpu.fp_status));
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
uint32_t fsth2 = fdt2 >> 32;
- fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+ fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status);
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
- fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
+ fstl2 = float32_sub(fstl2, float32_one, &env->active_fpu.fp_status);
fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
+ fstl2 = float32_chs(float32_div(fstl2, FLOAT_TWO32,
&env->active_fpu.fp_status));
fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32,
&env->active_fpu.fp_status));
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
uint32_t fsth1 = fdt1 >> 32;
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status);
+ fstl2 = float32_add(fstl0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_add(fstl1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
uint32_t fsth1 = fdt1 >> 32;
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status);
+ fstl2 = float32_mul(fstl0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_mul(fstl1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
#define FLOAT_MINMAX(name, bits, minmaxfunc) \
#undef FLOAT_MINMAX
/* ternary operations */
-#define UNFUSED_FMA(prefix, a, b, c, flags) \
-{ \
- a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
- if ((flags) & float_muladd_negate_c) { \
- a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
- } else { \
- a = prefix##_add(a, c, &env->active_fpu.fp_status); \
- } \
- if ((flags) & float_muladd_negate_result) { \
- a = prefix##_chs(a); \
- } \
-}
-
-/* FMA based operations */
-#define FLOAT_FMA(name, type) \
-uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
- uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2) \
-{ \
- UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
- update_fcr31(env, GETPC()); \
- return fdt0; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
- uint32_t fst0, uint32_t fst1, \
- uint32_t fst2) \
-{ \
- UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
- update_fcr31(env, GETPC()); \
- return fst0; \
-} \
- \
-uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
- uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2) \
-{ \
- uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
- uint32_t fsth0 = fdt0 >> 32; \
- uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
- uint32_t fsth1 = fdt1 >> 32; \
- uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
- uint32_t fsth2 = fdt2 >> 32; \
- \
- UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
- UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
- update_fcr31(env, GETPC()); \
- return ((uint64_t)fsth0 << 32) | fst0; \
-}
-FLOAT_FMA(madd, 0)
-FLOAT_FMA(msub, float_muladd_negate_c)
-FLOAT_FMA(nmadd, float_muladd_negate_result)
-FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
-#undef FLOAT_FMA
+
+uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_madd_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
+uint64_t helper_float_msub_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_msub_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_msub_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
+uint64_t helper_float_nmadd_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float64_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_nmadd_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float32_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_nmadd_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
+ fstl0 = float32_chs(fstl0);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
+ fsth0 = float32_chs(fsth0);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
+uint64_t helper_float_nmsub_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float64_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_nmsub_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float32_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_nmsub_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
+ fstl0 = float32_chs(fstl0);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
+ fsth0 = float32_chs(fsth0);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
int32_t CP0_Config5;
int32_t CP0_Config5_rw_bitmask;
int32_t CP0_Config6;
+ int32_t CP0_Config6_rw_bitmask;
int32_t CP0_Config7;
+ int32_t CP0_Config7_rw_bitmask;
target_ulong CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
int32_t SYNCI_Step;
uint64_t float_class_d(uint64_t arg, float_status *fst);
extern unsigned int ieee_rm[];
-int ieee_ex_to_mips(int xcpt);
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
static inline void restore_rounding_mode(CPUMIPSState *env)
+++ /dev/null
-/*
- * Loongson Multimedia Instruction emulation helpers for QEMU.
- *
- * Copyright (c) 2011 Richard Henderson <rth@twiddle.net>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "cpu.h"
-#include "exec/helper-proto.h"
-
-/*
- * If the byte ordering doesn't matter, i.e. all columns are treated
- * identically, then this union can be used directly. If byte ordering
- * does matter, we generally ignore dumping to memory.
- */
-typedef union {
- uint8_t ub[8];
- int8_t sb[8];
- uint16_t uh[4];
- int16_t sh[4];
- uint32_t uw[2];
- int32_t sw[2];
- uint64_t d;
-} LMIValue;
-
-/* Some byte ordering issues can be mitigated by XORing in the following. */
-#ifdef HOST_WORDS_BIGENDIAN
-# define BYTE_ORDER_XOR(N) N
-#else
-# define BYTE_ORDER_XOR(N) 0
-#endif
-
-#define SATSB(x) (x < -0x80 ? -0x80 : x > 0x7f ? 0x7f : x)
-#define SATUB(x) (x > 0xff ? 0xff : x)
-
-#define SATSH(x) (x < -0x8000 ? -0x8000 : x > 0x7fff ? 0x7fff : x)
-#define SATUH(x) (x > 0xffff ? 0xffff : x)
-
-#define SATSW(x) \
- (x < -0x80000000ll ? -0x80000000ll : x > 0x7fffffff ? 0x7fffffff : x)
-#define SATUW(x) (x > 0xffffffffull ? 0xffffffffull : x)
-
-uint64_t helper_paddsb(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; ++i) {
- int r = vs.sb[i] + vt.sb[i];
- vs.sb[i] = SATSB(r);
- }
- return vs.d;
-}
-
-uint64_t helper_paddusb(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; ++i) {
- int r = vs.ub[i] + vt.ub[i];
- vs.ub[i] = SATUB(r);
- }
- return vs.d;
-}
-
-uint64_t helper_paddsh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; ++i) {
- int r = vs.sh[i] + vt.sh[i];
- vs.sh[i] = SATSH(r);
- }
- return vs.d;
-}
-
-uint64_t helper_paddush(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; ++i) {
- int r = vs.uh[i] + vt.uh[i];
- vs.uh[i] = SATUH(r);
- }
- return vs.d;
-}
-
-uint64_t helper_paddb(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; ++i) {
- vs.ub[i] += vt.ub[i];
- }
- return vs.d;
-}
-
-uint64_t helper_paddh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; ++i) {
- vs.uh[i] += vt.uh[i];
- }
- return vs.d;
-}
-
-uint64_t helper_paddw(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 2; ++i) {
- vs.uw[i] += vt.uw[i];
- }
- return vs.d;
-}
-
-uint64_t helper_psubsb(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; ++i) {
- int r = vs.sb[i] - vt.sb[i];
- vs.sb[i] = SATSB(r);
- }
- return vs.d;
-}
-
-uint64_t helper_psubusb(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; ++i) {
- int r = vs.ub[i] - vt.ub[i];
- vs.ub[i] = SATUB(r);
- }
- return vs.d;
-}
-
-uint64_t helper_psubsh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; ++i) {
- int r = vs.sh[i] - vt.sh[i];
- vs.sh[i] = SATSH(r);
- }
- return vs.d;
-}
-
-uint64_t helper_psubush(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; ++i) {
- int r = vs.uh[i] - vt.uh[i];
- vs.uh[i] = SATUH(r);
- }
- return vs.d;
-}
-
-uint64_t helper_psubb(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; ++i) {
- vs.ub[i] -= vt.ub[i];
- }
- return vs.d;
-}
-
-uint64_t helper_psubh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; ++i) {
- vs.uh[i] -= vt.uh[i];
- }
- return vs.d;
-}
-
-uint64_t helper_psubw(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned int i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 2; ++i) {
- vs.uw[i] -= vt.uw[i];
- }
- return vs.d;
-}
-
-uint64_t helper_pshufh(uint64_t fs, uint64_t ft)
-{
- unsigned host = BYTE_ORDER_XOR(3);
- LMIValue vd, vs;
- unsigned i;
-
- vs.d = fs;
- vd.d = 0;
- for (i = 0; i < 4; i++, ft >>= 2) {
- vd.uh[i ^ host] = vs.uh[(ft & 3) ^ host];
- }
- return vd.d;
-}
-
-uint64_t helper_packsswh(uint64_t fs, uint64_t ft)
-{
- uint64_t fd = 0;
- int64_t tmp;
-
- tmp = (int32_t)(fs >> 0);
- tmp = SATSH(tmp);
- fd |= (tmp & 0xffff) << 0;
-
- tmp = (int32_t)(fs >> 32);
- tmp = SATSH(tmp);
- fd |= (tmp & 0xffff) << 16;
-
- tmp = (int32_t)(ft >> 0);
- tmp = SATSH(tmp);
- fd |= (tmp & 0xffff) << 32;
-
- tmp = (int32_t)(ft >> 32);
- tmp = SATSH(tmp);
- fd |= (tmp & 0xffff) << 48;
-
- return fd;
-}
-
-uint64_t helper_packsshb(uint64_t fs, uint64_t ft)
-{
- uint64_t fd = 0;
- unsigned int i;
-
- for (i = 0; i < 4; ++i) {
- int16_t tmp = fs >> (i * 16);
- tmp = SATSB(tmp);
- fd |= (uint64_t)(tmp & 0xff) << (i * 8);
- }
- for (i = 0; i < 4; ++i) {
- int16_t tmp = ft >> (i * 16);
- tmp = SATSB(tmp);
- fd |= (uint64_t)(tmp & 0xff) << (i * 8 + 32);
- }
-
- return fd;
-}
-
-uint64_t helper_packushb(uint64_t fs, uint64_t ft)
-{
- uint64_t fd = 0;
- unsigned int i;
-
- for (i = 0; i < 4; ++i) {
- int16_t tmp = fs >> (i * 16);
- tmp = SATUB(tmp);
- fd |= (uint64_t)(tmp & 0xff) << (i * 8);
- }
- for (i = 0; i < 4; ++i) {
- int16_t tmp = ft >> (i * 16);
- tmp = SATUB(tmp);
- fd |= (uint64_t)(tmp & 0xff) << (i * 8 + 32);
- }
-
- return fd;
-}
-
-uint64_t helper_punpcklwd(uint64_t fs, uint64_t ft)
-{
- return (fs & 0xffffffff) | (ft << 32);
-}
-
-uint64_t helper_punpckhwd(uint64_t fs, uint64_t ft)
-{
- return (fs >> 32) | (ft & ~0xffffffffull);
-}
-
-uint64_t helper_punpcklhw(uint64_t fs, uint64_t ft)
-{
- unsigned host = BYTE_ORDER_XOR(3);
- LMIValue vd, vs, vt;
-
- vs.d = fs;
- vt.d = ft;
- vd.uh[0 ^ host] = vs.uh[0 ^ host];
- vd.uh[1 ^ host] = vt.uh[0 ^ host];
- vd.uh[2 ^ host] = vs.uh[1 ^ host];
- vd.uh[3 ^ host] = vt.uh[1 ^ host];
-
- return vd.d;
-}
-
-uint64_t helper_punpckhhw(uint64_t fs, uint64_t ft)
-{
- unsigned host = BYTE_ORDER_XOR(3);
- LMIValue vd, vs, vt;
-
- vs.d = fs;
- vt.d = ft;
- vd.uh[0 ^ host] = vs.uh[2 ^ host];
- vd.uh[1 ^ host] = vt.uh[2 ^ host];
- vd.uh[2 ^ host] = vs.uh[3 ^ host];
- vd.uh[3 ^ host] = vt.uh[3 ^ host];
-
- return vd.d;
-}
-
-uint64_t helper_punpcklbh(uint64_t fs, uint64_t ft)
-{
- unsigned host = BYTE_ORDER_XOR(7);
- LMIValue vd, vs, vt;
-
- vs.d = fs;
- vt.d = ft;
- vd.ub[0 ^ host] = vs.ub[0 ^ host];
- vd.ub[1 ^ host] = vt.ub[0 ^ host];
- vd.ub[2 ^ host] = vs.ub[1 ^ host];
- vd.ub[3 ^ host] = vt.ub[1 ^ host];
- vd.ub[4 ^ host] = vs.ub[2 ^ host];
- vd.ub[5 ^ host] = vt.ub[2 ^ host];
- vd.ub[6 ^ host] = vs.ub[3 ^ host];
- vd.ub[7 ^ host] = vt.ub[3 ^ host];
-
- return vd.d;
-}
-
-uint64_t helper_punpckhbh(uint64_t fs, uint64_t ft)
-{
- unsigned host = BYTE_ORDER_XOR(7);
- LMIValue vd, vs, vt;
-
- vs.d = fs;
- vt.d = ft;
- vd.ub[0 ^ host] = vs.ub[4 ^ host];
- vd.ub[1 ^ host] = vt.ub[4 ^ host];
- vd.ub[2 ^ host] = vs.ub[5 ^ host];
- vd.ub[3 ^ host] = vt.ub[5 ^ host];
- vd.ub[4 ^ host] = vs.ub[6 ^ host];
- vd.ub[5 ^ host] = vt.ub[6 ^ host];
- vd.ub[6 ^ host] = vs.ub[7 ^ host];
- vd.ub[7 ^ host] = vt.ub[7 ^ host];
-
- return vd.d;
-}
-
-uint64_t helper_pavgh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; i++) {
- vs.uh[i] = (vs.uh[i] + vt.uh[i] + 1) >> 1;
- }
- return vs.d;
-}
-
-uint64_t helper_pavgb(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; i++) {
- vs.ub[i] = (vs.ub[i] + vt.ub[i] + 1) >> 1;
- }
- return vs.d;
-}
-
-uint64_t helper_pmaxsh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; i++) {
- vs.sh[i] = (vs.sh[i] >= vt.sh[i] ? vs.sh[i] : vt.sh[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_pminsh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; i++) {
- vs.sh[i] = (vs.sh[i] <= vt.sh[i] ? vs.sh[i] : vt.sh[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_pmaxub(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; i++) {
- vs.ub[i] = (vs.ub[i] >= vt.ub[i] ? vs.ub[i] : vt.ub[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_pminub(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; i++) {
- vs.ub[i] = (vs.ub[i] <= vt.ub[i] ? vs.ub[i] : vt.ub[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_pcmpeqw(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 2; i++) {
- vs.uw[i] = -(vs.uw[i] == vt.uw[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_pcmpgtw(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 2; i++) {
- vs.uw[i] = -(vs.uw[i] > vt.uw[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_pcmpeqh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; i++) {
- vs.uh[i] = -(vs.uh[i] == vt.uh[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_pcmpgth(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; i++) {
- vs.uh[i] = -(vs.uh[i] > vt.uh[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_pcmpeqb(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; i++) {
- vs.ub[i] = -(vs.ub[i] == vt.ub[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_pcmpgtb(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; i++) {
- vs.ub[i] = -(vs.ub[i] > vt.ub[i]);
- }
- return vs.d;
-}
-
-uint64_t helper_psllw(uint64_t fs, uint64_t ft)
-{
- LMIValue vs;
- unsigned i;
-
- ft &= 0x7f;
- if (ft > 31) {
- return 0;
- }
- vs.d = fs;
- for (i = 0; i < 2; ++i) {
- vs.uw[i] <<= ft;
- }
- return vs.d;
-}
-
-uint64_t helper_psrlw(uint64_t fs, uint64_t ft)
-{
- LMIValue vs;
- unsigned i;
-
- ft &= 0x7f;
- if (ft > 31) {
- return 0;
- }
- vs.d = fs;
- for (i = 0; i < 2; ++i) {
- vs.uw[i] >>= ft;
- }
- return vs.d;
-}
-
-uint64_t helper_psraw(uint64_t fs, uint64_t ft)
-{
- LMIValue vs;
- unsigned i;
-
- ft &= 0x7f;
- if (ft > 31) {
- ft = 31;
- }
- vs.d = fs;
- for (i = 0; i < 2; ++i) {
- vs.sw[i] >>= ft;
- }
- return vs.d;
-}
-
-uint64_t helper_psllh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs;
- unsigned i;
-
- ft &= 0x7f;
- if (ft > 15) {
- return 0;
- }
- vs.d = fs;
- for (i = 0; i < 4; ++i) {
- vs.uh[i] <<= ft;
- }
- return vs.d;
-}
-
-uint64_t helper_psrlh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs;
- unsigned i;
-
- ft &= 0x7f;
- if (ft > 15) {
- return 0;
- }
- vs.d = fs;
- for (i = 0; i < 4; ++i) {
- vs.uh[i] >>= ft;
- }
- return vs.d;
-}
-
-uint64_t helper_psrah(uint64_t fs, uint64_t ft)
-{
- LMIValue vs;
- unsigned i;
-
- ft &= 0x7f;
- if (ft > 15) {
- ft = 15;
- }
- vs.d = fs;
- for (i = 0; i < 4; ++i) {
- vs.sh[i] >>= ft;
- }
- return vs.d;
-}
-
-uint64_t helper_pmullh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; ++i) {
- vs.sh[i] *= vt.sh[i];
- }
- return vs.d;
-}
-
-uint64_t helper_pmulhh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; ++i) {
- int32_t r = vs.sh[i] * vt.sh[i];
- vs.sh[i] = r >> 16;
- }
- return vs.d;
-}
-
-uint64_t helper_pmulhuh(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 4; ++i) {
- uint32_t r = vs.uh[i] * vt.uh[i];
- vs.uh[i] = r >> 16;
- }
- return vs.d;
-}
-
-uint64_t helper_pmaddhw(uint64_t fs, uint64_t ft)
-{
- unsigned host = BYTE_ORDER_XOR(3);
- LMIValue vs, vt;
- uint32_t p0, p1;
-
- vs.d = fs;
- vt.d = ft;
- p0 = vs.sh[0 ^ host] * vt.sh[0 ^ host];
- p0 += vs.sh[1 ^ host] * vt.sh[1 ^ host];
- p1 = vs.sh[2 ^ host] * vt.sh[2 ^ host];
- p1 += vs.sh[3 ^ host] * vt.sh[3 ^ host];
-
- return ((uint64_t)p1 << 32) | p0;
-}
-
-uint64_t helper_pasubub(uint64_t fs, uint64_t ft)
-{
- LMIValue vs, vt;
- unsigned i;
-
- vs.d = fs;
- vt.d = ft;
- for (i = 0; i < 8; ++i) {
- int r = vs.ub[i] - vt.ub[i];
- vs.ub[i] = (r < 0 ? -r : r);
- }
- return vs.d;
-}
-
-uint64_t helper_biadd(uint64_t fs)
-{
- unsigned i, fd;
-
- for (i = fd = 0; i < 8; ++i) {
- fd += (fs >> (i * 8)) & 0xff;
- }
- return fd & 0xffff;
-}
-
-uint64_t helper_pmovmskb(uint64_t fs)
-{
- unsigned fd = 0;
-
- fd |= ((fs >> 7) & 1) << 0;
- fd |= ((fs >> 15) & 1) << 1;
- fd |= ((fs >> 23) & 1) << 2;
- fd |= ((fs >> 31) & 1) << 3;
- fd |= ((fs >> 39) & 1) << 4;
- fd |= ((fs >> 47) & 1) << 5;
- fd |= ((fs >> 55) & 1) << 6;
- fd |= ((fs >> 63) & 1) << 7;
-
- return fd & 0xff;
-}
--- /dev/null
+/*
+ * Loongson Multimedia Instruction emulation helpers for QEMU.
+ *
+ * Copyright (c) 2011 Richard Henderson <rth@twiddle.net>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+
+/*
+ * If the byte ordering doesn't matter, i.e. all columns are treated
+ * identically, then this union can be used directly. If byte ordering
+ * does matter, we generally ignore dumping to memory.
+ */
+typedef union {
+ uint8_t ub[8];
+ int8_t sb[8];
+ uint16_t uh[4];
+ int16_t sh[4];
+ uint32_t uw[2];
+ int32_t sw[2];
+ uint64_t d;
+} LMIValue;
+
+/* Some byte ordering issues can be mitigated by XORing in the following. */
+#ifdef HOST_WORDS_BIGENDIAN
+# define BYTE_ORDER_XOR(N) N
+#else
+# define BYTE_ORDER_XOR(N) 0
+#endif
+
+#define SATSB(x) (x < -0x80 ? -0x80 : x > 0x7f ? 0x7f : x)
+#define SATUB(x) (x > 0xff ? 0xff : x)
+
+#define SATSH(x) (x < -0x8000 ? -0x8000 : x > 0x7fff ? 0x7fff : x)
+#define SATUH(x) (x > 0xffff ? 0xffff : x)
+
+#define SATSW(x) \
+ (x < -0x80000000ll ? -0x80000000ll : x > 0x7fffffff ? 0x7fffffff : x)
+#define SATUW(x) (x > 0xffffffffull ? 0xffffffffull : x)
+
+uint64_t helper_paddsb(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; ++i) {
+ int r = vs.sb[i] + vt.sb[i];
+ vs.sb[i] = SATSB(r);
+ }
+ return vs.d;
+}
+
+uint64_t helper_paddusb(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; ++i) {
+ int r = vs.ub[i] + vt.ub[i];
+ vs.ub[i] = SATUB(r);
+ }
+ return vs.d;
+}
+
+uint64_t helper_paddsh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; ++i) {
+ int r = vs.sh[i] + vt.sh[i];
+ vs.sh[i] = SATSH(r);
+ }
+ return vs.d;
+}
+
+uint64_t helper_paddush(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; ++i) {
+ int r = vs.uh[i] + vt.uh[i];
+ vs.uh[i] = SATUH(r);
+ }
+ return vs.d;
+}
+
+uint64_t helper_paddb(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; ++i) {
+ vs.ub[i] += vt.ub[i];
+ }
+ return vs.d;
+}
+
+uint64_t helper_paddh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; ++i) {
+ vs.uh[i] += vt.uh[i];
+ }
+ return vs.d;
+}
+
+uint64_t helper_paddw(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 2; ++i) {
+ vs.uw[i] += vt.uw[i];
+ }
+ return vs.d;
+}
+
+uint64_t helper_psubsb(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; ++i) {
+ int r = vs.sb[i] - vt.sb[i];
+ vs.sb[i] = SATSB(r);
+ }
+ return vs.d;
+}
+
+uint64_t helper_psubusb(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; ++i) {
+ int r = vs.ub[i] - vt.ub[i];
+ vs.ub[i] = SATUB(r);
+ }
+ return vs.d;
+}
+
+uint64_t helper_psubsh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; ++i) {
+ int r = vs.sh[i] - vt.sh[i];
+ vs.sh[i] = SATSH(r);
+ }
+ return vs.d;
+}
+
+uint64_t helper_psubush(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; ++i) {
+ int r = vs.uh[i] - vt.uh[i];
+ vs.uh[i] = SATUH(r);
+ }
+ return vs.d;
+}
+
+uint64_t helper_psubb(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; ++i) {
+ vs.ub[i] -= vt.ub[i];
+ }
+ return vs.d;
+}
+
+uint64_t helper_psubh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; ++i) {
+ vs.uh[i] -= vt.uh[i];
+ }
+ return vs.d;
+}
+
+uint64_t helper_psubw(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned int i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 2; ++i) {
+ vs.uw[i] -= vt.uw[i];
+ }
+ return vs.d;
+}
+
+uint64_t helper_pshufh(uint64_t fs, uint64_t ft)
+{
+ unsigned host = BYTE_ORDER_XOR(3);
+ LMIValue vd, vs;
+ unsigned i;
+
+ vs.d = fs;
+ vd.d = 0;
+ for (i = 0; i < 4; i++, ft >>= 2) {
+ vd.uh[i ^ host] = vs.uh[(ft & 3) ^ host];
+ }
+ return vd.d;
+}
+
+uint64_t helper_packsswh(uint64_t fs, uint64_t ft)
+{
+ uint64_t fd = 0;
+ int64_t tmp;
+
+ tmp = (int32_t)(fs >> 0);
+ tmp = SATSH(tmp);
+ fd |= (tmp & 0xffff) << 0;
+
+ tmp = (int32_t)(fs >> 32);
+ tmp = SATSH(tmp);
+ fd |= (tmp & 0xffff) << 16;
+
+ tmp = (int32_t)(ft >> 0);
+ tmp = SATSH(tmp);
+ fd |= (tmp & 0xffff) << 32;
+
+ tmp = (int32_t)(ft >> 32);
+ tmp = SATSH(tmp);
+ fd |= (tmp & 0xffff) << 48;
+
+ return fd;
+}
+
+uint64_t helper_packsshb(uint64_t fs, uint64_t ft)
+{
+ uint64_t fd = 0;
+ unsigned int i;
+
+ for (i = 0; i < 4; ++i) {
+ int16_t tmp = fs >> (i * 16);
+ tmp = SATSB(tmp);
+ fd |= (uint64_t)(tmp & 0xff) << (i * 8);
+ }
+ for (i = 0; i < 4; ++i) {
+ int16_t tmp = ft >> (i * 16);
+ tmp = SATSB(tmp);
+ fd |= (uint64_t)(tmp & 0xff) << (i * 8 + 32);
+ }
+
+ return fd;
+}
+
+uint64_t helper_packushb(uint64_t fs, uint64_t ft)
+{
+ uint64_t fd = 0;
+ unsigned int i;
+
+ for (i = 0; i < 4; ++i) {
+ int16_t tmp = fs >> (i * 16);
+ tmp = SATUB(tmp);
+ fd |= (uint64_t)(tmp & 0xff) << (i * 8);
+ }
+ for (i = 0; i < 4; ++i) {
+ int16_t tmp = ft >> (i * 16);
+ tmp = SATUB(tmp);
+ fd |= (uint64_t)(tmp & 0xff) << (i * 8 + 32);
+ }
+
+ return fd;
+}
+
+uint64_t helper_punpcklwd(uint64_t fs, uint64_t ft)
+{
+ return (fs & 0xffffffff) | (ft << 32);
+}
+
+uint64_t helper_punpckhwd(uint64_t fs, uint64_t ft)
+{
+ return (fs >> 32) | (ft & ~0xffffffffull);
+}
+
+uint64_t helper_punpcklhw(uint64_t fs, uint64_t ft)
+{
+ unsigned host = BYTE_ORDER_XOR(3);
+ LMIValue vd, vs, vt;
+
+ vs.d = fs;
+ vt.d = ft;
+ vd.uh[0 ^ host] = vs.uh[0 ^ host];
+ vd.uh[1 ^ host] = vt.uh[0 ^ host];
+ vd.uh[2 ^ host] = vs.uh[1 ^ host];
+ vd.uh[3 ^ host] = vt.uh[1 ^ host];
+
+ return vd.d;
+}
+
+uint64_t helper_punpckhhw(uint64_t fs, uint64_t ft)
+{
+ unsigned host = BYTE_ORDER_XOR(3);
+ LMIValue vd, vs, vt;
+
+ vs.d = fs;
+ vt.d = ft;
+ vd.uh[0 ^ host] = vs.uh[2 ^ host];
+ vd.uh[1 ^ host] = vt.uh[2 ^ host];
+ vd.uh[2 ^ host] = vs.uh[3 ^ host];
+ vd.uh[3 ^ host] = vt.uh[3 ^ host];
+
+ return vd.d;
+}
+
+uint64_t helper_punpcklbh(uint64_t fs, uint64_t ft)
+{
+ unsigned host = BYTE_ORDER_XOR(7);
+ LMIValue vd, vs, vt;
+
+ vs.d = fs;
+ vt.d = ft;
+ vd.ub[0 ^ host] = vs.ub[0 ^ host];
+ vd.ub[1 ^ host] = vt.ub[0 ^ host];
+ vd.ub[2 ^ host] = vs.ub[1 ^ host];
+ vd.ub[3 ^ host] = vt.ub[1 ^ host];
+ vd.ub[4 ^ host] = vs.ub[2 ^ host];
+ vd.ub[5 ^ host] = vt.ub[2 ^ host];
+ vd.ub[6 ^ host] = vs.ub[3 ^ host];
+ vd.ub[7 ^ host] = vt.ub[3 ^ host];
+
+ return vd.d;
+}
+
+uint64_t helper_punpckhbh(uint64_t fs, uint64_t ft)
+{
+ unsigned host = BYTE_ORDER_XOR(7);
+ LMIValue vd, vs, vt;
+
+ vs.d = fs;
+ vt.d = ft;
+ vd.ub[0 ^ host] = vs.ub[4 ^ host];
+ vd.ub[1 ^ host] = vt.ub[4 ^ host];
+ vd.ub[2 ^ host] = vs.ub[5 ^ host];
+ vd.ub[3 ^ host] = vt.ub[5 ^ host];
+ vd.ub[4 ^ host] = vs.ub[6 ^ host];
+ vd.ub[5 ^ host] = vt.ub[6 ^ host];
+ vd.ub[6 ^ host] = vs.ub[7 ^ host];
+ vd.ub[7 ^ host] = vt.ub[7 ^ host];
+
+ return vd.d;
+}
+
+uint64_t helper_pavgh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; i++) {
+ vs.uh[i] = (vs.uh[i] + vt.uh[i] + 1) >> 1;
+ }
+ return vs.d;
+}
+
+uint64_t helper_pavgb(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; i++) {
+ vs.ub[i] = (vs.ub[i] + vt.ub[i] + 1) >> 1;
+ }
+ return vs.d;
+}
+
+uint64_t helper_pmaxsh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; i++) {
+ vs.sh[i] = (vs.sh[i] >= vt.sh[i] ? vs.sh[i] : vt.sh[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_pminsh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; i++) {
+ vs.sh[i] = (vs.sh[i] <= vt.sh[i] ? vs.sh[i] : vt.sh[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_pmaxub(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; i++) {
+ vs.ub[i] = (vs.ub[i] >= vt.ub[i] ? vs.ub[i] : vt.ub[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_pminub(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; i++) {
+ vs.ub[i] = (vs.ub[i] <= vt.ub[i] ? vs.ub[i] : vt.ub[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_pcmpeqw(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 2; i++) {
+ vs.uw[i] = -(vs.uw[i] == vt.uw[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_pcmpgtw(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 2; i++) {
+ vs.uw[i] = -(vs.uw[i] > vt.uw[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_pcmpeqh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; i++) {
+ vs.uh[i] = -(vs.uh[i] == vt.uh[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_pcmpgth(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; i++) {
+ vs.uh[i] = -(vs.uh[i] > vt.uh[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_pcmpeqb(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; i++) {
+ vs.ub[i] = -(vs.ub[i] == vt.ub[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_pcmpgtb(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; i++) {
+ vs.ub[i] = -(vs.ub[i] > vt.ub[i]);
+ }
+ return vs.d;
+}
+
+uint64_t helper_psllw(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs;
+ unsigned i;
+
+ ft &= 0x7f;
+ if (ft > 31) {
+ return 0;
+ }
+ vs.d = fs;
+ for (i = 0; i < 2; ++i) {
+ vs.uw[i] <<= ft;
+ }
+ return vs.d;
+}
+
+uint64_t helper_psrlw(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs;
+ unsigned i;
+
+ ft &= 0x7f;
+ if (ft > 31) {
+ return 0;
+ }
+ vs.d = fs;
+ for (i = 0; i < 2; ++i) {
+ vs.uw[i] >>= ft;
+ }
+ return vs.d;
+}
+
+uint64_t helper_psraw(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs;
+ unsigned i;
+
+ ft &= 0x7f;
+ if (ft > 31) {
+ ft = 31;
+ }
+ vs.d = fs;
+ for (i = 0; i < 2; ++i) {
+ vs.sw[i] >>= ft;
+ }
+ return vs.d;
+}
+
+uint64_t helper_psllh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs;
+ unsigned i;
+
+ ft &= 0x7f;
+ if (ft > 15) {
+ return 0;
+ }
+ vs.d = fs;
+ for (i = 0; i < 4; ++i) {
+ vs.uh[i] <<= ft;
+ }
+ return vs.d;
+}
+
+uint64_t helper_psrlh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs;
+ unsigned i;
+
+ ft &= 0x7f;
+ if (ft > 15) {
+ return 0;
+ }
+ vs.d = fs;
+ for (i = 0; i < 4; ++i) {
+ vs.uh[i] >>= ft;
+ }
+ return vs.d;
+}
+
+uint64_t helper_psrah(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs;
+ unsigned i;
+
+ ft &= 0x7f;
+ if (ft > 15) {
+ ft = 15;
+ }
+ vs.d = fs;
+ for (i = 0; i < 4; ++i) {
+ vs.sh[i] >>= ft;
+ }
+ return vs.d;
+}
+
+uint64_t helper_pmullh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; ++i) {
+ vs.sh[i] *= vt.sh[i];
+ }
+ return vs.d;
+}
+
+uint64_t helper_pmulhh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; ++i) {
+ int32_t r = vs.sh[i] * vt.sh[i];
+ vs.sh[i] = r >> 16;
+ }
+ return vs.d;
+}
+
+uint64_t helper_pmulhuh(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 4; ++i) {
+ uint32_t r = vs.uh[i] * vt.uh[i];
+ vs.uh[i] = r >> 16;
+ }
+ return vs.d;
+}
+
+uint64_t helper_pmaddhw(uint64_t fs, uint64_t ft)
+{
+ unsigned host = BYTE_ORDER_XOR(3);
+ LMIValue vs, vt;
+ uint32_t p0, p1;
+
+ vs.d = fs;
+ vt.d = ft;
+ p0 = vs.sh[0 ^ host] * vt.sh[0 ^ host];
+ p0 += vs.sh[1 ^ host] * vt.sh[1 ^ host];
+ p1 = vs.sh[2 ^ host] * vt.sh[2 ^ host];
+ p1 += vs.sh[3 ^ host] * vt.sh[3 ^ host];
+
+ return ((uint64_t)p1 << 32) | p0;
+}
+
+uint64_t helper_pasubub(uint64_t fs, uint64_t ft)
+{
+ LMIValue vs, vt;
+ unsigned i;
+
+ vs.d = fs;
+ vt.d = ft;
+ for (i = 0; i < 8; ++i) {
+ int r = vs.ub[i] - vt.ub[i];
+ vs.ub[i] = (r < 0 ? -r : r);
+ }
+ return vs.d;
+}
+
+uint64_t helper_biadd(uint64_t fs)
+{
+ unsigned i, fd;
+
+ for (i = fd = 0; i < 8; ++i) {
+ fd += (fs >> (i * 8)) & 0xff;
+ }
+ return fd & 0xffff;
+}
+
+uint64_t helper_pmovmskb(uint64_t fs)
+{
+ unsigned fd = 0;
+
+ fd |= ((fs >> 7) & 1) << 0;
+ fd |= ((fs >> 15) & 1) << 1;
+ fd |= ((fs >> 23) & 1) << 2;
+ fd |= ((fs >> 31) & 1) << 3;
+ fd |= ((fs >> 39) & 1) << 4;
+ fd |= ((fs >> 47) & 1) << 5;
+ fd |= ((fs >> 55) & 1) << 6;
+ fd |= ((fs >> 63) & 1) << 7;
+
+ return fd & 0xff;
+}
* ------------------------------------------------
*/
/*
- * bits 0-31: MIPS base instruction sets
+ * bits 0-23: MIPS base instruction sets
*/
#define ISA_MIPS1 0x0000000000000001ULL
#define ISA_MIPS2 0x0000000000000002ULL
#define ISA_MIPS64R6 0x0000000000004000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
- * bits 32-47: MIPS ASEs
+ * bits 24-39: MIPS ASEs
*/
-#define ASE_MIPS16 0x0000000100000000ULL
-#define ASE_MIPS3D 0x0000000200000000ULL
-#define ASE_MDMX 0x0000000400000000ULL
-#define ASE_DSP 0x0000000800000000ULL
-#define ASE_DSP_R2 0x0000001000000000ULL
-#define ASE_DSP_R3 0x0000002000000000ULL
-#define ASE_MT 0x0000004000000000ULL
-#define ASE_SMARTMIPS 0x0000008000000000ULL
-#define ASE_MICROMIPS 0x0000010000000000ULL
-#define ASE_MSA 0x0000020000000000ULL
+#define ASE_MIPS16 0x0000000001000000ULL
+#define ASE_MIPS3D 0x0000000002000000ULL
+#define ASE_MDMX 0x0000000004000000ULL
+#define ASE_DSP 0x0000000008000000ULL
+#define ASE_DSP_R2 0x0000000010000000ULL
+#define ASE_DSP_R3 0x0000000020000000ULL
+#define ASE_MT 0x0000000040000000ULL
+#define ASE_SMARTMIPS 0x0000000080000000ULL
+#define ASE_MICROMIPS 0x0000000100000000ULL
+#define ASE_MSA 0x0000000200000000ULL
/*
- * bits 48-55: vendor-specific base instruction sets
+ * bits 40-51: vendor-specific base instruction sets
*/
-#define INSN_LOONGSON2E 0x0001000000000000ULL
-#define INSN_LOONGSON2F 0x0002000000000000ULL
-#define INSN_VR54XX 0x0004000000000000ULL
-#define INSN_R5900 0x0008000000000000ULL
+#define INSN_VR54XX 0x0000010000000000ULL
+#define INSN_R5900 0x0000020000000000ULL
+#define INSN_LOONGSON2E 0x0000040000000000ULL
+#define INSN_LOONGSON2F 0x0000080000000000ULL
+#define INSN_LOONGSON3A 0x0000100000000000ULL
/*
- * bits 56-63: vendor-specific ASEs
+ * bits 52-63: vendor-specific ASEs
*/
-#define ASE_MMI 0x0100000000000000ULL
-#define ASE_MXU 0x0200000000000000ULL
+#define ASE_MMI 0x0010000000000000ULL
+#define ASE_MXU 0x0020000000000000ULL
+#define ASE_LMMI 0x0040000000000000ULL
+#define ASE_LEXT 0x0080000000000000ULL
/* MIPS CPU defines. */
#define CPU_MIPS1 (ISA_MIPS1)
/* Wave Computing: "nanoMIPS" */
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
+#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A)
+
/*
* Strictly follow the architecture standard:
* - Disallow "special" instruction handling for PMON/SPIM.
#define CLEAR_IS_INEXACT 2
#define RECIPROCAL_INEXACT 4
-static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
+
+static inline int ieee_to_mips_xcpt_msa(int ieee_xcpt)
{
- int ieee_ex;
+ int mips_xcpt = 0;
- int c;
+ if (ieee_xcpt & float_flag_invalid) {
+ mips_xcpt |= FP_INVALID;
+ }
+ if (ieee_xcpt & float_flag_overflow) {
+ mips_xcpt |= FP_OVERFLOW;
+ }
+ if (ieee_xcpt & float_flag_underflow) {
+ mips_xcpt |= FP_UNDERFLOW;
+ }
+ if (ieee_xcpt & float_flag_divbyzero) {
+ mips_xcpt |= FP_DIV0;
+ }
+ if (ieee_xcpt & float_flag_inexact) {
+ mips_xcpt |= FP_INEXACT;
+ }
+
+ return mips_xcpt;
+}
+
+static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
+{
+ int ieee_exception_flags;
+ int mips_exception_flags = 0;
int cause;
int enable;
- ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
+ ieee_exception_flags = get_float_exception_flags(
+ &env->active_tc.msa_fp_status);
/* QEMU softfloat does not signal all underflow cases */
if (denormal) {
- ieee_ex |= float_flag_underflow;
+ ieee_exception_flags |= float_flag_underflow;
+ }
+ if (ieee_exception_flags) {
+ mips_exception_flags = ieee_to_mips_xcpt_msa(ieee_exception_flags);
}
-
- c = ieee_ex_to_mips(ieee_ex);
enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
/* Set Inexact (I) when flushing inputs to zero */
- if ((ieee_ex & float_flag_input_denormal) &&
+ if ((ieee_exception_flags & float_flag_input_denormal) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
if (action & CLEAR_IS_INEXACT) {
- c &= ~FP_INEXACT;
+ mips_exception_flags &= ~FP_INEXACT;
} else {
- c |= FP_INEXACT;
+ mips_exception_flags |= FP_INEXACT;
}
}
/* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
- if ((ieee_ex & float_flag_output_denormal) &&
+ if ((ieee_exception_flags & float_flag_output_denormal) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
- c |= FP_INEXACT;
+ mips_exception_flags |= FP_INEXACT;
if (action & CLEAR_FS_UNDERFLOW) {
- c &= ~FP_UNDERFLOW;
+ mips_exception_flags &= ~FP_UNDERFLOW;
} else {
- c |= FP_UNDERFLOW;
+ mips_exception_flags |= FP_UNDERFLOW;
}
}
/* Set Inexact (I) when Overflow (O) is not enabled */
- if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
- c |= FP_INEXACT;
+ if ((mips_exception_flags & FP_OVERFLOW) != 0 &&
+ (enable & FP_OVERFLOW) == 0) {
+ mips_exception_flags |= FP_INEXACT;
}
/* Clear Exact Underflow when Underflow (U) is not enabled */
- if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
- (c & FP_INEXACT) == 0) {
- c &= ~FP_UNDERFLOW;
+ if ((mips_exception_flags & FP_UNDERFLOW) != 0 &&
+ (enable & FP_UNDERFLOW) == 0 &&
+ (mips_exception_flags & FP_INEXACT) == 0) {
+ mips_exception_flags &= ~FP_UNDERFLOW;
}
/*
* divide by zero
*/
if ((action & RECIPROCAL_INEXACT) &&
- (c & (FP_INVALID | FP_DIV0)) == 0) {
- c = FP_INEXACT;
+ (mips_exception_flags & (FP_INVALID | FP_DIV0)) == 0) {
+ mips_exception_flags = FP_INEXACT;
}
- cause = c & enable; /* all current enabled exceptions */
+ cause = mips_exception_flags & enable; /* all current enabled exceptions */
if (cause == 0) {
/*
* with all current exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
- (GET_FP_CAUSE(env->active_tc.msacsr) | c));
+ (GET_FP_CAUSE(env->active_tc.msacsr) | mips_exception_flags));
} else {
/* Current exceptions are enabled */
if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
* with all enabled exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
- (GET_FP_CAUSE(env->active_tc.msacsr) | c));
+ (GET_FP_CAUSE(env->active_tc.msacsr) | mips_exception_flags));
}
}
- return c;
+ return mips_exception_flags;
}
static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
env->CP0_Config5 = env->cpu_model->CP0_Config5;
env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
env->CP0_Config6 = env->cpu_model->CP0_Config6;
+ env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
env->CP0_Config7 = env->cpu_model->CP0_Config7;
+ env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
<< env->cpu_model->CP0_LLAddr_shift;
env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
},
{
/* FIXME:
- * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL
+ * Config3: VZ, CTXTC, CDMM, TL
* Config4: MMUExtDef
* Config5: MRP
* FIR(FCR0): Has2008
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_FP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
- (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) |
- (1 << CP0C3_VInt),
+ (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
+ (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
(0x1c << CP0C4_KScrExist),
.CP0_Config4_rw_bitmask = 0,
.insn_flags = CPU_LOONGSON2F,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ .name = "Loongson-3A1000",
+ .CP0_PRid = 0x6305,
+ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+ (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
+ (3 << CP0C2_SA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x74D8FFFF,
+ .CP0_PageGrain = (1 << CP0PG_ELPA),
+ .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
+ (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
+ (0x1 << FCR0_D) | (0x1 << FCR0_S),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 42,
+ .PABITS = 48,
+ .insn_flags = CPU_LOONGSON3A,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "Loongson-3A4000",
+ .CP0_PRid = 0x14C000,
+ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
+ (15 << CP0C2_SA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
+ (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
+ .CP0_Config4_rw_bitmask = 0,
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
+ (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
+ (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
+ .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
+ (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
+ (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
+ .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
+ (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
+ (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
+ (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
+ (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
+ (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
+ (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
+ (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
+ (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
+ (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
+ (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
+ (1 << CP0C6_DATAPREF),
+ .CP0_Config7 = 0,
+ .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
+ (1 << CP0C7_VFPUCGEN),
+ .CP0_LLAddr_rw_bitmask = 1,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x7DDBFFFF,
+ .CP0_PageGrain = (1 << CP0PG_ELPA),
+ .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
+ (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
+ (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
+ (0x1 << FCR0_D) | (0x1 << FCR0_S),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 48,
+ .PABITS = 48,
+ .insn_flags = CPU_LOONGSON3A,
+ .mmu_type = MMU_TYPE_R4000,
+ },
{
/* A generic CPU providing MIPS64 DSP R2 ASE features.
FIXME: Eventually this should be replaced by a real CPU model. */
*/
#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
-#include "exec/gdbstub.h"
#include "exec/helper-proto.h"
-#include "qemu/host-utils.h"
-#ifndef CONFIG_USER_ONLY
-#include "ui/console.h"
-#endif
+#include "hw/semihosting/console.h"
#undef DEBUG_UC32
}
return;
unrecognized:
- DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
- creg, cop);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+ creg, cop);
}
uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
}
break;
}
- DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
- creg, cop);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+ creg, cop);
return 0;
}
-#ifdef CONFIG_CURSES
-
-/* KEY_EVENT is defined in wincon.h and in curses.h. Avoid redefinition. */
-#undef KEY_EVENT
-#include <curses.h>
-#undef KEY_EVENT
-
-/*
- * FIXME:
- * 1. curses windows will be blank when switching back
- * 2. backspace is not handled yet
- */
-static void putc_on_screen(unsigned char ch)
+void helper_cp1_putc(target_ulong regval)
{
- static WINDOW *localwin;
- static int init;
-
- if (!init) {
- /* Assume 80 * 30 screen to minimize the implementation */
- localwin = newwin(30, 80, 0, 0);
- scrollok(localwin, TRUE);
- init = TRUE;
- }
+ const char c = regval;
- if (isprint(ch)) {
- wprintw(localwin, "%c", ch);
- } else {
- switch (ch) {
- case '\n':
- wprintw(localwin, "%c", ch);
- break;
- case '\r':
- /* If '\r' is put before '\n', the curses window will destroy the
- * last print line. And meanwhile, '\n' implifies '\r' inside. */
- break;
- default: /* Not handled, so just print it hex code */
- wprintw(localwin, "-- 0x%x --", ch);
- }
- }
-
- wrefresh(localwin);
-}
-#else
-#define putc_on_screen(c) do { } while (0)
-#endif
-
-void helper_cp1_putc(target_ulong x)
-{
- putc_on_screen((unsigned char)x); /* Output to screen */
- DPRINTF("%c", x); /* Output to stdout */
+ qemu_semihosting_log_out(&c, sizeof(c));
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
%sub1 0:8
%sub2 8:8
-%sub3 16:8
-%sub4 24:8
-# Groups with no overlap are supposed to fail
+# Make sure braces are matched
{
- top 00000000 00000000 00000000 00000000
- sub4 ........ ........ ........ ........ %sub1 %sub2 %sub3 %sub4
+ top 00000000 00000000 00000000 00000000
+ [
+ sub1 00000000 00000000 00000000 ........ %sub1
+ sub2 00000000 00000000 ........ ........ %sub1 %sub2
+ }
}
--- /dev/null
+# This work is licensed under the terms of the GNU LGPL, version 2 or later.
+# See the COPYING.LIB file in the top-level directory.
+
+# Make sure braces are matched
+{
+ [
--- /dev/null
+# This work is licensed under the terms of the GNU LGPL, version 2 or later.
+# See the COPYING.LIB file in the top-level directory.
+
+%sub1 0:8
+%sub2 8:8
+
+# The exclusive group should error for overlap.
+{
+ top 00000000 00000000 00000000 00000000
+ [
+ sub1 00000000 00000000 00000000 ........ %sub1
+ sub2 00000000 00000000 ........ ........ %sub1 %sub2
+ ]
+}
--- /dev/null
+# This work is licensed under the terms of the GNU LGPL, version 2 or later.
+# See the COPYING.LIB file in the top-level directory.
+
+%sub1 0:8
+%sub2 8:8
+%sub3 16:8
+%sub4 24:8
+
+# Group with complete overlap of the two patterns
+{
+ top 00000000 00000000 00000000 00000000
+ sub4 ........ ........ ........ ........ %sub1 %sub2 %sub3 %sub4
+}
--- /dev/null
+# This work is licensed under the terms of the GNU LGPL, version 2 or later.
+# See the COPYING.LIB file in the top-level directory.
+
+{
+ [
+ sub1 00000000 a:8 b:8 c:8
+ sub2 00000001 a:8 b:8 c:8
+ sub3 00000010 a:8 b:8 c:8
+ ]
+ sub4 000000 d:2 a:8 b:8 c:8
+}
--- /dev/null
+# This work is licensed under the terms of the GNU LGPL, version 2 or later.
+# See the COPYING.LIB file in the top-level directory.
+
+# Verify deeper nesting, and a single element in the groups.
+{
+ [
+ {
+ [
+ sub1 00000000 a:8 b:8 c:8
+ ]
+ }
+ ]
+}
docker-image-travis: NOUSER=1
# Specialist build images, sometimes very limited tools
-docker-image-tricore-cross: docker-image-debian9
+docker-image-debian-tricore-cross: docker-image-debian9
docker-image-debian-arm64-test-cross: docker-image-debian11
# These images may be good enough for building tests but not for test builds
# Please keep this list sorted alphabetically
ENV PACKAGES \
- bison \
bzip2 \
bzip2-devel \
ccache \
csnappy-devel \
dbus-daemon \
- flex \
gcc-c++ \
gcc \
gettext \
RUN dnf -y update
ENV PACKAGES \
SDL-devel \
- bison \
bzip2 \
bzip2-devel \
dbus-daemon \
- flex \
gcc \
gcc-c++ \
gettext \
DEBIAN_FRONTEND=noninteractive apt install -yy eatmydata && \
DEBIAN_FRONTEND=noninteractive eatmydata \
apt-get install -y --no-install-recommends \
- bison \
build-essential \
ca-certificates \
curl \
- flex \
gettext \
git \
python3-minimal
DEBIAN_FRONTEND=noninteractive eatmydata \
apt install -y --no-install-recommends \
bc \
- bison \
build-essential \
ca-certificates \
clang \
dbus \
- flex \
gdb-multiarch \
gettext \
git \
DEBIAN_FRONTEND=noninteractive eatmydata \
apt install -y --no-install-recommends \
bc \
- bison \
build-essential \
ca-certificates \
clang \
- flex \
gdb-multiarch \
gettext \
git \
# Please keep this list sorted alphabetically
ENV PACKAGES \
bc \
- bison \
brlapi-devel \
bzip2 \
bzip2-devel \
dbus-daemon \
device-mapper-multipath-devel \
findutils \
- flex \
gcc \
gcc-c++ \
gettext \
# system won't pick up that it has changed.
#
-FROM ubuntu:19.04
-ENV PACKAGES flex bison \
+FROM ubuntu:20.04
+ENV PACKAGES \
ccache \
clang \
dbus \
FROM ubuntu:18.04
-ENV PACKAGES flex bison \
+ENV PACKAGES \
ccache \
clang \
gcc \
g_string_printf(out, "mem accesses: %" PRIu64 "\n", mem_count);
if (do_haddr) {
- g_string_append_printf(out, "io accesses: %" PRIu64 "\n", mem_count);
+ g_string_append_printf(out, "io accesses: %" PRIu64 "\n", io_count);
}
qemu_plugin_outs(out->str);
}
header_length 72
Header extension:
-magic 0x12345678
+magic 0x12345678 (<unknown>)
length 31
data 'This is a test header extension'
header_length 72
Header extension:
-magic 0x12345678
+magic 0x12345678 (<unknown>)
length 31
data 'This is a test header extension'
header_length 72
Header extension:
-magic 0xe2792aca
+magic 0xe2792aca (Backing format)
length 11
data 'host_device'
Header extension:
-magic 0x12345678
+magic 0x12345678 (<unknown>)
length 31
data 'This is a test header extension'
header_length 112
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
Header extension:
-magic 0x12345678
+magic 0x12345678 (<unknown>)
length 31
data 'This is a test header extension'
header_length 112
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
Header extension:
-magic 0x12345678
+magic 0x12345678 (<unknown>)
length 31
data 'This is a test header extension'
header_length 112
Header extension:
-magic 0xe2792aca
+magic 0xe2792aca (Backing format)
length 11
data 'host_device'
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
Header extension:
-magic 0x12345678
+magic 0x12345678 (<unknown>)
length 31
data 'This is a test header extension'
compatible_features []
autoclear_features [63]
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
compatible_features []
autoclear_features []
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
header_length 112
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
header_length 112
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
header_length 112
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
header_length 112
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
header_length 112
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
header_length 112
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
header_length 112
Header extension:
-magic 0x6803f857
+magic 0x6803f857 (Feature table)
length 336
data <binary>
$QEMU_IO_PROG -f raw -c quit \
"nbd+unix:///no_such_export?socket=$SOCK_DIR/nbd" 2>&1 \
| _filter_qemu_io | _filter_nbd
+# Likewise, with longest possible name permitted in NBD protocol
+$QEMU_IO_PROG -f raw -c quit \
+ "nbd+unix:///$(printf %4096d 1 | tr ' ' a)?socket=$SOCK_DIR/nbd" 2>&1 \
+ | _filter_qemu_io | _filter_nbd | sed 's/aaaa*aa/aa--aa/'
_send_qemu_cmd $QEMU_HANDLE \
"{ 'execute': 'quit' }" \
{"return": {}}
qemu-io: can't open device nbd+unix:///no_such_export?socket=SOCK_DIR/nbd: Requested export not available
server reported: export 'no_such_export' not present
+qemu-io: can't open device nbd+unix:///aa--aa1?socket=SOCK_DIR/nbd: Requested export not available
+server reported: export 'aa--aa...' not present
{ 'execute': 'quit' }
{"return": {}}
{"timestamp": {"seconds": TIMESTAMP, "microseconds": TIMESTAMP}, "event": "SHUTDOWN", "data": {"guest": false, "reason": "host-qmp-quit"}}
iotests.log(dest_vm.qmp('nbd-server-stop'))
break
+ iotests.log('Wait for migration completion on target...')
+ migr_events = (('MIGRATION', {'data': {'status': 'completed'}}),
+ ('MIGRATION', {'data': {'status': 'failed'}}))
+ event = dest_vm.events_wait(migr_events)
+ iotests.log(event, filters=[iotests.filter_qmp_event])
+
+ iotests.log('Check bitmaps on source:')
iotests.log(source_vm.qmp('query-block')['return'][0]['dirty-bitmaps'])
+
+ iotests.log('Check bitmaps on target:')
+ iotests.log(dest_vm.qmp('query-block')['return'][0]['dirty-bitmaps'])
{"data": {"device": "mirror-job0", "len": 1073741824, "offset": 1073741824, "speed": 0, "type": "mirror"}, "event": "BLOCK_JOB_COMPLETED", "timestamp": {"microseconds": "USECS", "seconds": "SECS"}}
Stopping the NBD server on destination...
{"return": {}}
+Wait for migration completion on target...
+{"data": {"status": "completed"}, "event": "MIGRATION", "timestamp": {"microseconds": "USECS", "seconds": "SECS"}}
+Check bitmaps on source:
+[{"busy": false, "count": 0, "granularity": 65536, "name": "bitmap0", "persistent": false, "recording": true, "status": "active"}]
+Check bitmaps on target:
[{"busy": false, "count": 0, "granularity": 65536, "name": "bitmap0", "persistent": false, "recording": true, "status": "active"}]
$QEMU_IMG bitmap --disable -f $IMGFMT "$TEST_IMG" b1
$QEMU_IMG bitmap --enable -f $IMGFMT "$TEST_IMG" b2
$QEMU_IO -c 'w 2M 1M' -f $IMGFMT "$TEST_IMG" | _filter_qemu_io
+echo "Check resulting qcow2 header extensions:"
+$PYTHON qcow2.py "$TEST_IMG" dump-header-exts
echo
echo "=== Bitmap preservation not possible to non-qcow2 ==="
# Only bitmaps from the active layer are copied
$QEMU_IMG convert --bitmaps -O qcow2 "$TEST_IMG.orig" "$TEST_IMG"
-$QEMU_IMG info "$TEST_IMG" | _filter_img_info --format-specific
+_img_info --format-specific
# But we can also merge in bitmaps from other layers. This test is a bit
# contrived to cover more code paths, in reality, you could merge directly
# into b0 without going through tmp
$QEMU_IMG bitmap --merge tmp -f $IMGFMT "$TEST_IMG" b0
$QEMU_IMG bitmap --remove --image-opts \
driver=$IMGFMT,file.driver=file,file.filename="$TEST_IMG" tmp
-$QEMU_IMG info "$TEST_IMG" | _filter_img_info --format-specific
+_img_info --format-specific
+echo "Check resulting qcow2 header extensions:"
+$PYTHON qcow2.py "$TEST_IMG" dump-header-exts
echo
echo "=== Check bitmap contents ==="
1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
wrote 1048576/1048576 bytes at offset 2097152
1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+Check resulting qcow2 header extensions:
+Header extension:
+magic 0xe2792aca (Backing format)
+length 5
+data 'qcow2'
+
+Header extension:
+magic 0x6803f857 (Feature table)
+length 336
+data <binary>
+
+Header extension:
+magic 0x23852875 (Bitmaps)
+length 24
+nb_bitmaps 2
+reserved32 0
+bitmap_directory_size 0x40
+bitmap_directory_offset 0x510000
+
=== Bitmap preservation not possible to non-qcow2 ===
image: TEST_DIR/t.IMGFMT
file format: IMGFMT
virtual size: 10 MiB (10485760 bytes)
-disk size: 4.39 MiB
+cluster_size: 65536
Format specific information:
compat: 1.1
compression type: zlib
image: TEST_DIR/t.IMGFMT
file format: IMGFMT
virtual size: 10 MiB (10485760 bytes)
-disk size: 4.48 MiB
+cluster_size: 65536
Format specific information:
compat: 1.1
compression type: zlib
granularity: 65536
refcount bits: 16
corrupt: false
+Check resulting qcow2 header extensions:
+Header extension:
+magic 0x6803f857 (Feature table)
+length 336
+data <binary>
+
+Header extension:
+magic 0x23852875 (Bitmaps)
+length 24
+nb_bitmaps 3
+reserved32 0
+bitmap_directory_size 0x60
+bitmap_directory_offset 0x520000
+
=== Check bitmap contents ===
#!/usr/bin/env python3
+#
+# Manipulations with qcow2 image
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
import sys
-import struct
-import string
-
-class QcowHeaderExtension:
-
- def __init__(self, magic, length, data):
- if length % 8 != 0:
- padding = 8 - (length % 8)
- data += b"\0" * padding
-
- self.magic = magic
- self.length = length
- self.data = data
-
- @classmethod
- def create(cls, magic, data):
- return QcowHeaderExtension(magic, len(data), data)
-
-class QcowHeader:
-
- uint32_t = 'I'
- uint64_t = 'Q'
-
- fields = [
- # Version 2 header fields
- [ uint32_t, '%#x', 'magic' ],
- [ uint32_t, '%d', 'version' ],
- [ uint64_t, '%#x', 'backing_file_offset' ],
- [ uint32_t, '%#x', 'backing_file_size' ],
- [ uint32_t, '%d', 'cluster_bits' ],
- [ uint64_t, '%d', 'size' ],
- [ uint32_t, '%d', 'crypt_method' ],
- [ uint32_t, '%d', 'l1_size' ],
- [ uint64_t, '%#x', 'l1_table_offset' ],
- [ uint64_t, '%#x', 'refcount_table_offset' ],
- [ uint32_t, '%d', 'refcount_table_clusters' ],
- [ uint32_t, '%d', 'nb_snapshots' ],
- [ uint64_t, '%#x', 'snapshot_offset' ],
-
- # Version 3 header fields
- [ uint64_t, 'mask', 'incompatible_features' ],
- [ uint64_t, 'mask', 'compatible_features' ],
- [ uint64_t, 'mask', 'autoclear_features' ],
- [ uint32_t, '%d', 'refcount_order' ],
- [ uint32_t, '%d', 'header_length' ],
- ];
-
- fmt = '>' + ''.join(field[0] for field in fields)
-
- def __init__(self, fd):
-
- buf_size = struct.calcsize(QcowHeader.fmt)
-
- fd.seek(0)
- buf = fd.read(buf_size)
-
- header = struct.unpack(QcowHeader.fmt, buf)
- self.__dict__ = dict((field[2], header[i])
- for i, field in enumerate(QcowHeader.fields))
-
- self.set_defaults()
- self.cluster_size = 1 << self.cluster_bits
-
- fd.seek(self.header_length)
- self.load_extensions(fd)
-
- if self.backing_file_offset:
- fd.seek(self.backing_file_offset)
- self.backing_file = fd.read(self.backing_file_size)
- else:
- self.backing_file = None
-
- def set_defaults(self):
- if self.version == 2:
- self.incompatible_features = 0
- self.compatible_features = 0
- self.autoclear_features = 0
- self.refcount_order = 4
- self.header_length = 72
-
- def load_extensions(self, fd):
- self.extensions = []
-
- if self.backing_file_offset != 0:
- end = min(self.cluster_size, self.backing_file_offset)
- else:
- end = self.cluster_size
-
- while fd.tell() < end:
- (magic, length) = struct.unpack('>II', fd.read(8))
- if magic == 0:
- break
- else:
- padded = (length + 7) & ~7
- data = fd.read(padded)
- self.extensions.append(QcowHeaderExtension(magic, length, data))
-
- def update_extensions(self, fd):
-
- fd.seek(self.header_length)
- extensions = self.extensions
- extensions.append(QcowHeaderExtension(0, 0, b""))
- for ex in extensions:
- buf = struct.pack('>II', ex.magic, ex.length)
- fd.write(buf)
- fd.write(ex.data)
-
- if self.backing_file != None:
- self.backing_file_offset = fd.tell()
- fd.write(self.backing_file)
-
- if fd.tell() > self.cluster_size:
- raise Exception("I think I just broke the image...")
-
-
- def update(self, fd):
- header_bytes = self.header_length
-
- self.update_extensions(fd)
-
- fd.seek(0)
- header = tuple(self.__dict__[f] for t, p, f in QcowHeader.fields)
- buf = struct.pack(QcowHeader.fmt, *header)
- buf = buf[0:header_bytes-1]
- fd.write(buf)
-
- def dump(self):
- for f in QcowHeader.fields:
- value = self.__dict__[f[2]]
- if f[1] == 'mask':
- bits = []
- for bit in range(64):
- if value & (1 << bit):
- bits.append(bit)
- value_str = str(bits)
- else:
- value_str = f[1] % value
-
- print("%-25s" % f[2], value_str)
- print("")
-
- def dump_extensions(self):
- for ex in self.extensions:
- data = ex.data[:ex.length]
- if all(c in string.printable.encode('ascii') for c in data):
- data = "'%s'" % data.decode('ascii')
- else:
- data = "<binary>"
-
- print("Header extension:")
- print("%-25s %#x" % ("magic", ex.magic))
- print("%-25s %d" % ("length", ex.length))
- print("%-25s %s" % ("data", data))
- print("")
+from qcow2_format import (
+ QcowHeader,
+ QcowHeaderExtension
+)
def cmd_dump_header(fd):
h = QcowHeader(fd)
h.dump()
+ print()
h.dump_extensions()
+
def cmd_dump_header_exts(fd):
h = QcowHeader(fd)
h.dump_extensions()
+
def cmd_set_header(fd, name, value):
try:
value = int(value, 0)
- except:
+ except ValueError:
print("'%s' is not a valid number" % value)
sys.exit(1)
fields = (field[2] for field in QcowHeader.fields)
- if not name in fields:
+ if name not in fields:
print("'%s' is not a known header field" % name)
sys.exit(1)
h.__dict__[name] = value
h.update(fd)
+
def cmd_add_header_ext(fd, magic, data):
try:
magic = int(magic, 0)
- except:
+ except ValueError:
print("'%s' is not a valid magic number" % magic)
sys.exit(1)
h = QcowHeader(fd)
- h.extensions.append(QcowHeaderExtension.create(magic, data.encode('ascii')))
+ h.extensions.append(QcowHeaderExtension.create(magic,
+ data.encode('ascii')))
h.update(fd)
+
def cmd_add_header_ext_stdio(fd, magic):
data = sys.stdin.read()
cmd_add_header_ext(fd, magic, data)
+
def cmd_del_header_ext(fd, magic):
try:
magic = int(magic, 0)
- except:
+ except ValueError:
print("'%s' is not a valid magic number" % magic)
sys.exit(1)
h.update(fd)
+
def cmd_set_feature_bit(fd, group, bit):
try:
bit = int(bit, 0)
if bit < 0 or bit >= 64:
raise ValueError
- except:
+ except ValueError:
print("'%s' is not a valid bit number in range [0, 64)" % bit)
sys.exit(1)
elif group == 'autoclear':
h.autoclear_features |= 1 << bit
else:
- print("'%s' is not a valid group, try 'incompatible', 'compatible', or 'autoclear'" % group)
+ print("'%s' is not a valid group, try "
+ "'incompatible', 'compatible', or 'autoclear'" % group)
sys.exit(1)
h.update(fd)
+
cmds = [
- [ 'dump-header', cmd_dump_header, 0, 'Dump image header and header extensions' ],
- [ 'dump-header-exts', cmd_dump_header_exts, 0, 'Dump image header extensions' ],
- [ 'set-header', cmd_set_header, 2, 'Set a field in the header'],
- [ 'add-header-ext', cmd_add_header_ext, 2, 'Add a header extension' ],
- [ 'add-header-ext-stdio', cmd_add_header_ext_stdio, 1, 'Add a header extension, data from stdin' ],
- [ 'del-header-ext', cmd_del_header_ext, 1, 'Delete a header extension' ],
- [ 'set-feature-bit', cmd_set_feature_bit, 2, 'Set a feature bit'],
+ ['dump-header', cmd_dump_header, 0,
+ 'Dump image header and header extensions'],
+ ['dump-header-exts', cmd_dump_header_exts, 0,
+ 'Dump image header extensions'],
+ ['set-header', cmd_set_header, 2, 'Set a field in the header'],
+ ['add-header-ext', cmd_add_header_ext, 2, 'Add a header extension'],
+ ['add-header-ext-stdio', cmd_add_header_ext_stdio, 1,
+ 'Add a header extension, data from stdin'],
+ ['del-header-ext', cmd_del_header_ext, 1, 'Delete a header extension'],
+ ['set-feature-bit', cmd_set_feature_bit, 2, 'Set a feature bit'],
]
+
def main(filename, cmd, args):
fd = open(filename, "r+b")
try:
finally:
fd.close()
+
def usage():
print("Usage: %s <file> <cmd> [<arg>, ...]" % sys.argv[0])
print("")
for name, handler, num_args, desc in cmds:
print(" %-20s - %s" % (name, desc))
+
if __name__ == '__main__':
if len(sys.argv) < 3:
usage()
--- /dev/null
+# Library for manipulations with qcow2 image
+#
+# Copyright (c) 2020 Virtuozzo International GmbH.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+import struct
+import string
+
+
+class Qcow2Field:
+
+ def __init__(self, value):
+ self.value = value
+
+ def __str__(self):
+ return str(self.value)
+
+
+class Flags64(Qcow2Field):
+
+ def __str__(self):
+ bits = []
+ for bit in range(64):
+ if self.value & (1 << bit):
+ bits.append(bit)
+ return str(bits)
+
+
+class Enum(Qcow2Field):
+
+ def __str__(self):
+ return f'{self.value:#x} ({self.mapping.get(self.value, "<unknown>")})'
+
+
+class Qcow2StructMeta(type):
+
+ # Mapping from c types to python struct format
+ ctypes = {
+ 'u8': 'B',
+ 'u16': 'H',
+ 'u32': 'I',
+ 'u64': 'Q'
+ }
+
+ def __init__(self, name, bases, attrs):
+ if 'fields' in attrs:
+ self.fmt = '>' + ''.join(self.ctypes[f[0]] for f in self.fields)
+
+
+class Qcow2Struct(metaclass=Qcow2StructMeta):
+
+ """Qcow2Struct: base class for qcow2 data structures
+
+ Successors should define fields class variable, which is: list of tuples,
+ each of three elements:
+ - c-type (one of 'u8', 'u16', 'u32', 'u64')
+ - format (format_spec to use with .format() when dump or 'mask' to dump
+ bitmasks)
+ - field name
+ """
+
+ def __init__(self, fd=None, offset=None, data=None):
+ """
+ Two variants:
+ 1. Specify data. fd and offset must be None.
+ 2. Specify fd and offset, data must be None. offset may be omitted
+ in this case, than current position of fd is used.
+ """
+ if data is None:
+ assert fd is not None
+ buf_size = struct.calcsize(self.fmt)
+ if offset is not None:
+ fd.seek(offset)
+ data = fd.read(buf_size)
+ else:
+ assert fd is None and offset is None
+
+ values = struct.unpack(self.fmt, data)
+ self.__dict__ = dict((field[2], values[i])
+ for i, field in enumerate(self.fields))
+
+ def dump(self):
+ for f in self.fields:
+ value = self.__dict__[f[2]]
+ if isinstance(f[1], str):
+ value_str = f[1].format(value)
+ else:
+ value_str = str(f[1](value))
+
+ print('{:<25} {}'.format(f[2], value_str))
+
+
+class Qcow2BitmapExt(Qcow2Struct):
+
+ fields = (
+ ('u32', '{}', 'nb_bitmaps'),
+ ('u32', '{}', 'reserved32'),
+ ('u64', '{:#x}', 'bitmap_directory_size'),
+ ('u64', '{:#x}', 'bitmap_directory_offset')
+ )
+
+
+QCOW2_EXT_MAGIC_BITMAPS = 0x23852875
+
+
+class QcowHeaderExtension(Qcow2Struct):
+
+ class Magic(Enum):
+ mapping = {
+ 0xe2792aca: 'Backing format',
+ 0x6803f857: 'Feature table',
+ 0x0537be77: 'Crypto header',
+ QCOW2_EXT_MAGIC_BITMAPS: 'Bitmaps',
+ 0x44415441: 'Data file'
+ }
+
+ fields = (
+ ('u32', Magic, 'magic'),
+ ('u32', '{}', 'length')
+ # length bytes of data follows
+ # then padding to next multiply of 8
+ )
+
+ def __init__(self, magic=None, length=None, data=None, fd=None):
+ """
+ Support both loading from fd and creation from user data.
+ For fd-based creation current position in a file will be used to read
+ the data.
+
+ This should be somehow refactored and functionality should be moved to
+ superclass (to allow creation of any qcow2 struct), but then, fields
+ of variable length (data here) should be supported in base class
+ somehow. Note also, that we probably want to parse different
+ extensions. Should they be subclasses of this class, or how to do it
+ better? Should it be something like QAPI union with discriminator field
+ (magic here). So, it's a TODO. We'll see how to properly refactor this
+ when we have more qcow2 structures.
+ """
+ if fd is None:
+ assert all(v is not None for v in (magic, length, data))
+ self.magic = magic
+ self.length = length
+ if length % 8 != 0:
+ padding = 8 - (length % 8)
+ data += b'\0' * padding
+ self.data = data
+ else:
+ assert all(v is None for v in (magic, length, data))
+ super().__init__(fd=fd)
+ padded = (self.length + 7) & ~7
+ self.data = fd.read(padded)
+ assert self.data is not None
+
+ if self.magic == QCOW2_EXT_MAGIC_BITMAPS:
+ self.obj = Qcow2BitmapExt(data=self.data)
+ else:
+ self.obj = None
+
+ def dump(self):
+ super().dump()
+
+ if self.obj is None:
+ data = self.data[:self.length]
+ if all(c in string.printable.encode('ascii') for c in data):
+ data = f"'{ data.decode('ascii') }'"
+ else:
+ data = '<binary>'
+ print(f'{"data":<25} {data}')
+ else:
+ self.obj.dump()
+
+ @classmethod
+ def create(cls, magic, data):
+ return QcowHeaderExtension(magic, len(data), data)
+
+
+class QcowHeader(Qcow2Struct):
+
+ fields = (
+ # Version 2 header fields
+ ('u32', '{:#x}', 'magic'),
+ ('u32', '{}', 'version'),
+ ('u64', '{:#x}', 'backing_file_offset'),
+ ('u32', '{:#x}', 'backing_file_size'),
+ ('u32', '{}', 'cluster_bits'),
+ ('u64', '{}', 'size'),
+ ('u32', '{}', 'crypt_method'),
+ ('u32', '{}', 'l1_size'),
+ ('u64', '{:#x}', 'l1_table_offset'),
+ ('u64', '{:#x}', 'refcount_table_offset'),
+ ('u32', '{}', 'refcount_table_clusters'),
+ ('u32', '{}', 'nb_snapshots'),
+ ('u64', '{:#x}', 'snapshot_offset'),
+
+ # Version 3 header fields
+ ('u64', Flags64, 'incompatible_features'),
+ ('u64', Flags64, 'compatible_features'),
+ ('u64', Flags64, 'autoclear_features'),
+ ('u32', '{}', 'refcount_order'),
+ ('u32', '{}', 'header_length'),
+ )
+
+ def __init__(self, fd):
+ super().__init__(fd=fd, offset=0)
+
+ self.set_defaults()
+ self.cluster_size = 1 << self.cluster_bits
+
+ fd.seek(self.header_length)
+ self.load_extensions(fd)
+
+ if self.backing_file_offset:
+ fd.seek(self.backing_file_offset)
+ self.backing_file = fd.read(self.backing_file_size)
+ else:
+ self.backing_file = None
+
+ def set_defaults(self):
+ if self.version == 2:
+ self.incompatible_features = 0
+ self.compatible_features = 0
+ self.autoclear_features = 0
+ self.refcount_order = 4
+ self.header_length = 72
+
+ def load_extensions(self, fd):
+ self.extensions = []
+
+ if self.backing_file_offset != 0:
+ end = min(self.cluster_size, self.backing_file_offset)
+ else:
+ end = self.cluster_size
+
+ while fd.tell() < end:
+ ext = QcowHeaderExtension(fd=fd)
+ if ext.magic == 0:
+ break
+ else:
+ self.extensions.append(ext)
+
+ def update_extensions(self, fd):
+
+ fd.seek(self.header_length)
+ extensions = self.extensions
+ extensions.append(QcowHeaderExtension(0, 0, b''))
+ for ex in extensions:
+ buf = struct.pack('>II', ex.magic, ex.length)
+ fd.write(buf)
+ fd.write(ex.data)
+
+ if self.backing_file is not None:
+ self.backing_file_offset = fd.tell()
+ fd.write(self.backing_file)
+
+ if fd.tell() > self.cluster_size:
+ raise Exception('I think I just broke the image...')
+
+ def update(self, fd):
+ header_bytes = self.header_length
+
+ self.update_extensions(fd)
+
+ fd.seek(0)
+ header = tuple(self.__dict__[f] for t, p, f in QcowHeader.fields)
+ buf = struct.pack(QcowHeader.fmt, *header)
+ buf = buf[0:header_bytes-1]
+ fd.write(buf)
+
+ def dump_extensions(self):
+ for ex in self.extensions:
+ print('Header extension:')
+ ex.dump()
+ print()
tests/qtest/boot-order-test$(EXESUF): tests/qtest/boot-order-test.o $(libqos-obj-y)
tests/qtest/boot-serial-test$(EXESUF): tests/qtest/boot-serial-test.o $(libqos-obj-y)
tests/qtest/bios-tables-test$(EXESUF): tests/qtest/bios-tables-test.o \
+ tests/qtest/tpm-emu.o $(test-io-obj-y) \
tests/qtest/boot-sector.o tests/qtest/acpi-utils.o $(libqos-obj-y)
tests/qtest/pxe-test$(EXESUF): tests/qtest/pxe-test.o tests/qtest/boot-sector.o $(libqos-obj-y)
tests/qtest/microbit-test$(EXESUF): tests/qtest/microbit-test.o
#include "qemu/bitmap.h"
#include "acpi-utils.h"
#include "boot-sector.h"
+#include "tpm-emu.h"
+#include "hw/acpi/tpm.h"
+
#define MACHINE_PC "pc"
#define MACHINE_Q35 "q35"
free_test_data(&data);
}
+uint64_t tpm_tis_base_addr;
+
+static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if,
+ uint64_t base)
+{
+ gchar *tmp_dir_name = g_strdup_printf("qemu-test_acpi_%s_tcg_%s.XXXXXX",
+ machine, tpm_if);
+ char *tmp_path = g_dir_make_tmp(tmp_dir_name, NULL);
+ TestState test;
+ test_data data;
+ GThread *thread;
+ char *args, *variant = g_strdup_printf(".%s", tpm_if);
+
+ tpm_tis_base_addr = base;
+
+ module_call_init(MODULE_INIT_QOM);
+
+ test.addr = g_new0(SocketAddress, 1);
+ test.addr->type = SOCKET_ADDRESS_TYPE_UNIX;
+ test.addr->u.q_unix.path = g_build_filename(tmp_path, "sock", NULL);
+ g_mutex_init(&test.data_mutex);
+ g_cond_init(&test.data_cond);
+ test.data_cond_signal = false;
+
+ thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test);
+ tpm_emu_test_wait_cond(&test);
+
+ memset(&data, 0, sizeof(data));
+ data.machine = machine;
+ data.variant = variant;
+
+ args = g_strdup_printf(
+ " -chardev socket,id=chr,path=%s"
+ " -tpmdev emulator,id=dev,chardev=chr"
+ " -device tpm-%s,tpmdev=dev",
+ test.addr->u.q_unix.path, tpm_if);
+
+ test_acpi_one(args, &data);
+
+ g_thread_join(thread);
+ g_unlink(test.addr->u.q_unix.path);
+ qapi_free_SocketAddress(test.addr);
+ g_rmdir(tmp_path);
+ g_free(variant);
+ g_free(tmp_path);
+ g_free(tmp_dir_name);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_tpm_tis(void)
+{
+ test_acpi_tcg_tpm("q35", "tis", 0xFED40000);
+}
+
static void test_acpi_tcg_dimm_pxm(const char *machine)
{
test_data data;
return ret;
}
+ qtest_add_func("acpi/q35/tpm-tis", test_acpi_q35_tcg_tpm_tis);
qtest_add_func("acpi/piix4", test_acpi_piix4_tcg);
qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge);
qtest_add_func("acpi/q35", test_acpi_q35_tcg);
s->tpm_msg->tag = be16_to_cpu(s->tpm_msg->tag);
s->tpm_msg->len = be32_to_cpu(s->tpm_msg->len);
g_assert_cmpint(s->tpm_msg->len, >=, minhlen);
- g_assert_cmpint(s->tpm_msg->tag, ==, TPM2_ST_NO_SESSIONS);
s->tpm_msg = g_realloc(s->tpm_msg, s->tpm_msg->len);
qio_channel_read(ioc, (char *)&s->tpm_msg->code,
#define TPM_RC_FAILURE 0x101
#define TPM2_ST_NO_SESSIONS 0x8001
+#include "qemu/sockets.h"
+#include "io/channel.h"
+
struct tpm_hdr {
uint16_t tag;
uint32_t len;
run-plugin-semiconsole-arm-with-%:
$(call skip-test, $<, "MANUAL ONLY")
+ARM_TESTS += commpage
+
TESTS += $(ARM_TESTS)
# On ARM Linux only supports 4k pages
--- /dev/null
+/*
+ * Verify the COMMPAGE emulation
+ *
+ * The ARM commpage is a set of user space helper functions provided
+ * by the kernel in an effort to ease portability of user space code
+ * between different CPUs with potentially different capabilities. It
+ * is a 32 bit invention and similar to the vdso segment in many ways.
+ *
+ * The ABI is documented in the Linux kernel:
+ * Documentation/arm/kernel_userspace_helpers.rst
+ *
+ * Copyright (c) 2020 Linaro Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+
+#define ARM_COMMPAGE (0xffff0f00u)
+#define ARM_KUSER_VERSION (*(int32_t *)(ARM_COMMPAGE + 0xfc))
+typedef void * (get_tls_fn)(void);
+#define ARM_KUSER_GET_TLS (*(get_tls_fn *)(ARM_COMMPAGE + 0xe0))
+typedef int (cmpxchg_fn)(int oldval, int newval, volatile int *ptr);
+#define ARM_KUSER_CMPXCHG (*(cmpxchg_fn *)(ARM_COMMPAGE + 0xc0))
+typedef void (dmb_fn)(void);
+#define ARM_KUSER_DMB (*(dmb_fn *)(ARM_COMMPAGE + 0xa0))
+typedef int (cmpxchg64_fn)(const int64_t *oldval,
+ const int64_t *newval,
+ volatile int64_t *ptr);
+#define ARM_KUSER_CMPXCHG64 (*(cmpxchg64_fn *)(ARM_COMMPAGE + 0x60))
+
+#define fail_unless(x) \
+ do { \
+ if (!(x)) { \
+ fprintf(stderr, "FAILED at %s:%d\n", __FILE__, __LINE__); \
+ exit(EXIT_FAILURE); \
+ } \
+ } while (0)
+
+
+int main(int argc, char *argv[argc])
+{
+ void *kuser_tls;
+ int val = 1;
+ const int64_t oldval = 1, newval = 2;
+ int64_t val64 = 1;
+
+ fail_unless(ARM_KUSER_VERSION == 0x5);
+ kuser_tls = ARM_KUSER_GET_TLS();
+ printf("TLS = %p\n", kuser_tls);
+ fail_unless(kuser_tls != 0);
+ fail_unless(ARM_KUSER_CMPXCHG(1, 2, &val) == 0);
+ printf("val = %d\n", val);
+ /* this is a crash test, not checking an actual barrier occurs */
+ ARM_KUSER_DMB();
+ fail_unless(ARM_KUSER_CMPXCHG64(&oldval, &newval, &val64) == 0);
+ printf("val64 = %lld\n", val64);
+ return 0;
+}
pkgs = [
# tools
'git-core',
- 'flex', 'bison',
'gcc', 'binutils', 'make',
# perl
"bash",
"gmake",
"gsed",
- "flex", "bison",
# libs: crypto
"gnutls",
"bash",
"gmake",
"gsed",
- "flex", "bison",
# libs: crypto
"gnutls",
"bash",
"gmake",
"gsed",
- "bison",
# libs: usb
"libusb1",
self.ssh_root_check("sed -ie s/^#\ deb-src/deb-src/g /etc/apt/sources.list")
self.ssh_root_check("apt-get update")
self.ssh_root_check("apt-get build-dep -y qemu")
- self.ssh_root_check("apt-get install -y libfdt-dev flex bison language-pack-en")
+ self.ssh_root_check("apt-get install -y libfdt-dev language-pack-en")
self.ssh_root("poweroff")
self.wait()
os.rename(img_tmp, img)
projects / mirror_qemu.git / commitdiff