drm/amdgpu: fix memory clock can't switch on CI.

if we set only lowest mclk level enabled,
when we enable uvd dpm during boot time,
mclk will be fixed in the lowest level.
the mclk switch will fail if try to enable
other level of mclk at this time.
so set all mclk levels enabled.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 11ccda83d767b0e416667c56e48cb72f1ecb9668..a6dda3470003fe2d130695e8d434a92a90359c0b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -3036,6 +3036,7 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev,
                                                      memory_clock,
                                                      &memory_level->MinVddcPhases);
 
+       memory_level->EnabledForActivity = 1;
        memory_level->EnabledForThrottle = 1;
        memory_level->UpH = 0;
        memory_level->DownH = 100;
@@ -3468,8 +3469,6 @@ static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
                        return ret;
        }
 
-       pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
-
        if ((dpm_table->mclk_table.count >= 2) &&
            ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
                pi->smc_state_table.MemoryLevel[1].MinVddc =