usb: phy: omap-usb3: updated dpll M,N values to support DRA7xx devices

Addition of the M and N recommended values for the USB3 PHY DPLL.
Sysclk for DRA7xx is 20MHz.

This yields:
Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz

Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/usb/phy/phy-omap-usb3.c
index a6e60b1e102e84c070a44e139d8e9ac2b1ff01c7..efe6e1464f45b59fb831a9ca5c05361593b3b7a5 100644 (file)
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/usb/phy/phy-omap-usb3.c
@@ -27,7 +27,7 @@
 #include <linux/delay.h>
 #include <linux/usb/omap_control_usb.h>
 
-#define        NUM_SYS_CLKS            5
+#define        NUM_SYS_CLKS            6
 #define        PLL_STATUS              0x00000004
 #define        PLL_GO                  0x00000008
 #define        PLL_CONFIGURATION1      0x0000000C
@@ -62,6 +62,7 @@ enum sys_clk_rate {
        CLK_RATE_12MHZ,
        CLK_RATE_16MHZ,
        CLK_RATE_19MHZ,
+       CLK_RATE_20MHZ,
        CLK_RATE_26MHZ,
        CLK_RATE_38MHZ
 };
@@ -72,6 +73,8 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
        {1172, 8, 4, 20, 65537},        /* 19.2 MHz */
        {1250, 12, 4, 20, 0},           /* 26 MHz */
        {3125, 47, 4, 20, 92843},       /* 38.4 MHz */
+       {1000, 7, 4, 10, 0},            /* 20 MHz */
+
 };
 
 static int omap_usb3_suspend(struct usb_phy *x, int suspend)
@@ -122,6 +125,8 @@ static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
                return CLK_RATE_16MHZ;
        case 19200000:
                return CLK_RATE_19MHZ;
+       case 20000000:
+               return CLK_RATE_20MHZ;
        case 26000000:
                return CLK_RATE_26MHZ;
        case 38400000: