]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
authorLinus Torvalds <torvalds@linux-foundation.org>
Sat, 20 Jul 2019 00:13:56 +0000 (17:13 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sat, 20 Jul 2019 00:13:56 +0000 (17:13 -0700)
Pull ARM SoC-related driver updates from Olof Johansson:
 "Various driver updates for platforms and a couple of the small driver
  subsystems we merge through our tree:

   - A driver for SCU (system control) on NXP i.MX8QXP

   - Qualcomm Always-on Subsystem messaging driver (AOSS QMP)

   - Qualcomm PM support for MSM8998

   - Support for a newer version of DRAM PHY driver for Broadcom (DPFE)

   - Reset controller support for Bitmain BM1880

   - TI SCI (System Control Interface) support for CPU control on AM654
     processors

   - More TI sysc refactoring and rework"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
  reset: remove redundant null check on pointer dev
  soc: rockchip: work around clang warning
  dt-bindings: reset: imx7: Fix the spelling of 'indices'
  soc: imx: Add i.MX8MN SoC driver support
  soc: aspeed: lpc-ctrl: Fix probe error handling
  soc: qcom: geni: Add support for ACPI
  firmware: ti_sci: Fix gcc unused-but-set-variable warning
  firmware: ti_sci: Use the correct style for SPDX License Identifier
  soc: imx8: Use existing of_root directly
  soc: imx8: Fix potential kernel dump in error path
  firmware/psci: psci_checker: Park kthreads before stopping them
  memory: move jedec_ddr.h from include/memory to drivers/memory/
  memory: move jedec_ddr_data.c from lib/ to drivers/memory/
  MAINTAINERS: Remove myself as qcom maintainer
  soc: aspeed: lpc-ctrl: make parameter optional
  soc: qcom: apr: Don't use reg for domain id
  soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
  memory: tegra: Fix -Wunused-const-variable
  firmware: tegra: Early resume BPMP
  soc/tegra: Select pinctrl for Tegra194
  ...

17 files changed:
1  2 
MAINTAINERS
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/mach-omap2/pdata-quirks.c
drivers/firmware/ti_sci.c
drivers/firmware/ti_sci.h
drivers/memory/Kconfig
drivers/memory/brcmstb_dpfe.c
drivers/memory/emif.c
drivers/memory/jedec_ddr.h
drivers/memory/jedec_ddr_data.c
drivers/memory/tegra/tegra124.c
drivers/soc/imx/soc-imx8.c
drivers/soc/rockchip/pm_domains.c
drivers/soc/tegra/pmc.c
include/linux/soc/ti/ti_sci_protocol.h
lib/Kconfig
lib/Makefile

diff --cc MAINTAINERS
index 9bd4c3b154e85bc174acb79aa39b38dbdc4b0408,78d83690f07e55b36c10a643112fe1145aaf09fd..bd3fe4fe13c4c7d39d93b6864d2512be06c488bf
@@@ -11905,8 -11671,19 +11905,9 @@@ S:  Maintaine
  F:    drivers/mtd/nand/onenand/
  F:    include/linux/mtd/onenand*.h
  
 -ONSTREAM SCSI TAPE DRIVER
 -M:    Willem Riede <osst@riede.org>
 -L:    osst-users@lists.sourceforge.net
 -L:    linux-scsi@vger.kernel.org
 -S:    Maintained
 -F:    Documentation/scsi/osst.txt
 -F:    drivers/scsi/osst.*
 -F:    drivers/scsi/osst_*.h
 -F:    drivers/scsi/st.h
 -
  OP-TEE DRIVER
  M:    Jens Wiklander <jens.wiklander@linaro.org>
+ L:    tee-dev@lists.linaro.org
  S:    Maintained
  F:    drivers/tee/optee/
  
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index 0000000000000000000000000000000000000000,a2094a9a588efb9bed66a1ed65c66590c03b42de..4a21b5044ff88898169b8201bddfa7b7bb126b6d
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,175 +1,172 @@@
 - *
 - * This program is free software; you can redistribute it and/or modify
 - * it under the terms of the GNU General Public License version 2 as
 - * published by the Free Software Foundation.
++/* SPDX-License-Identifier: GPL-2.0-only */
+ /*
+  * Definitions for DDR memories based on JEDEC specs
+  *
+  * Copyright (C) 2012 Texas Instruments, Inc.
+  *
+  * Aneesh V <aneesh@ti.com>
+  */
+ #ifndef __JEDEC_DDR_H
+ #define __JEDEC_DDR_H
+ #include <linux/types.h>
+ /* DDR Densities */
+ #define DDR_DENSITY_64Mb      1
+ #define DDR_DENSITY_128Mb     2
+ #define DDR_DENSITY_256Mb     3
+ #define DDR_DENSITY_512Mb     4
+ #define DDR_DENSITY_1Gb               5
+ #define DDR_DENSITY_2Gb               6
+ #define DDR_DENSITY_4Gb               7
+ #define DDR_DENSITY_8Gb               8
+ #define DDR_DENSITY_16Gb      9
+ #define DDR_DENSITY_32Gb      10
+ /* DDR type */
+ #define DDR_TYPE_DDR2         1
+ #define DDR_TYPE_DDR3         2
+ #define DDR_TYPE_LPDDR2_S4    3
+ #define DDR_TYPE_LPDDR2_S2    4
+ #define DDR_TYPE_LPDDR2_NVM   5
+ /* DDR IO width */
+ #define DDR_IO_WIDTH_4                1
+ #define DDR_IO_WIDTH_8                2
+ #define DDR_IO_WIDTH_16               3
+ #define DDR_IO_WIDTH_32               4
+ /* Number of Row bits */
+ #define R9                    9
+ #define R10                   10
+ #define R11                   11
+ #define R12                   12
+ #define R13                   13
+ #define R14                   14
+ #define R15                   15
+ #define R16                   16
+ /* Number of Column bits */
+ #define C7                    7
+ #define C8                    8
+ #define C9                    9
+ #define C10                   10
+ #define C11                   11
+ #define C12                   12
+ /* Number of Banks */
+ #define B1                    0
+ #define B2                    1
+ #define B4                    2
+ #define B8                    3
+ /* Refresh rate in nano-seconds */
+ #define T_REFI_15_6           15600
+ #define T_REFI_7_8            7800
+ #define T_REFI_3_9            3900
+ /* tRFC values */
+ #define T_RFC_90              90000
+ #define T_RFC_110             110000
+ #define T_RFC_130             130000
+ #define T_RFC_160             160000
+ #define T_RFC_210             210000
+ #define T_RFC_300             300000
+ #define T_RFC_350             350000
+ /* Mode register numbers */
+ #define DDR_MR0                       0
+ #define DDR_MR1                       1
+ #define DDR_MR2                       2
+ #define DDR_MR3                       3
+ #define DDR_MR4                       4
+ #define DDR_MR5                       5
+ #define DDR_MR6                       6
+ #define DDR_MR7                       7
+ #define DDR_MR8                       8
+ #define DDR_MR9                       9
+ #define DDR_MR10              10
+ #define DDR_MR11              11
+ #define DDR_MR16              16
+ #define DDR_MR17              17
+ #define DDR_MR18              18
+ /*
+  * LPDDR2 related defines
+  */
+ /* MR4 register fields */
+ #define MR4_SDRAM_REF_RATE_SHIFT                      0
+ #define MR4_SDRAM_REF_RATE_MASK                               7
+ #define MR4_TUF_SHIFT                                 7
+ #define MR4_TUF_MASK                                  (1 << 7)
+ /* MR4 SDRAM Refresh Rate field values */
+ #define SDRAM_TEMP_NOMINAL                            0x3
+ #define SDRAM_TEMP_RESERVED_4                         0x4
+ #define SDRAM_TEMP_HIGH_DERATE_REFRESH                        0x5
+ #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS    0x6
+ #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN                 0x7
+ #define NUM_DDR_ADDR_TABLE_ENTRIES                    11
+ #define NUM_DDR_TIMING_TABLE_ENTRIES                  4
+ /* Structure for DDR addressing info from the JEDEC spec */
+ struct lpddr2_addressing {
+       u32 num_banks;
+       u32 tREFI_ns;
+       u32 tRFCab_ps;
+ };
+ /*
+  * Structure for timings from the LPDDR2 datasheet
+  * All parameters are in pico seconds(ps) unless explicitly indicated
+  * with a suffix like tRAS_max_ns below
+  */
+ struct lpddr2_timings {
+       u32 max_freq;
+       u32 min_freq;
+       u32 tRPab;
+       u32 tRCD;
+       u32 tWR;
+       u32 tRAS_min;
+       u32 tRRD;
+       u32 tWTR;
+       u32 tXP;
+       u32 tRTP;
+       u32 tCKESR;
+       u32 tDQSCK_max;
+       u32 tDQSCK_max_derated;
+       u32 tFAW;
+       u32 tZQCS;
+       u32 tZQCL;
+       u32 tZQinit;
+       u32 tRAS_max_ns;
+ };
+ /*
+  * Min value for some parameters in terms of number of tCK cycles(nCK)
+  * Please set to zero parameters that are not valid for a given memory
+  * type
+  */
+ struct lpddr2_min_tck {
+       u32 tRPab;
+       u32 tRCD;
+       u32 tWR;
+       u32 tRASmin;
+       u32 tRRD;
+       u32 tWTR;
+       u32 tXP;
+       u32 tRTP;
+       u32 tCKE;
+       u32 tCKESR;
+       u32 tFAW;
+ };
+ extern const struct lpddr2_addressing
+       lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
+ extern const struct lpddr2_timings
+       lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
+ extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
+ #endif /* __JEDEC_DDR_H */
index 0000000000000000000000000000000000000000,1f9ca0f23407aa534060f8aeb65821fee21aacfd..ed601d813175e7c723c2022932cc9431b13907ec
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,136 +1,133 @@@
 - *
 - * This program is free software; you can redistribute it and/or modify
 - * it under the terms of the GNU General Public License version 2 as
 - * published by the Free Software Foundation.
++// SPDX-License-Identifier: GPL-2.0-only
+ /*
+  * DDR addressing details and AC timing parameters from JEDEC specs
+  *
+  * Copyright (C) 2012 Texas Instruments, Inc.
+  *
+  * Aneesh V <aneesh@ti.com>
+  */
+ #include <linux/export.h>
+ #include "jedec_ddr.h"
+ /* LPDDR2 addressing details from JESD209-2 section 2.4 */
+ const struct lpddr2_addressing
+       lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
+       {B4, T_REFI_15_6, T_RFC_90}, /* 64M */
+       {B4, T_REFI_15_6, T_RFC_90}, /* 128M */
+       {B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
+       {B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
+       {B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
+       {B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
+       {B8, T_REFI_3_9, T_RFC_130}, /* 4G */
+       {B8, T_REFI_3_9, T_RFC_210}, /* 8G */
+       {B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
+       {B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
+ };
+ EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
+ /* LPDDR2 AC timing parameters from JESD209-2 section 12 */
+ const struct lpddr2_timings
+       lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
+       /* Speed bin 400(200 MHz) */
+       [0] = {
+               .max_freq       = 200000000,
+               .min_freq       = 10000000,
+               .tRPab          = 21000,
+               .tRCD           = 18000,
+               .tWR            = 15000,
+               .tRAS_min       = 42000,
+               .tRRD           = 10000,
+               .tWTR           = 10000,
+               .tXP            = 7500,
+               .tRTP           = 7500,
+               .tCKESR         = 15000,
+               .tDQSCK_max     = 5500,
+               .tFAW           = 50000,
+               .tZQCS          = 90000,
+               .tZQCL          = 360000,
+               .tZQinit        = 1000000,
+               .tRAS_max_ns    = 70000,
+               .tDQSCK_max_derated = 6000,
+       },
+       /* Speed bin 533(266 MHz) */
+       [1] = {
+               .max_freq       = 266666666,
+               .min_freq       = 10000000,
+               .tRPab          = 21000,
+               .tRCD           = 18000,
+               .tWR            = 15000,
+               .tRAS_min       = 42000,
+               .tRRD           = 10000,
+               .tWTR           = 7500,
+               .tXP            = 7500,
+               .tRTP           = 7500,
+               .tCKESR         = 15000,
+               .tDQSCK_max     = 5500,
+               .tFAW           = 50000,
+               .tZQCS          = 90000,
+               .tZQCL          = 360000,
+               .tZQinit        = 1000000,
+               .tRAS_max_ns    = 70000,
+               .tDQSCK_max_derated = 6000,
+       },
+       /* Speed bin 800(400 MHz) */
+       [2] = {
+               .max_freq       = 400000000,
+               .min_freq       = 10000000,
+               .tRPab          = 21000,
+               .tRCD           = 18000,
+               .tWR            = 15000,
+               .tRAS_min       = 42000,
+               .tRRD           = 10000,
+               .tWTR           = 7500,
+               .tXP            = 7500,
+               .tRTP           = 7500,
+               .tCKESR         = 15000,
+               .tDQSCK_max     = 5500,
+               .tFAW           = 50000,
+               .tZQCS          = 90000,
+               .tZQCL          = 360000,
+               .tZQinit        = 1000000,
+               .tRAS_max_ns    = 70000,
+               .tDQSCK_max_derated = 6000,
+       },
+       /* Speed bin 1066(533 MHz) */
+       [3] = {
+               .max_freq       = 533333333,
+               .min_freq       = 10000000,
+               .tRPab          = 21000,
+               .tRCD           = 18000,
+               .tWR            = 15000,
+               .tRAS_min       = 42000,
+               .tRRD           = 10000,
+               .tWTR           = 7500,
+               .tXP            = 7500,
+               .tRTP           = 7500,
+               .tCKESR         = 15000,
+               .tDQSCK_max     = 5500,
+               .tFAW           = 50000,
+               .tZQCS          = 90000,
+               .tZQCL          = 360000,
+               .tZQinit        = 1000000,
+               .tRAS_max_ns    = 70000,
+               .tDQSCK_max_derated = 5620,
+       },
+ };
+ EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
+ const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
+       .tRPab          = 3,
+       .tRCD           = 3,
+       .tWR            = 3,
+       .tRASmin        = 3,
+       .tRRD           = 2,
+       .tWTR           = 2,
+       .tXP            = 2,
+       .tRTP           = 2,
+       .tCKE           = 3,
+       .tCKESR         = 3,
+       .tFAW           = 8
+ };
+ EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
Simple merge
index b1bd8e2543ac529b1c581c4617e192bf89bca1a0,9fb5293469f8ba19a117d3e722d06932d04b0f6b..f924ae8c65141a6d968e200b075123380a72a256
@@@ -96,16 -129,17 +129,20 @@@ static int __init imx8_soc_init(void
        }
  
        soc_dev_attr->revision = imx8_revision(soc_rev);
-       if (!soc_dev_attr->revision)
+       if (!soc_dev_attr->revision) {
+               ret = -ENOMEM;
                goto free_soc;
+       }
  
        soc_dev = soc_device_register(soc_dev_attr);
-       if (IS_ERR(soc_dev))
+       if (IS_ERR(soc_dev)) {
+               ret = PTR_ERR(soc_dev);
                goto free_rev;
+       }
  
 +      if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
 +              platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
 +
        return 0;
  
  free_rev:
Simple merge
Simple merge
diff --cc lib/Kconfig
Simple merge
diff --cc lib/Makefile
Simple merge