drm/i915: DSL_LINEMASK is 12 bits only on gen2

Gen3+ is 13 bits (12:0), and on gen2 only 12 (11:0). For both the high
bits are marked reserved, read-only so continue to mask them. Bit 31
is not reserved and has a meaning.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10e71a9f8bd9de612119c5d71f2df3d3ac8ec264..833052ef7cf5b9cf787308783642de8058ed6bf1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2476,7 +2476,8 @@
 
 /* Pipe A */
 #define _PIPEADSL              0x70000
-#define   DSL_LINEMASK         0x00000fff
+#define   DSL_LINEMASK_GEN2    0x00000fff
+#define   DSL_LINEMASK_GEN3    0x00001fff
 #define _PIPEACONF             0x70008
 #define   PIPECONF_ENABLE      (1<<31)
 #define   PIPECONF_DISABLE     0

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6b4139064f9c48d0de9b8e799553347b8c581417..83b785f400fe060c9b9f15425695000d871e8990 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -849,15 +849,20 @@ void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
                             100))
                        DRM_DEBUG_KMS("pipe_off wait timed out\n");
        } else {
-               u32 last_line;
+               u32 last_line, line_mask;
                int reg = PIPEDSL(pipe);
                unsigned long timeout = jiffies + msecs_to_jiffies(100);
 
+               if (IS_GEN2(dev))
+                       line_mask = DSL_LINEMASK_GEN2;
+               else
+                       line_mask = DSL_LINEMASK_GEN3;
+
                /* Wait for the display line to settle */
                do {
-                       last_line = I915_READ(reg) & DSL_LINEMASK;
+                       last_line = I915_READ(reg) & line_mask;
                        mdelay(5);
-               } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
+               } while (((I915_READ(reg) & line_mask) != last_line) &&
                         time_after(timeout, jiffies));
                if (time_after(jiffies, timeout))
                        DRM_DEBUG_KMS("pipe_off wait timed out\n");