phy: qcom-qmp: qserdes-txrx: Add missing registers offsets

BugLink: https://bugs.launchpad.net/bugs/2075154
[ Upstream commit 5314e84c33e7ad61df5203df540626ac59f9dcd9 ]

Currently, the x1e80100 uses pure V6 register offsets for DP part of the
combo PHY. This hasn't been an issue because external DP is not yet
enabled on any of the boards yet. But in order to enabled it, all these
new V6 N4 register offsets are needed. So add them.

Fixes: 762c3565f3c8 ("phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets")
Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-1-be8a0b882117@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Manuel Diewald <manuel.diewald@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h
index a814ad11af071b187c8c9b13054f506dccf1aa81..d37cc0d4fd365c78b599ccc2e8fc3b1a1186dca4 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h
@@ -6,11 +6,24 @@
 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
 #define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
 
+#define QSERDES_V6_N4_TX_CLKBUF_ENABLE                 0x08
+#define QSERDES_V6_N4_TX_TX_EMP_POST1_LVL              0x0c
+#define QSERDES_V6_N4_TX_TX_DRV_LVL                    0x14
+#define QSERDES_V6_N4_TX_RESET_TSYNC_EN                        0x1c
+#define QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN                0x20
 #define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX       0x30
 #define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX       0x34
+#define QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN           0x48
+#define QSERDES_V6_N4_TX_HIGHZ_DRVR_EN                 0x4c
+#define QSERDES_V6_N4_TX_TX_POL_INV                    0x50
+#define QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN    0x54
 #define QSERDES_V6_N4_TX_LANE_MODE_1                   0x78
 #define QSERDES_V6_N4_TX_LANE_MODE_2                   0x7c
 #define QSERDES_V6_N4_TX_LANE_MODE_3                   0x80
+#define QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN              0xac
+#define QSERDES_V6_N4_TX_TX_BAND                       0xd8
+#define QSERDES_V6_N4_TX_INTERFACE_SELECT              0xe4
+#define QSERDES_V6_N4_TX_VMODE_CTRL1                   0xb0
 
 #define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2            0x8
 #define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2            0x18