]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
net: mvpp2: populate supported_interfaces member
authorRussell King <rmk+kernel@armlinux.org.uk>
Wed, 27 Oct 2021 09:49:14 +0000 (10:49 +0100)
committerDavid S. Miller <davem@davemloft.net>
Thu, 28 Oct 2021 11:55:44 +0000 (12:55 +0100)
Populate the phy interface mode bitmap for the Marvell mvpp2 driver
with interfaces modes supported by the MAC.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

index 8ddf58f379ac29561fd62da1fc664f4ffb6f9238..43ffff01bd444b34ce4b65a0c8606d33e8f99cfa 100644 (file)
@@ -6937,6 +6937,40 @@ static int mvpp2_port_probe(struct platform_device *pdev,
                port->phylink_config.dev = &dev->dev;
                port->phylink_config.type = PHYLINK_NETDEV;
 
+               if (mvpp2_port_supports_xlg(port)) {
+                       __set_bit(PHY_INTERFACE_MODE_10GBASER,
+                                 port->phylink_config.supported_interfaces);
+                       __set_bit(PHY_INTERFACE_MODE_XAUI,
+                                 port->phylink_config.supported_interfaces);
+               }
+
+               if (mvpp2_port_supports_rgmii(port))
+                       phy_interface_set_rgmii(port->phylink_config.supported_interfaces);
+
+               if (comphy) {
+                       /* If a COMPHY is present, we can support any of the
+                        * serdes modes and switch between them.
+                        */
+                       __set_bit(PHY_INTERFACE_MODE_SGMII,
+                                 port->phylink_config.supported_interfaces);
+                       __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+                                 port->phylink_config.supported_interfaces);
+                       __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+                                 port->phylink_config.supported_interfaces);
+               } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
+                       /* No COMPHY, with only 2500BASE-X mode supported */
+                       __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+                                 port->phylink_config.supported_interfaces);
+               } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
+                          phy_mode == PHY_INTERFACE_MODE_SGMII) {
+                       /* No COMPHY, we can switch between 1000BASE-X and SGMII
+                        */
+                       __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+                                 port->phylink_config.supported_interfaces);
+                       __set_bit(PHY_INTERFACE_MODE_SGMII,
+                                 port->phylink_config.supported_interfaces);
+               }
+
                phylink = phylink_create(&port->phylink_config, port_fwnode,
                                         phy_mode, &mvpp2_phylink_ops);
                if (IS_ERR(phylink)) {