iio: accel: adxl345: convert address field usage in iio_chan_spec

BugLink: https://bugs.launchpad.net/bugs/1836287
[ Upstream commit 9048f1f18a70a01eaa3c8e7166fdb2538929d780 ]

Currently the address field in iio_chan_spec is filled with an accel
data register address for the corresponding axis.

In preparation for adding calibration offset support, this sets the
address field to the index of accel data registers instead of the actual
register address.

This change makes it easier to access both accel registers and
calibration offset registers with fewer lines of code as these are
located in X-axis, Y-axis, Z-axis order.

Cc: Eva Rachel Retuya <eraretuya@gmail.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c
index 7251d0e63d744b10070e14c2b593eb96b3f7e8b7..98080e05ac6d16c2b05b8b63eea62fcb9f5b7a07 100644 (file)
--- a/drivers/iio/accel/adxl345_core.c
+++ b/drivers/iio/accel/adxl345_core.c
@@ -21,6 +21,8 @@
 #define ADXL345_REG_DATAX0             0x32
 #define ADXL345_REG_DATAY0             0x34
 #define ADXL345_REG_DATAZ0             0x36
+#define ADXL345_REG_DATA_AXIS(index)   \
+       (ADXL345_REG_DATAX0 + (index) * sizeof(__le16))
 
 #define ADXL345_POWER_CTL_MEASURE      BIT(3)
 #define ADXL345_POWER_CTL_STANDBY      0x00
@@ -47,19 +49,19 @@ struct adxl345_data {
        u8 data_range;
 };
 
-#define ADXL345_CHANNEL(reg, axis) {                                   \
+#define ADXL345_CHANNEL(index, axis) {                                 \
        .type = IIO_ACCEL,                                              \
        .modified = 1,                                                  \
        .channel2 = IIO_MOD_##axis,                                     \
-       .address = reg,                                                 \
+       .address = index,                                               \
        .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
        .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),           \
 }
 
 static const struct iio_chan_spec adxl345_channels[] = {
-       ADXL345_CHANNEL(ADXL345_REG_DATAX0, X),
-       ADXL345_CHANNEL(ADXL345_REG_DATAY0, Y),
-       ADXL345_CHANNEL(ADXL345_REG_DATAZ0, Z),
+       ADXL345_CHANNEL(0, X),
+       ADXL345_CHANNEL(1, Y),
+       ADXL345_CHANNEL(2, Z),
 };
 
 static int adxl345_read_raw(struct iio_dev *indio_dev,
@@ -67,7 +69,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
                            int *val, int *val2, long mask)
 {
        struct adxl345_data *data = iio_priv(indio_dev);
-       __le16 regval;
+       __le16 accel;
        int ret;
 
        switch (mask) {
@@ -77,12 +79,13 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
                 * ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte
                 * and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte
                 */
-               ret = regmap_bulk_read(data->regmap, chan->address, &regval,
-                                      sizeof(regval));
+               ret = regmap_bulk_read(data->regmap,
+                                      ADXL345_REG_DATA_AXIS(chan->address),
+                                      &accel, sizeof(accel));
                if (ret < 0)
                        return ret;
 
-               *val = sign_extend32(le16_to_cpu(regval), 12);
+               *val = sign_extend32(le16_to_cpu(accel), 12);
                return IIO_VAL_INT;
        case IIO_CHAN_INFO_SCALE:
                *val = 0;