PCI: aardvark: Do not unmask unused interrupts

BugLink: https://bugs.launchpad.net/bugs/1953387
commit 1fb95d7d3c7a926b002fe8a6bd27a1cb428b46dc upstream.

There are lot of undocumented interrupt bits. To prevent unwanted
spurious interrupts, fix all *_ALL_MASK macros to define all interrupt
bits, so that driver can properly mask all interrupts, including those
which are undocumented.

Link: https://lore.kernel.org/r/20211005180952.6812-8-kabel@kernel.org
Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Kelsey Skunberg <kelsey.skunberg@canonical.com>

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index a5b0a952ee6d2a0d8d4aeaf7b8d0a694b3f53f40..88be131fd22dbb7bcc9473114e0c3338823391ce 100644 (file)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -108,13 +108,13 @@
 #define     PCIE_ISR0_MSI_INT_PENDING          BIT(24)
 #define     PCIE_ISR0_INTX_ASSERT(val)         BIT(16 + (val))
 #define     PCIE_ISR0_INTX_DEASSERT(val)       BIT(20 + (val))
-#define            PCIE_ISR0_ALL_MASK                  GENMASK(26, 0)
+#define     PCIE_ISR0_ALL_MASK                 GENMASK(31, 0)
 #define PCIE_ISR1_REG                          (CONTROL_BASE_ADDR + 0x48)
 #define PCIE_ISR1_MASK_REG                     (CONTROL_BASE_ADDR + 0x4C)
 #define     PCIE_ISR1_POWER_STATE_CHANGE       BIT(4)
 #define     PCIE_ISR1_FLUSH                    BIT(5)
 #define     PCIE_ISR1_INTX_ASSERT(val)         BIT(8 + (val))
-#define     PCIE_ISR1_ALL_MASK                 GENMASK(11, 4)
+#define     PCIE_ISR1_ALL_MASK                 GENMASK(31, 0)
 #define PCIE_MSI_ADDR_LOW_REG                  (CONTROL_BASE_ADDR + 0x50)
 #define PCIE_MSI_ADDR_HIGH_REG                 (CONTROL_BASE_ADDR + 0x54)
 #define PCIE_MSI_STATUS_REG                    (CONTROL_BASE_ADDR + 0x58)
@@ -202,7 +202,7 @@ enum {
 #define     PCIE_IRQ_MSI_INT2_DET              BIT(21)
 #define     PCIE_IRQ_RC_DBELL_DET              BIT(22)
 #define     PCIE_IRQ_EP_STATUS                 BIT(23)
-#define     PCIE_IRQ_ALL_MASK                  0xfff0fb
+#define     PCIE_IRQ_ALL_MASK                  GENMASK(31, 0)
 #define     PCIE_IRQ_ENABLE_INTS_MASK          PCIE_IRQ_CORE_INT
 
 /* Transaction types */