clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider

The clock was missing CLK_SET_RATE_PARENT flag, which caused rate
setting failures due to inability of reconfiguration of second
divider behind it.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index ad5ff50c5f281a5e1c31c498c78c5a717aa464de..d967571d305ee6d32f80d32ec401fb86fb50d7e8 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -530,7 +530,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
        DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
        DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
        DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
-       DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
+       DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
+                       CLK_SET_RATE_PARENT, 0),
        DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
        DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
        DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),