drm/i915/tgl: Add Wa_22010178259:tgl

We need to explicitly set the TLB Request Timer initial value in the
BW_BUDDY registers to 0x8 rather than relying on the hardware default.

v2: Apply missing REG_FIELD_PREP to ensure 0x8 is placed in the correct
    bits during the rmw.  (Jose)

Bspec: 52890
Bspec: 50044
Fixes: 3fa01d642fa7 ("drm/i915/tgl: Program BW_BUDDY registers during display init")
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200219215655.2923650-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0d94fe01be7fbc028a2c4ab279e4e5b89e26052f..8ba68ec6dc245df9e108455e510057316564a7f0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5003,6 +5003,14 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
                               table[i].page_mask);
                intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
                               table[i].page_mask);
+
+               /* Wa_22010178259:tgl */
+               intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
+                            BW_BUDDY_TLB_REQ_TIMER_MASK,
+                            REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
+               intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
+                            BW_BUDDY_TLB_REQ_TIMER_MASK,
+                            REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
        }
 }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4acb6deaf97dcfd920436612160e12299588ce54..f45b5e86ec63e4b48b4916ba0a7d6ba28369285f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7767,6 +7767,7 @@ enum {
 #define BW_BUDDY1_CTL                  _MMIO(0x45140)
 #define BW_BUDDY2_CTL                  _MMIO(0x45150)
 #define   BW_BUDDY_DISABLE             REG_BIT(31)
+#define   BW_BUDDY_TLB_REQ_TIMER_MASK  REG_GENMASK(21, 16)
 
 #define BW_BUDDY1_PAGE_MASK            _MMIO(0x45144)
 #define BW_BUDDY2_PAGE_MASK            _MMIO(0x45154)