drm/amdgpu/gfx8: implement emit_rreg/wreg function

Implement emit_rreg/wreg function for kiq ring.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index fa1d569ec479fbbdf324fa75f80066dd5f304249..70ab72cd8fae53adf26830449221e9c3dd3f184a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -34,6 +34,7 @@ struct amdgpu_virt {
        uint32_t caps;
        struct amdgpu_bo *csa_obj;
        uint64_t csa_vmid0_addr;
+       uint32_t                reg_val_offs;
 };
 
 #define AMDGPU_CSA_SIZE    (8 * 1024)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 0907173d9681c24d11ac6a2206527849bb1b2a0a..aa053f628786e00104dcc34f037ea545d35fefe6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1373,6 +1373,12 @@ static int gfx_v8_0_kiq_init_ring(struct amdgpu_device *adev,
 {
        int r = 0;
 
+       if (amdgpu_sriov_vf(adev)) {
+               r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
+               if (r)
+                       return r;
+       }
+
        ring->adev = NULL;
        ring->ring_obj = NULL;
        ring->use_doorbell = true;
@@ -1399,6 +1405,9 @@ static int gfx_v8_0_kiq_init_ring(struct amdgpu_device *adev,
 static void gfx_v8_0_kiq_free_ring(struct amdgpu_ring *ring,
                                   struct amdgpu_irq_src *irq)
 {
+       if (amdgpu_sriov_vf(ring->adev))
+               amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
+
        amdgpu_ring_fini(ring);
        irq->data = NULL;
 }
@@ -6720,6 +6729,32 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
        amdgpu_ring_write(ring, 0);
 }
 
+static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
+{
+       struct amdgpu_device *adev = ring->adev;
+
+       amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
+       amdgpu_ring_write(ring, 0 |     /* src: register*/
+                               (5 << 8) |      /* dst: memory */
+                               (1 << 20));     /* write confirm */
+       amdgpu_ring_write(ring, reg);
+       amdgpu_ring_write(ring, 0);
+       amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
+                               adev->virt.reg_val_offs * 4));
+       amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
+                               adev->virt.reg_val_offs * 4));
+}
+
+static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
+                                 uint32_t val)
+{
+       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+       amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
+       amdgpu_ring_write(ring, reg);
+       amdgpu_ring_write(ring, 0);
+       amdgpu_ring_write(ring, val);
+}
+
 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
                                                 enum amdgpu_interrupt_state state)
 {
@@ -7035,6 +7070,8 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
        .test_ib = gfx_v8_0_ring_test_ib,
        .insert_nop = amdgpu_ring_insert_nop,
        .pad_ib = amdgpu_ring_generic_pad_ib,
+       .emit_rreg = gfx_v8_0_ring_emit_rreg,
+       .emit_wreg = gfx_v8_0_ring_emit_wreg,
 };
 
 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)