A missing call to qemu_set_irq() when reading the IRQ register
required SW to write to the IRQ register to acknowledge an
interrupt. With this patch the behavior is fixed:
- Reading the interrupt register clears it and updates the timers
interrupt status
- Writes to the interrupt register are ignored
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
/* cleared after read */
value = s->reg_intr;
s->reg_intr = 0;
+ cadence_timer_update(s);
return value;
case 0x60: /* interrupt enable */
case 0x54: /* interrupt register */
case 0x58:
case 0x5c:
- s->reg_intr &= (~value & 0xfff);
break;
case 0x60: /* interrupt enable */