clk: meson: gxbb: no spread spectrum on mpll0

The documentation says there is an SSEN bit on mpll0 but, after testing
it, no spread spectrum function appears to be enabled by this bit on any
of the MPLLs.

Let's remove it until we know more

Fixes: 1f737ffa13ef ("clk: meson: mpll: fix mpll0 fractional part ignored")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 29ffb4fde7145adefe855c11283825e1e4ea1f11..dab16d9b1af8b442eed369771e38117c06f48864 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -679,11 +679,6 @@ static struct clk_regmap gxbb_mpll0_div = {
                        .shift   = 16,
                        .width   = 9,
                },
-               .ssen = {
-                       .reg_off = HHI_MPLL_CNTL,
-                       .shift   = 25,
-                       .width   = 1,
-               },
                .lock = &meson_clk_lock,
        },
        .hw.init = &(struct clk_init_data){