arm64: dts: rockchip: Enable PCIe controller on quartz64-a

Add the nodes to enable the PCIe controller on the Quartz64 Model A
board.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20220429123832.2376381-6-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index a02ac75916f40fda6138ee5c713f65227541cdf6..619fd536d90aa84809423a3f04e9e2ad8d4d6276 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -127,6 +127,18 @@
                vin-supply = <&vcc12v_dcin>;
        };
 
+       vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pcie_enable_h>;
+               regulator-name = "vcc3v3_pcie_p";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&vcc_3v3>;
+       };
+
        vcc5v0_usb: vcc5v0_usb {
                compatible = "regulator-fixed";
                regulator-name = "vcc5v0_usb";
@@ -203,6 +215,10 @@
        status = "okay";
 };
 
+&combphy2 {
+       status = "okay";
+};
+
 &cpu0 {
        cpu-supply = <&vdd_cpu>;
 };
@@ -511,6 +527,14 @@
        };
 };
 
+&pcie2x1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_reset_h>;
+       reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+       vpcie3v3-supply = <&vcc3v3_pcie_p>;
+       status = "okay";
+};
+
 &pinctrl {
        bt {
                bt_enable_h: bt-enable-h {
@@ -542,6 +566,16 @@
                };
        };
 
+       pcie {
+               pcie_enable_h: pcie-enable-h {
+                       rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               pcie_reset_h: pcie-reset-h {
+                       rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
        pmic {
                pmic_int_l: pmic-int-l {
                        rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;