}
}
+static void xilinx_axidma_reset(DeviceState *dev)
+{
+ int i;
+ XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
+
+ for (i = 0; i < 2; i++) {
+ stream_reset(&s->streams[i]);
+ }
+}
+
static void
axidma_push(StreamSlave *obj, unsigned char *buf, size_t len, uint32_t *app)
{
sysbus_init_mmio(dev, &s->iomem);
for (i = 0; i < 2; i++) {
- stream_reset(&s->streams[i]);
s->streams[i].nr = i;
s->streams[i].bh = qemu_bh_new(timer_hit, &s->streams[i]);
s->streams[i].ptimer = ptimer_init(s->streams[i].bh);
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
k->init = xilinx_axidma_init;
+ dc->reset = xilinx_axidma_reset;
dc->props = axidma_properties;
ssc->push = axidma_push;
}