PCI: aardvark: Replace custom macros by standard linux/pci_regs.h macros

BugLink: https://bugs.launchpad.net/bugs/1956380
commit 96be36dbffacea0aa9e6ec4839583e79faa141a1 upstream.

PCI-E capability macros are already defined in linux/pci_regs.h.
Remove their reimplementation in pcie-aardvark.

Link: https://lore.kernel.org/r/20200430080625.26070-9-pali@kernel.org
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 1b16256ba69676477b557276bd2316f4e15ded84..97ad321cfc7cdce40795079fc1b0d97d35a450c9 100644 (file)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -32,17 +32,6 @@
 #define     PCIE_CORE_CMD_MEM_IO_REQ_EN                                BIT(2)
 #define PCIE_CORE_DEV_REV_REG                                  0x8
 #define PCIE_CORE_PCIEXP_CAP                                   0xc0
-#define PCIE_CORE_DEV_CTRL_STATS_REG                           0xc8
-#define     PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE       (0 << 4)
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT      5
-#define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE             (0 << 11)
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT     12
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ             0x2
-#define PCIE_CORE_LINK_CTRL_STAT_REG                           0xd0
-#define     PCIE_CORE_LINK_L0S_ENTRY                           BIT(0)
-#define     PCIE_CORE_LINK_TRAINING                            BIT(5)
-#define     PCIE_CORE_LINK_SPEED_SHIFT                         16
-#define     PCIE_CORE_LINK_WIDTH_SHIFT                         20
 #define PCIE_CORE_ERR_CAPCTL_REG                               0x118
 #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX                   BIT(5)
 #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN                        BIT(6)
@@ -267,6 +256,11 @@ static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
        return readl(pcie->base + reg);
 }
 
+static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg)
+{
+       return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8);
+}
+
 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie)
 {
        u32 val;
@@ -366,16 +360,16 @@ static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen)
         * Start link training immediately after enabling it.
         * This solves problems for some buggy cards.
         */
-       reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
-       reg |= PCIE_CORE_LINK_TRAINING;
-       advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
+       reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL);
+       reg |= PCI_EXP_LNKCTL_RL;
+       advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL);
 
        ret = advk_pcie_wait_for_link(pcie);
        if (ret)
                return ret;
 
-       reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
-       neg_gen = (reg >> PCIE_CORE_LINK_SPEED_SHIFT) & 0xf;
+       reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA);
+       neg_gen = reg & PCI_EXP_LNKSTA_CLS;
 
        return neg_gen;
 }
@@ -470,13 +464,14 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
                PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
        advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
 
-       /* Set PCIe Device Control and Status 1 PF0 register */
-       reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
-               (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
-               PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
-               (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
-                PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
-       advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
+       /* Set PCIe Device Control register */
+       reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
+       reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
+       reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
+       reg &= ~PCI_EXP_DEVCTL_READRQ;
+       reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */
+       reg |= PCI_EXP_DEVCTL_READRQ_512B;
+       advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
 
        /* Program PCIe Control 2 to disable strict ordering */
        reg = PCIE_CORE_CTRL2_RESERVED |