ARM: dts: Configure interconnect target module for dra7 sata

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.

Note that the old sysc register offset is wrong, the real offset is at
0x1100 as listed in TRM for SATA_SYSCONFIG register. Looks like we've been
happily using sata on the bootloader configured sysconfig register and
nobody noticed. Also the old register range for SATAMAC_wrapper registers
is wrong at 7 while it should be 8. But that too seems harmless.

There is also an L3 parent interconnect range that we don't seem to be
using. That can be added as needed later on.

Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 3bf90d9e33353b366d826b876d0b40101ad01e36..2c5c682a15ee86f833236c11f75876901864f3eb 100644 (file)
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -572,11 +572,34 @@
                };
 
                target-module@40000 {                   /* 0x4a140000, ap 31 06.0 */
-                       compatible = "ti,sysc";
-                       status = "disabled";
-                       #address-cells = <1>;
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       ti,hwmods = "sata";
+                       reg = <0x400fc 4>,
+                             <0x41100 4>;
+                       reg-names = "rev", "sysc";
+                       ti,sysc-midle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       power-domains = <&prm_l3init>;
+                       clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>;
+                       clock-names = "fck";
                        #size-cells = <1>;
+                       #address-cells = <1>;
                        ranges = <0x0 0x40000 0x10000>;
+
+                       sata: sata@0 {
+                               compatible = "snps,dwc-ahci";
+                               reg = <0 0x1100>, <0x1100 0x8>;
+                               interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&sata_phy>;
+                               phy-names = "sata-phy";
+                               clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
+                               ports-implemented = <0x1>;
+                       };
                };
 
                target-module@51000 {                   /* 0x4a151000, ap 33 50.0 */

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 91d5763b09f41de23cd69560e6d971ff23daf56f..e9f3435521eea10663965a074024d331a838966e 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -785,18 +785,6 @@
                        };
                };
 
-               /* OCP2SCP3 */
-               sata: sata@4a141100 {
-                       compatible = "snps,dwc-ahci";
-                       reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
-                       interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-                       phys = <&sata_phy>;
-                       phy-names = "sata-phy";
-                       clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
-                       ti,hwmods = "sata";
-                       ports-implemented = <0x1>;
-               };
-
                /* OCP2SCP1 */
                /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */