ARM: dts: Set i2c7 clock at 400kHz for exynos based Peach boards

The downstream ChromeOS 3.8 kernel sets the clock frequency
for the I2C bus 7 at 400kHz. Do the same change in mainline.

Suggested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index b8fea56b16a0396c8bb472952e69a5fb4ddc03b5..f24770937ec01a27cab08ca5aace8d82a3596840 100644 (file)
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -489,6 +489,7 @@
 
 &hsi2c_7 {
        status = "okay";
+       clock-frequency = <400000>;
 
        max98090: codec@10 {
                compatible = "maxim,max98090";

diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 17537f0ab44a4568742748ac8c72a776baba80d6..88b354452d2f39f3aee6476089ea0e66141a1116 100644 (file)
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -487,6 +487,7 @@
 
 &hsi2c_7 {
        status = "okay";
+       clock-frequency = <400000>;
 
        max98091: codec@10 {
                compatible = "maxim,max98091";