typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
-void cpu_register_physical_memory(target_phys_addr_t start_addr,
- ram_addr_t size,
- ram_addr_t phys_offset);
+void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
+ ram_addr_t size,
+ ram_addr_t phys_offset,
+ ram_addr_t region_offset);
+static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
+ ram_addr_t size,
+ ram_addr_t phys_offset)
+{
+ cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
+}
+
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(ram_addr_t);
void qemu_ram_free(ram_addr_t addr);
typedef struct PhysPageDesc {
/* offset in host memory of the page + io_index in the low bits */
ram_addr_t phys_offset;
+ ram_addr_t region_offset;
} PhysPageDesc;
#define L2_BITS 10
CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
void *opaque[TARGET_PAGE_SIZE][2][4];
+ ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4];
} subpage_t;
#ifdef _WIN32
and avoid full address decoding in every device.
We can't use the high bits of pd for this because
IO_MEM_ROMD uses these as a ram address. */
- iotlb = (pd & ~TARGET_PAGE_MASK) + paddr;
+ iotlb = (pd & ~TARGET_PAGE_MASK);
+ if (p) {
+ /* FIXME: What if this isn't page aligned? */
+ iotlb += p->region_offset;
+ } else {
+ iotlb += paddr;
+ }
}
code_address = address;
#endif /* defined(CONFIG_USER_ONLY) */
#if !defined(CONFIG_USER_ONLY)
+
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
- ram_addr_t memory);
+ ram_addr_t memory, ram_addr_t region_offset);
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
- ram_addr_t orig_memory);
+ ram_addr_t orig_memory, ram_addr_t region_offset);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
need_subpage) \
do { \
/* register physical memory. 'size' must be a multiple of the target
page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
- io memory page */
-void cpu_register_physical_memory(target_phys_addr_t start_addr,
- ram_addr_t size,
- ram_addr_t phys_offset)
+ io memory page. The address used when calling the IO function is
+ the offset from the start of the region, plus region_offset. Both
+ start_region and regon_offset are rounded down to a page boundary
+ before calculating this offset. This should not be a problem unless
+ the low bits of start_addr and region_offset differ. */
+void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
+ ram_addr_t size,
+ ram_addr_t phys_offset,
+ ram_addr_t region_offset)
{
target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
if (kvm_enabled())
kvm_set_phys_mem(start_addr, size, phys_offset);
+ region_offset &= TARGET_PAGE_MASK;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
end_addr = start_addr + (target_phys_addr_t)size;
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
if (!(orig_memory & IO_MEM_SUBPAGE)) {
subpage = subpage_init((addr & TARGET_PAGE_MASK),
- &p->phys_offset, orig_memory);
+ &p->phys_offset, orig_memory,
+ p->region_offset);
} else {
subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
>> IO_MEM_SHIFT];
}
- subpage_register(subpage, start_addr2, end_addr2, phys_offset);
+ subpage_register(subpage, start_addr2, end_addr2, phys_offset,
+ region_offset);
+ p->region_offset = 0;
} else {
p->phys_offset = phys_offset;
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
} else {
p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
p->phys_offset = phys_offset;
+ p->region_offset = region_offset;
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
- (phys_offset & IO_MEM_ROMD))
+ (phys_offset & IO_MEM_ROMD)) {
phys_offset += TARGET_PAGE_SIZE;
- else {
+ }else {
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
subpage = subpage_init((addr & TARGET_PAGE_MASK),
- &p->phys_offset, IO_MEM_UNASSIGNED);
+ &p->phys_offset, IO_MEM_UNASSIGNED,
+ 0);
subpage_register(subpage, start_addr2, end_addr2,
- phys_offset);
+ phys_offset, region_offset);
+ p->region_offset = 0;
}
}
}
+ region_offset += TARGET_PAGE_SIZE;
}
/* since each CPU stores ram addresses in its TLB cache, we must
uint32_t ret;
unsigned int idx;
- idx = SUBPAGE_IDX(addr - mmio->base);
+ idx = SUBPAGE_IDX(addr);
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
mmio, len, addr, idx);
#endif
- ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr);
+ ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len],
+ addr + mmio->region_offset[idx][0][len]);
return ret;
}
{
unsigned int idx;
- idx = SUBPAGE_IDX(addr - mmio->base);
+ idx = SUBPAGE_IDX(addr);
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
mmio, len, addr, idx, value);
#endif
- (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value);
+ (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len],
+ addr + mmio->region_offset[idx][1][len],
+ value);
}
static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
};
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
- ram_addr_t memory)
+ ram_addr_t memory, ram_addr_t region_offset)
{
int idx, eidx;
unsigned int i;
if (io_mem_read[memory][i]) {
mmio->mem_read[idx][i] = &io_mem_read[memory][i];
mmio->opaque[idx][0][i] = io_mem_opaque[memory];
+ mmio->region_offset[idx][0][i] = region_offset;
}
if (io_mem_write[memory][i]) {
mmio->mem_write[idx][i] = &io_mem_write[memory][i];
mmio->opaque[idx][1][i] = io_mem_opaque[memory];
+ mmio->region_offset[idx][1][i] = region_offset;
}
}
}
}
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
- ram_addr_t orig_memory)
+ ram_addr_t orig_memory, ram_addr_t region_offset)
{
subpage_t *mmio;
int subpage_memory;
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
#endif
*phys = subpage_memory | IO_MEM_SUBPAGE;
- subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory);
+ subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory,
+ region_offset);
}
return mmio;
if (is_write) {
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ if (p)
+ addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
/* XXX: could force cpu_single_env to NULL to avoid
potential bugs */
if (l >= 4 && ((addr & 3) == 0)) {
!(pd & IO_MEM_ROMD)) {
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ if (p)
+ addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
if (l >= 4 && ((addr & 3) == 0)) {
/* 32 bit read access */
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
!(pd & IO_MEM_ROMD)) {
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ if (p)
+ addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
} else {
/* RAM case */
!(pd & IO_MEM_ROMD)) {
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ if (p)
+ addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
#ifdef TARGET_WORDS_BIGENDIAN
val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ if (p)
+ addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
} else {
unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ if (p)
+ addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
#ifdef TARGET_WORDS_BIGENDIAN
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ if (p)
+ addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
} else {
unsigned long addr1;
#ifdef NVIC
static const uint8_t gic_id[] =
{ 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
-#define GIC_DIST_OFFSET 0
/* The NVIC has 16 internal vectors. However these are not exposed
through the normal GIC interface. */
#define GIC_BASE_IRQ 32
#else
static const uint8_t gic_id[] =
{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
-#define GIC_DIST_OFFSET 0x1000
#define GIC_BASE_IRQ 0
#endif
typedef struct gic_state
{
- uint32_t base;
qemu_irq parent_irq[NCPU];
int enabled;
int cpu_enabled[NCPU];
cpu = gic_get_current_cpu();
cm = 1 << cpu;
- offset -= s->base + GIC_DIST_OFFSET;
if (offset < 0x100) {
#ifndef NVIC
if (offset == 0)
#ifdef NVIC
gic_state *s = (gic_state *)opaque;
uint32_t addr;
- addr = offset - s->base;
+ addr = offset;
if (addr < 0x100 || addr > 0xd00)
return nvic_readl(s->nvic, addr);
#endif
int cpu;
cpu = gic_get_current_cpu();
- offset -= s->base + GIC_DIST_OFFSET;
if (offset < 0x100) {
#ifdef NVIC
goto bad_reg;
gic_state *s = (gic_state *)opaque;
#ifdef NVIC
uint32_t addr;
- addr = offset - s->base;
+ addr = offset;
if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
nvic_writel(s->nvic, addr, value);
return;
}
#endif
- if (offset - s->base == GIC_DIST_OFFSET + 0xf00) {
+ if (offset == 0xf00) {
int cpu;
int irq;
int mask;
return 0;
}
-static gic_state *gic_init(uint32_t base, qemu_irq *parent_irq)
+static gic_state *gic_init(uint32_t dist_base, qemu_irq *parent_irq)
{
gic_state *s;
int iomemtype;
}
iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
gic_dist_writefn, s);
- cpu_register_physical_memory(base + GIC_DIST_OFFSET, 0x00001000,
+ cpu_register_physical_memory(dist_base, 0x00001000,
iomemtype);
- s->base = base;
gic_reset(s);
register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);
return s;
#define LOCK_VALUE 0xa05f
typedef struct {
- uint32_t base;
uint32_t sys_id;
uint32_t leds;
uint16_t lockval;
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* ID */
return s->sys_id;
uint32_t val)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x08: /* LED */
s = (arm_sysctl_state *)qemu_mallocz(sizeof(arm_sysctl_state));
if (!s)
return;
- s->base = base;
s->sys_id = sys_id;
/* The MPcore bootloader uses these flags to start secondary CPUs.
We don't use a bootloader, so do this here. */
typedef struct {
void *timer[2];
int level[2];
- uint32_t base;
qemu_irq irq;
} sp804_state;
sp804_state *s = (sp804_state *)opaque;
/* ??? Don't know the PrimeCell ID for this device. */
- offset -= s->base;
if (offset < 0x20) {
return arm_timer_read(s->timer[0], offset);
} else {
{
sp804_state *s = (sp804_state *)opaque;
- offset -= s->base;
if (offset < 0x20) {
arm_timer_write(s->timer[0], offset, value);
} else {
s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
- s->base = base;
s->irq = irq;
/* ??? The timers are actually configurable between 32kHz and 1MHz, but
we don't implement that. */
typedef struct {
void *timer[3];
- uint32_t base;
} icp_pit_state;
static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
int n;
/* ??? Don't know the PrimeCell ID for this device. */
- offset -= s->base;
n = offset >> 8;
if (n > 3)
cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
- offset -= s->base;
n = offset >> 8;
if (n > 3)
cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
icp_pit_state *s;
s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
- s->base = base;
/* Timer 0 runs at the system clock speed (40MHz). */
s->timer[0] = arm_timer_init(40000000, pic[irq]);
/* The other two timers run at 1MHz. */
/* Bitbanded IO. Each word corresponds to a single bit. */
/* Get the byte address of the real memory for a bitband acess. */
-static inline uint32_t bitband_addr(uint32_t addr)
+static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
{
uint32_t res;
- res = addr & 0xe0000000;
+ res = *(uint32_t *)opaque;
res |= (addr & 0x1ffffff) >> 5;
return res;
static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
{
uint8_t v;
- cpu_physical_memory_read(bitband_addr(offset), &v, 1);
+ cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
uint32_t addr;
uint8_t mask;
uint8_t v;
- addr = bitband_addr(offset);
+ addr = bitband_addr(opaque, offset);
mask = (1 << ((offset >> 2) & 7));
cpu_physical_memory_read(addr, &v, 1);
if (value & 1)
uint32_t addr;
uint16_t mask;
uint16_t v;
- addr = bitband_addr(offset) & ~1;
+ addr = bitband_addr(opaque, offset) & ~1;
mask = (1 << ((offset >> 2) & 15));
mask = tswap16(mask);
cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
uint32_t addr;
uint16_t mask;
uint16_t v;
- addr = bitband_addr(offset) & ~1;
+ addr = bitband_addr(opaque, offset) & ~1;
mask = (1 << ((offset >> 2) & 15));
mask = tswap16(mask);
cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
uint32_t addr;
uint32_t mask;
uint32_t v;
- addr = bitband_addr(offset) & ~3;
+ addr = bitband_addr(opaque, offset) & ~3;
mask = (1 << ((offset >> 2) & 31));
mask = tswap32(mask);
cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
uint32_t addr;
uint32_t mask;
uint32_t v;
- addr = bitband_addr(offset) & ~3;
+ addr = bitband_addr(opaque, offset) & ~3;
mask = (1 << ((offset >> 2) & 31));
mask = tswap32(mask);
cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
static void armv7m_bitband_init(void)
{
int iomemtype;
+ static uint32_t bitband1_offset = 0x20000000;
+ static uint32_t bitband2_offset = 0x40000000;
iomemtype = cpu_register_io_memory(0, bitband_readfn, bitband_writefn,
- NULL);
+ &bitband1_offset);
cpu_register_physical_memory(0x22000000, 0x02000000, iomemtype);
+ iomemtype = cpu_register_io_memory(0, bitband_readfn, bitband_writefn,
+ &bitband2_offset);
cpu_register_physical_memory(0x42000000, 0x02000000, iomemtype);
}
typedef struct ds1225y_t
{
- target_phys_addr_t mem_base;
uint32_t chip_size;
QEMUFile *file;
uint8_t *contents;
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
ds1225y_t *s = opaque;
- int64_t pos;
uint32_t val;
- pos = addr - s->mem_base;
- if (pos >= s->chip_size)
- pos -= s->chip_size;
-
- val = s->contents[pos];
+ val = s->contents[addr];
#ifdef DEBUG_NVRAM
printf("nvram: read 0x%x at " TARGET_FMT_lx "\n", val, addr);
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
{
ds1225y_t *s = opaque;
- int64_t pos;
#ifdef DEBUG_NVRAM
printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr);
#endif
- pos = addr - s->mem_base;
- s->contents[pos] = val & 0xff;
+ s->contents[addr] = val & 0xff;
if (s->file) {
- qemu_fseek(s->file, pos, SEEK_SET);
+ qemu_fseek(s->file, addr, SEEK_SET);
qemu_put_byte(s->file, (int)val);
qemu_fflush(s->file);
}
return;
}
- nvram_writeb(opaque, addr - s->chip_size, val);
+ nvram_writeb(opaque, addr, val);
}
static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
if (!s->contents) {
return NULL;
}
- s->mem_base = mem_base;
s->protection = 7;
/* Read current file */
PCIDevice dev;
VLANClientState *vc;
NICInfo *nd;
- uint32_t mmio_base;
int mmio_index;
uint32_t mac_reg[0x8000];
e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
E1000State *s = opaque;
- unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
+ unsigned int index = (addr & 0x1ffff) >> 2;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
{
E1000State *s = opaque;
- unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
+ unsigned int index = (addr & 0x1ffff) >> 2;
if (index < NREADOPS && macreg_readops[index])
{
int i, j;
pci_device_save(&s->dev, f);
- qemu_put_be32s(f, &s->mmio_base);
+ qemu_put_be32(f, 0);
qemu_put_be32s(f, &s->rxbuf_size);
qemu_put_be32s(f, &s->rxbuf_min_shift);
qemu_put_be32s(f, &s->eecd_state.val_in);
return ret;
if (version_id == 1)
qemu_get_sbe32s(f, &i); /* once some unused instance id */
- qemu_get_be32s(f, &s->mmio_base);
+ qemu_get_be32(f); /* Ignored. Was mmio_base. */
qemu_get_be32s(f, &s->rxbuf_size);
qemu_get_be32s(f, &s->rxbuf_min_shift);
qemu_get_be32s(f, &s->eecd_state.val_in);
DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
- d->mmio_base = addr;
cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
}
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
- addr -= s->region[0];
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write1(s, addr, val);
}
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
- addr -= s->region[0];
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write2(s, addr, val);
}
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
- addr -= s->region[0];
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write4(s, addr, val);
}
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
- addr -= s->region[0];
//~ logout("addr=%s\n", regname(addr));
return eepro100_read1(s, addr);
}
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
- addr -= s->region[0];
//~ logout("addr=%s\n", regname(addr));
return eepro100_read2(s, addr);
}
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
- addr -= s->region[0];
//~ logout("addr=%s\n", regname(addr));
return eepro100_read4(s, addr);
}
struct fs_dma_ctrl
{
CPUState *env;
- target_phys_addr_t base;
int nr_channels;
struct fs_dma_channel *channels;
&& ctrl->channels[c].client;
}
-static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
+static inline int fs_channel(target_phys_addr_t addr)
{
/* Every channel has a 0x2000 ctrl register map. */
- return (addr - base) >> 13;
+ return addr >> 13;
}
#ifdef USE_THIS_DEAD_CODE
uint32_t r = 0;
/* Make addr relative to this instances base. */
- c = fs_channel(ctrl->base, addr);
+ c = fs_channel(addr);
addr &= 0x1fff;
switch (addr)
{
int c;
/* Make addr relative to this instances base. */
- c = fs_channel(ctrl->base, addr);
+ c = fs_channel(addr);
addr &= 0x1fff;
switch (addr)
{
ctrl->bh = qemu_bh_new(DMA_run, ctrl);
- ctrl->base = base;
ctrl->env = env;
ctrl->nr_channels = nr_channels;
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
dma_read,
dma_write,
ctrl);
- cpu_register_physical_memory (base + i * 0x2000,
- sizeof ctrl->channels[i].regs,
- ctrl->channels[i].regmap);
+ cpu_register_physical_memory_offset (base + i * 0x2000,
+ sizeof ctrl->channels[i].regs, ctrl->channels[i].regmap,
+ i * 0x2000);
}
return ctrl;
{
CPUState *env;
qemu_irq *irq;
- target_phys_addr_t base;
VLANClientState *vc;
int ethregs;
struct fs_eth *eth = opaque;
uint32_t r = 0;
- /* Make addr relative to this instances base. */
- addr -= eth->base;
switch (addr) {
case R_STAT:
/* Attach an MDIO/PHY abstraction. */
{
struct fs_eth *eth = opaque;
- /* Make addr relative to this instances base. */
- addr -= eth->base;
switch (addr)
{
case RW_MA0_LO:
dma[1].client.pull = NULL;
eth->env = env;
- eth->base = base;
eth->irq = irq;
eth->dma_out = dma;
eth->dma_in = dma + 1;
struct fs_pic_state_t
{
CPUState *env;
- target_phys_addr_t base;
uint32_t rw_mask;
/* Active interrupt lines. */
struct fs_pic_state_t *fs = opaque;
uint32_t rval;
- /* Transform this to a relative addr. */
- addr -= fs->base;
switch (addr)
{
case 0x0:
{
struct fs_pic_state_t *fs = opaque;
D(printf("%s addr=%x val=%x\n", __func__, addr, value));
- /* Transform this to a relative addr. */
- addr -= fs->base;
switch (addr)
{
case 0x0:
intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
cpu_register_physical_memory(base, 0x14, intr_vect_regs);
- fs->base = base;
return pic;
err:
CharDriverState *chr;
qemu_irq *irq;
- target_phys_addr_t base;
-
int pending_tx;
/* Control registers. */
s->env = env;
s->irq = irq;
- s->base = base;
-
s->chr = chr;
/* transmitter begins ready and idle. */
CPUState *env;
qemu_irq *irq;
qemu_irq *nmi;
- target_phys_addr_t base;
QEMUBH *bh_t0;
QEMUBH *bh_t1;
struct fs_timer_t *t = opaque;
uint32_t r = 0;
- /* Make addr relative to this instances base. */
- addr -= t->base;
switch (addr) {
case R_TMR0_DATA:
break;
{
struct fs_timer_t *t = opaque;
- /* Make addr relative to this instances base. */
- addr -= t->base;
switch (addr)
{
case RW_TMR0_DIV:
t->irq = irqs;
t->nmi = nmi;
t->env = env;
- t->base = base;
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
cpu_register_physical_memory (base, 0x5c, timer_regs);
//#define DEBUG_G364
typedef struct G364State {
- target_phys_addr_t vram_base;
unsigned int vram_size;
uint8_t *vram_buffer;
uint32_t ctla;
static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr)
{
G364State *s = opaque;
- target_phys_addr_t relative_addr = addr - s->vram_base;
- return s->vram_buffer[relative_addr];
+ return s->vram_buffer[addr];
}
static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr)
static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
G364State *s = opaque;
- target_phys_addr_t relative_addr = addr - s->vram_base;
- s->vram_buffer[relative_addr] = val;
+ s->vram_buffer[addr] = val;
}
static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
g364fb_reset(s);
s->ds = ds;
- s->vram_base = vram_base;
s->console = graphic_console_init(ds, g364fb_update_display,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
- cpu_register_physical_memory(s->vram_base, vram_size, io_vram);
+ cpu_register_physical_memory(vram_base, vram_size, io_vram);
io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);
static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
{
integratorcm_state *s = (integratorcm_state *)opaque;
- offset -= 0x10000000;
if (offset >= 0x100 && offset < 0x200) {
/* CM_SPD */
if (offset >= 0x180)
uint32_t value)
{
integratorcm_state *s = (integratorcm_state *)opaque;
- offset -= 0x10000000;
switch (offset >> 2) {
case 2: /* CM_OSC */
if (s->cm_lock == 0xa05f)
typedef struct icp_pic_state
{
- uint32_t base;
uint32_t level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
{
icp_pic_state *s = (icp_pic_state *)opaque;
- offset -= s->base;
switch (offset >> 2) {
case 0: /* IRQ_STATUS */
return s->level & s->irq_enabled;
uint32_t value)
{
icp_pic_state *s = (icp_pic_state *)opaque;
- offset -= s->base;
switch (offset >> 2) {
case 2: /* IRQ_ENABLESET */
if (!s)
return NULL;
qi = qemu_allocate_irqs(icp_pic_set_irq, s, 32);
- s->base = base;
s->parent_irq = parent_irq;
s->parent_fiq = parent_fiq;
iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
}
/* CP control registers. */
-typedef struct {
- uint32_t base;
-} icp_control_state;
-
static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
{
- icp_control_state *s = (icp_control_state *)opaque;
- offset -= s->base;
switch (offset >> 2) {
case 0: /* CP_IDFIELD */
return 0x41034003;
static void icp_control_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
- icp_control_state *s = (icp_control_state *)opaque;
- offset -= s->base;
switch (offset >> 2) {
case 1: /* CP_FLASHPROG */
case 2: /* CP_INTREG */
static void icp_control_init(uint32_t base)
{
int iomemtype;
- icp_control_state *s;
- s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state));
iomemtype = cpu_register_io_memory(0, icp_control_readfn,
- icp_control_writefn, s);
+ icp_control_writefn, NULL);
cpu_register_physical_memory(base, 0x00800000, iomemtype);
- s->base = base;
/* ??? Save/restore. */
}
#define PAGE_MASK (PAGE_SIZE - 1)
typedef struct IOMMUState {
- target_phys_addr_t addr;
uint32_t regs[IOMMU_NREGS];
target_phys_addr_t iostart;
uint32_t version;
target_phys_addr_t saddr;
uint32_t ret;
- saddr = (addr - s->addr) >> 2;
+ saddr = addr >> 2;
switch (saddr) {
default:
ret = s->regs[saddr];
IOMMUState *s = opaque;
target_phys_addr_t saddr;
- saddr = (addr - s->addr) >> 2;
+ saddr = addr >> 2;
DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
switch (saddr) {
case IOMMU_CTRL:
if (!s)
return NULL;
- s->addr = addr;
s->version = version;
s->irq = irq;
} screen_state_t;
typedef struct LedState {
- target_phys_addr_t base;
uint8_t segments;
DisplayState *ds;
QEMUConsole *console;
static uint32_t led_readb(void *opaque, target_phys_addr_t addr)
{
LedState *s = opaque;
- int relative_addr = addr - s->base;
uint32_t val;
- switch (relative_addr) {
+ switch (addr) {
case 0:
val = s->segments;
break;
static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LedState *s = opaque;
- int relative_addr = addr - s->base;
- switch (relative_addr) {
+ switch (addr) {
case 0:
s->segments = val;
s->state |= REDRAW_SEGMENTS;
if (!s)
return;
- s->base = base;
s->ds = ds;
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
io = cpu_register_io_memory(0, led_read, led_write, s);
- cpu_register_physical_memory(s->base, 1, io);
+ cpu_register_physical_memory(base, 1, io);
s->console = graphic_console_init(ds, jazz_led_update_display,
jazz_led_invalidate_display,
/* Hardware parameters */
qemu_irq IRQ;
int mem_index;
- target_phys_addr_t mem_base;
uint32_t io_base;
uint16_t size;
/* RTC management */
{
m48t59_t *NVRAM = opaque;
- addr -= NVRAM->mem_base;
m48t59_write(NVRAM, addr, value & 0xff);
}
{
m48t59_t *NVRAM = opaque;
- addr -= NVRAM->mem_base;
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
m48t59_write(NVRAM, addr + 1, value & 0xff);
}
{
m48t59_t *NVRAM = opaque;
- addr -= NVRAM->mem_base;
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
m48t59_t *NVRAM = opaque;
uint32_t retval;
- addr -= NVRAM->mem_base;
retval = m48t59_read(NVRAM, addr);
return retval;
}
m48t59_t *NVRAM = opaque;
uint32_t retval;
- addr -= NVRAM->mem_base;
retval = m48t59_read(NVRAM, addr) << 8;
retval |= m48t59_read(NVRAM, addr + 1);
return retval;
m48t59_t *NVRAM = opaque;
uint32_t retval;
- addr -= NVRAM->mem_base;
retval = m48t59_read(NVRAM, addr) << 24;
retval |= m48t59_read(NVRAM, addr + 1) << 16;
retval |= m48t59_read(NVRAM, addr + 2) << 8;
}
s->IRQ = IRQ;
s->size = size;
- s->mem_base = mem_base;
s->io_base = io_base;
s->addr = 0;
s->type = type;
#include "ppc_mac.h"
struct MacIONVRAMState {
- target_phys_addr_t mem_base;
target_phys_addr_t size;
int mem_index;
uint8_t data[0x2000];
{
MacIONVRAMState *s = opaque;
- addr -= s->mem_base;
addr = (addr >> 4) & 0x1fff;
s->data[addr] = value;
// printf("macio_nvram_writeb %04x = %02x\n", addr, value);
MacIONVRAMState *s = opaque;
uint32_t value;
- addr -= s->mem_base;
addr = (addr >> 4) & 0x1fff;
value = s->data[addr];
// printf("macio_nvram_readb %04x = %02x\n", addr, value);
MacIONVRAMState *s;
s = opaque;
- s->mem_base = mem_base;
cpu_register_physical_memory(mem_base, s->size, s->mem_index);
}
uint8_t cmos_index;
struct tm current_tm;
qemu_irq irq;
- target_phys_addr_t base;
int it_shift;
/* periodic timer */
QEMUTimer *periodic_timer;
{
RTCState *s = opaque;
- return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
+ return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF;
}
static void cmos_mm_writeb (void *opaque,
{
RTCState *s = opaque;
- cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
+ cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
RTCState *s = opaque;
uint32_t val;
- val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
+ val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
- cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
+ cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
RTCState *s = opaque;
uint32_t val;
- val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift);
+ val = cmos_ioport_read(s, addr >> s->it_shift);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
- cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value);
+ cmos_ioport_write(s, addr >> s->it_shift, value);
}
static CPUReadMemoryFunc *rtc_mm_read[] = {
s->cmos_data[RTC_REG_B] = 0x02;
s->cmos_data[RTC_REG_C] = 0x00;
s->cmos_data[RTC_REG_D] = 0x80;
- s->base = base;
rtc_set_date_from_host(s);
qemu_irq_lower(s->irq);
}
-static void m5208_timer_write(m5208_timer_state *s, int offset,
+static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
+ m5208_timer_state *s = (m5208_timer_state *)opaque;
int prescale;
int limit;
switch (offset) {
case 4:
break;
default:
- /* Should never happen. */
- abort();
+ cpu_abort(cpu_single_env, "m5208_timer_write: Bad offset 0x%x\n",
+ (int)offset);
+ break;
}
m5208_timer_update(s);
}
m5208_timer_update(s);
}
-typedef struct {
- m5208_timer_state timer[2];
-} m5208_sys_state;
+static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
+{
+ m5208_timer_state *s = (m5208_timer_state *)opaque;
+ switch (addr) {
+ case 0:
+ return s->pcsr;
+ case 2:
+ return s->pmr;
+ case 4:
+ return ptimer_get_count(s->timer);
+ default:
+ cpu_abort(cpu_single_env, "m5208_timer_read: Bad offset 0x%x\n",
+ (int)addr);
+ return 0;
+ }
+}
+
+static CPUReadMemoryFunc *m5208_timer_readfn[] = {
+ m5208_timer_read,
+ m5208_timer_read,
+ m5208_timer_read
+};
+
+static CPUWriteMemoryFunc *m5208_timer_writefn[] = {
+ m5208_timer_write,
+ m5208_timer_write,
+ m5208_timer_write
+};
static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
{
- m5208_sys_state *s = (m5208_sys_state *)opaque;
switch (addr) {
- /* PIT0 */
- case 0xfc080000:
- return s->timer[0].pcsr;
- case 0xfc080002:
- return s->timer[0].pmr;
- case 0xfc080004:
- return ptimer_get_count(s->timer[0].timer);
- /* PIT1 */
- case 0xfc084000:
- return s->timer[1].pcsr;
- case 0xfc084002:
- return s->timer[1].pmr;
- case 0xfc084004:
- return ptimer_get_count(s->timer[1].timer);
-
- /* SDRAM Controller. */
- case 0xfc0a8110: /* SDCS0 */
+ case 0x110: /* SDCS0 */
{
int n;
for (n = 0; n < 32; n++) {
}
return (n - 1) | 0x40000000;
}
- case 0xfc0a8114: /* SDCS1 */
+ case 0x114: /* SDCS1 */
return 0;
default:
static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- m5208_sys_state *s = (m5208_sys_state *)opaque;
- switch (addr) {
- /* PIT0 */
- case 0xfc080000:
- case 0xfc080002:
- case 0xfc080004:
- m5208_timer_write(&s->timer[0], addr & 0xf, value);
- return;
- /* PIT1 */
- case 0xfc084000:
- case 0xfc084002:
- case 0xfc084004:
- m5208_timer_write(&s->timer[1], addr & 0xf, value);
- return;
- default:
- cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
- (int)addr);
- break;
- }
+ cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
+ (int)addr);
}
static CPUReadMemoryFunc *m5208_sys_readfn[] = {
static void mcf5208_sys_init(qemu_irq *pic)
{
int iomemtype;
- m5208_sys_state *s;
+ m5208_timer_state *s;
QEMUBH *bh;
int i;
- s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state));
iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
- m5208_sys_writefn, s);
+ m5208_sys_writefn, NULL);
/* SDRAMC. */
cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
/* Timers. */
for (i = 0; i < 2; i++) {
- bh = qemu_bh_new(m5208_timer_trigger, &s->timer[i]);
- s->timer[i].timer = ptimer_init(bh);
+ s = (m5208_timer_state *)qemu_mallocz(sizeof(m5208_timer_state));
+ bh = qemu_bh_new(m5208_timer_trigger, s);
+ s->timer = ptimer_init(bh);
+ iomemtype = cpu_register_io_memory(0, m5208_timer_readfn,
+ m5208_timer_writefn, s);
cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
iomemtype);
- s->timer[i].irq = pic[4 + i];
+ s->irq = pic[4 + i];
}
}
malta_fpga_write, s);
cpu_register_physical_memory(base, 0x900, malta);
+ /* 0xa00 is less than a page, so will still get the right offsets. */
cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
s->display = qemu_chr_open("fpga", "vc:320x200");
s = (mpcore_priv_state *)qemu_mallocz(sizeof(mpcore_priv_state));
if (!s)
return NULL;
- s->gic = gic_init(base, pic_irq);
+ s->gic = gic_init(base + 0x1000, pic_irq);
if (!s->gic)
return NULL;
iomemtype = cpu_register_io_memory(0, mpcore_priv_readfn,
/* Mainstone FPGA for extern irqs */
#define FPGA_GPIO_PIN 0
#define MST_NUM_IRQS 16
-#define MST_BASE MST_FPGA_PHYS
#define MST_LEDDAT1 0x10
#define MST_LEDDAT2 0x14
#define MST_LEDCTRL 0x40
#define MST_PCMCIA1 0xe4
typedef struct mst_irq_state{
- target_phys_addr_t target_base;
qemu_irq *parent;
qemu_irq *pins;
mst_fpga_readb(void *opaque, target_phys_addr_t addr)
{
mst_irq_state *s = (mst_irq_state *) opaque;
- addr -= s->target_base;
switch (addr) {
case MST_LEDDAT1:
mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
mst_irq_state *s = (mst_irq_state *) opaque;
- addr -= s->target_base;
value &= 0xffffffff;
switch (addr) {
if (!s)
return NULL;
- s->target_base = base;
s->parent = &cpu->pic[irq];
/* alloc the external 16 irqs */
iomemtype = cpu_register_io_memory(0, mst_fpga_readfn,
mst_fpga_writefn, s);
- cpu_register_physical_memory(MST_BASE, 0x00100000, iomemtype);
+ cpu_register_physical_memory(base, 0x00100000, iomemtype);
register_savevm("mainstone_fpga", 0, 0, mst_fpga_save, mst_fpga_load, s);
return qi;
}
static const char audio_name[] = "mv88w8618";
typedef struct musicpal_audio_state {
- uint32_t base;
qemu_irq irq;
uint32_t playback_mode;
uint32_t status;
{
musicpal_audio_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_AUDIO_PLAYBACK_MODE:
return s->playback_mode;
{
musicpal_audio_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_AUDIO_PLAYBACK_MODE:
if (value & MP_AUDIO_PLAYBACK_EN &&
s = qemu_mallocz(sizeof(musicpal_audio_state));
if (!s)
return NULL;
- s->base = base;
s->irq = irq;
i2c = qemu_mallocz(sizeof(i2c_interface));
} mv88w8618_rx_desc;
typedef struct mv88w8618_eth_state {
- uint32_t base;
qemu_irq irq;
uint32_t smir;
uint32_t icr;
{
mv88w8618_eth_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_ETH_SMIR:
if (s->smir & MP_ETH_SMIR_OPCODE) {
{
mv88w8618_eth_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_ETH_SMIR:
s->smir = value;
s = qemu_mallocz(sizeof(mv88w8618_eth_state));
if (!s)
return;
- s->base = base;
s->irq = irq;
s->vc = qemu_new_vlan_client(nd->vlan, eth_receive, eth_can_receive, s);
iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
typedef struct musicpal_lcd_state {
- uint32_t base;
uint32_t mode;
uint32_t irqctrl;
int page;
{
musicpal_lcd_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_LCD_IRQCTRL:
return s->irqctrl;
{
musicpal_lcd_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_LCD_IRQCTRL:
s->irqctrl = value;
s = qemu_mallocz(sizeof(musicpal_lcd_state));
if (!s)
return;
- s->base = base;
s->ds = ds;
iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
musicpal_lcd_writefn, s);
typedef struct mv88w8618_pic_state
{
- uint32_t base;
uint32_t level;
uint32_t enabled;
qemu_irq parent_irq;
{
mv88w8618_pic_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_PIC_STATUS:
return s->level & s->enabled;
{
mv88w8618_pic_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_PIC_ENABLE_SET:
s->enabled |= value;
if (!s)
return NULL;
qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
- s->base = base;
s->parent_irq = parent_irq;
iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
mv88w8618_pic_writefn, s);
typedef struct mv88w8618_pit_state {
void *timer[4];
uint32_t control;
- uint32_t base;
} mv88w8618_pit_state;
static void mv88w8618_timer_tick(void *opaque)
mv88w8618_pit_state *s = opaque;
mv88w8618_timer_state *t;
- offset -= s->base;
switch (offset) {
case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
mv88w8618_timer_state *t;
int i;
- offset -= s->base;
switch (offset) {
case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
t = s->timer[offset >> 2];
if (!s)
return;
- s->base = base;
/* Letting them all run at 1 MHz is likely just a pragmatic
* simplification. */
s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
#define MP_FLASHCFG_CFGR0 0x04
typedef struct mv88w8618_flashcfg_state {
- uint32_t base;
uint32_t cfgr0;
} mv88w8618_flashcfg_state;
{
mv88w8618_flashcfg_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_FLASHCFG_CFGR0:
return s->cfgr0;
{
mv88w8618_flashcfg_state *s = opaque;
- offset -= s->base;
switch (offset) {
case MP_FLASHCFG_CFGR0:
s->cfgr0 = value;
if (!s)
return;
- s->base = base;
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
mv88w8618_flashcfg_writefn, s);
static uint32_t musicpal_read(void *opaque, target_phys_addr_t offset)
{
- offset -= 0x80000000;
switch (offset) {
case MP_BOARD_REVISION:
return 0x0031;
static void musicpal_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
- offset -= 0x80000000;
switch (offset) {
case MP_GPIO_OE_HI: /* used for LCD brightness control */
lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
struct omap_lcd_panel_s *lcd;
- target_phys_addr_t ulpd_pm_base;
uint32_t ulpd_pm_regs[21];
int64_t ulpd_gauge_start;
- target_phys_addr_t pin_cfg_base;
uint32_t func_mux_ctrl[14];
uint32_t comp_mode_ctrl[1];
uint32_t pull_dwn_ctrl[4];
int compat1509;
uint32_t mpui_ctrl;
- target_phys_addr_t mpui_base;
struct omap_tipb_bridge_s *private_tipb;
struct omap_tipb_bridge_s *public_tipb;
- target_phys_addr_t tcmi_base;
uint32_t tcmi_regs[17];
struct dpll_ctl_s {
- target_phys_addr_t base;
uint16_t mode;
omap_clk dpll;
} dpll[3];
omap_clk clks;
struct {
- target_phys_addr_t mpu_base;
- target_phys_addr_t dsp_base;
-
int cold_start;
int clocking_scheme;
uint16_t arm_ckctl;
struct omap_gp_timer_s *gptimer[12];
- target_phys_addr_t tap_base;
-
struct omap_synctimer_s {
- target_phys_addr_t base;
uint32_t val;
uint16_t readh;
} synctimer;
struct omap_intr_handler_s {
qemu_irq *pins;
qemu_irq parent_intr[2];
- target_phys_addr_t base;
unsigned char nbanks;
int level_only;
static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
- int i, offset = addr - s->base;
+ int i, offset = addr;
int bank_no = offset >> 8;
int line_no;
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
uint32_t value)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
- int i, offset = addr - s->base;
+ int i, offset = addr;
int bank_no = offset >> 8;
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
offset &= 0xff;
s->parent_intr[0] = parent_irq;
s->parent_intr[1] = parent_fiq;
- s->base = base;
s->nbanks = nbanks;
s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
if (pins)
iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
omap_inth_writefn, s);
- cpu_register_physical_memory(s->base, size, iomemtype);
+ cpu_register_physical_memory(base, size, iomemtype);
return s;
}
static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
- int offset = addr - s->base;
+ int offset = addr;
int bank_no, line_no;
struct omap_intr_handler_bank_s *bank = 0;
uint32_t value)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
- int offset = addr - s->base;
+ int offset = addr;
int bank_no, line_no;
struct omap_intr_handler_bank_s *bank = 0;
s->parent_intr[0] = parent_irq;
s->parent_intr[1] = parent_fiq;
- s->base = base;
s->nbanks = nbanks;
s->level_only = 1;
s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
iomemtype = cpu_register_io_memory(0, omap2_inth_readfn,
omap2_inth_writefn, s);
- cpu_register_physical_memory(s->base, size, iomemtype);
+ cpu_register_physical_memory(base, size, iomemtype);
return s;
}
struct omap_mpu_timer_s {
qemu_irq irq;
omap_clk clk;
- target_phys_addr_t base;
uint32_t val;
int64_t time;
QEMUTimer *timer;
static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* CNTL_TIMER */
return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
uint32_t value)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* CNTL_TIMER */
omap_timer_sync(s);
s->enable = (value >> 5) & 1;
s->irq = irq;
s->clk = clk;
- s->base = base;
s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
s->tick = qemu_bh_new(omap_timer_fire, s);
omap_mpu_timer_reset(s);
iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
omap_mpu_timer_writefn, s);
- cpu_register_physical_memory(s->base, 0x100, iomemtype);
+ cpu_register_physical_memory(base, 0x100, iomemtype);
return s;
}
static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
- int offset = addr - s->timer.base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* CNTL_TIMER */
return (s->timer.ptv << 9) | (s->timer.ar << 8) |
(s->timer.st << 7) | (s->free << 1);
uint32_t value)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
- int offset = addr - s->timer.base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* CNTL_TIMER */
omap_timer_sync(&s->timer);
s->timer.ptv = (value >> 9) & 7;
s->timer.irq = irq;
s->timer.clk = clk;
- s->timer.base = base;
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
omap_wd_timer_writefn, s);
- cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
+ cpu_register_physical_memory(base, 0x100, iomemtype);
return s;
}
s->timer.irq = irq;
s->timer.clk = clk;
- s->timer.base = base;
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
omap_os_timer_writefn, s);
- cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
}
static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->ulpd_pm_base;
uint16_t ret;
- switch (offset) {
+ switch (addr) {
case 0x14: /* IT_STATUS */
- ret = s->ulpd_pm_regs[offset >> 2];
- s->ulpd_pm_regs[offset >> 2] = 0;
+ ret = s->ulpd_pm_regs[addr >> 2];
+ s->ulpd_pm_regs[addr >> 2] = 0;
qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
return ret;
case 0x48: /* LOCL_TIME */
case 0x4c: /* APLL_CTRL */
case 0x50: /* POWER_CTRL */
- return s->ulpd_pm_regs[offset >> 2];
+ return s->ulpd_pm_regs[addr >> 2];
}
OMAP_BAD_REG(addr);
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->ulpd_pm_base;
int64_t now, ticks;
int div, mult;
static const int bypass_div[4] = { 1, 2, 4, 4 };
uint16_t diff;
- switch (offset) {
+ switch (addr) {
case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */
case 0x08: /* COUNTER_HIGH_FREQ_LSB */
case 0x10: /* GAUGING_CTRL */
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
- if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
+ if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
now = qemu_get_clock(vm_clock);
if (value & 1)
qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
}
}
- s->ulpd_pm_regs[offset >> 2] = value;
+ s->ulpd_pm_regs[addr >> 2] = value;
break;
case 0x18: /* Reserved */
case 0x38: /* COUNTER_32_FIQ */
case 0x48: /* LOCL_TIME */
case 0x50: /* POWER_CTRL */
- s->ulpd_pm_regs[offset >> 2] = value;
+ s->ulpd_pm_regs[addr >> 2] = value;
break;
case 0x30: /* CLOCK_CTRL */
- diff = s->ulpd_pm_regs[offset >> 2] ^ value;
- s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
+ diff = s->ulpd_pm_regs[addr >> 2] ^ value;
+ s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
omap_ulpd_clk_update(s, diff, value);
break;
case 0x34: /* SOFT_REQ */
- diff = s->ulpd_pm_regs[offset >> 2] ^ value;
- s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
+ diff = s->ulpd_pm_regs[addr >> 2] ^ value;
+ s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
omap_ulpd_req_update(s, diff, value);
break;
* omitted altogether, probably a typo. */
/* This register has identical semantics with DPLL(1:3) control
* registers, see omap_dpll_write() */
- diff = s->ulpd_pm_regs[offset >> 2] & value;
- s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
+ diff = s->ulpd_pm_regs[addr >> 2] & value;
+ s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
if (diff & (0x3ff << 2)) {
if (value & (1 << 4)) { /* PLL_ENABLE */
div = ((value >> 5) & 3) + 1; /* PLL_DIV */
}
/* Enter the desired mode. */
- s->ulpd_pm_regs[offset >> 2] =
- (s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
- ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
+ s->ulpd_pm_regs[addr >> 2] =
+ (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
+ ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
/* Act as if the lock is restored. */
- s->ulpd_pm_regs[offset >> 2] |= 2;
+ s->ulpd_pm_regs[addr >> 2] |= 2;
break;
case 0x4c: /* APLL_CTRL */
- diff = s->ulpd_pm_regs[offset >> 2] & value;
- s->ulpd_pm_regs[offset >> 2] = value & 0xf;
+ diff = s->ulpd_pm_regs[addr >> 2] & value;
+ s->ulpd_pm_regs[addr >> 2] = value & 0xf;
if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
(value & (1 << 0)) ? "apll" : "dpll4"));
int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
omap_ulpd_pm_writefn, mpu);
- mpu->ulpd_pm_base = base;
- cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
omap_ulpd_pm_reset(mpu);
}
static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->pin_cfg_base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */
case 0x04: /* FUNC_MUX_CTRL_1 */
case 0x08: /* FUNC_MUX_CTRL_2 */
- return s->func_mux_ctrl[offset >> 2];
+ return s->func_mux_ctrl[addr >> 2];
case 0x0c: /* COMP_MODE_CTRL_0 */
return s->comp_mode_ctrl[0];
case 0x30: /* FUNC_MUX_CTRL_B */
case 0x34: /* FUNC_MUX_CTRL_C */
case 0x38: /* FUNC_MUX_CTRL_D */
- return s->func_mux_ctrl[(offset >> 2) - 1];
+ return s->func_mux_ctrl[(addr >> 2) - 1];
case 0x40: /* PULL_DWN_CTRL_0 */
case 0x44: /* PULL_DWN_CTRL_1 */
case 0x48: /* PULL_DWN_CTRL_2 */
case 0x4c: /* PULL_DWN_CTRL_3 */
- return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
+ return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
case 0x50: /* GATE_INH_CTRL_0 */
return s->gate_inh_ctrl[0];
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->pin_cfg_base;
uint32_t diff;
- switch (offset) {
+ switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */
- diff = s->func_mux_ctrl[offset >> 2] ^ value;
- s->func_mux_ctrl[offset >> 2] = value;
+ diff = s->func_mux_ctrl[addr >> 2] ^ value;
+ s->func_mux_ctrl[addr >> 2] = value;
omap_pin_funcmux0_update(s, diff, value);
return;
case 0x04: /* FUNC_MUX_CTRL_1 */
- diff = s->func_mux_ctrl[offset >> 2] ^ value;
- s->func_mux_ctrl[offset >> 2] = value;
+ diff = s->func_mux_ctrl[addr >> 2] ^ value;
+ s->func_mux_ctrl[addr >> 2] = value;
omap_pin_funcmux1_update(s, diff, value);
return;
case 0x08: /* FUNC_MUX_CTRL_2 */
- s->func_mux_ctrl[offset >> 2] = value;
+ s->func_mux_ctrl[addr >> 2] = value;
return;
case 0x0c: /* COMP_MODE_CTRL_0 */
case 0x30: /* FUNC_MUX_CTRL_B */
case 0x34: /* FUNC_MUX_CTRL_C */
case 0x38: /* FUNC_MUX_CTRL_D */
- s->func_mux_ctrl[(offset >> 2) - 1] = value;
+ s->func_mux_ctrl[(addr >> 2) - 1] = value;
return;
case 0x40: /* PULL_DWN_CTRL_0 */
case 0x44: /* PULL_DWN_CTRL_1 */
case 0x48: /* PULL_DWN_CTRL_2 */
case 0x4c: /* PULL_DWN_CTRL_3 */
- s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
+ s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
return;
case 0x50: /* GATE_INH_CTRL_0 */
int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
omap_pin_cfg_writefn, mpu);
- mpu->pin_cfg_base = base;
- cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
omap_pin_cfg_reset(mpu);
}
{
int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
omap_id_writefn, mpu);
- cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
- cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
+ cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
+ cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
if (!cpu_is_omap15xx(mpu))
- cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
+ cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000);
}
/* MPUI Control (Dummy) */
static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->mpui_base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* CTRL */
return s->mpui_ctrl;
case 0x04: /* DEBUG_ADDR */
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->mpui_base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* CTRL */
s->mpui_ctrl = value & 0x007fffff;
break;
int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
omap_mpui_writefn, mpu);
- mpu->mpui_base = base;
- cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
+ cpu_register_physical_memory(base, 0x100, iomemtype);
omap_mpui_reset(mpu);
}
/* TIPB Bridges */
struct omap_tipb_bridge_s {
- target_phys_addr_t base;
qemu_irq abort;
int width_intr;
static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* TIPB_CNTL */
return s->control;
case 0x04: /* TIPB_BUS_ALLOC */
uint32_t value)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* TIPB_CNTL */
s->control = value & 0xffff;
break;
qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
s->abort = abort_irq;
- s->base = base;
omap_tipb_bridge_reset(s);
iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
omap_tipb_bridge_writefn, s);
- cpu_register_physical_memory(s->base, 0x100, iomemtype);
+ cpu_register_physical_memory(base, 0x100, iomemtype);
return s;
}
static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->tcmi_base;
uint32_t ret;
- switch (offset) {
+ switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
case 0x08: /* EMIFF_PRIO */
case 0x30: /* TIMEOUT3 */
case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
case 0x40: /* EMIFS_CFG_DYN_WAIT */
- return s->tcmi_regs[offset >> 2];
+ return s->tcmi_regs[addr >> 2];
case 0x20: /* EMIFF_SDRAM_CONFIG */
- ret = s->tcmi_regs[offset >> 2];
- s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
+ ret = s->tcmi_regs[addr >> 2];
+ s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
/* XXX: We can try using the VGA_DIRTY flag for this */
return ret;
}
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->tcmi_base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
case 0x08: /* EMIFF_PRIO */
case 0x30: /* TIMEOUT3 */
case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
case 0x40: /* EMIFS_CFG_DYN_WAIT */
- s->tcmi_regs[offset >> 2] = value;
+ s->tcmi_regs[addr >> 2] = value;
break;
case 0x0c: /* EMIFS_CONFIG */
- s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
+ s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
break;
default:
int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
omap_tcmi_writefn, mpu);
- mpu->tcmi_base = base;
- cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
+ cpu_register_physical_memory(base, 0x100, iomemtype);
omap_tcmi_reset(mpu);
}
static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
- int offset = addr - s->base;
- if (offset == 0x00) /* CTL_REG */
+ if (addr == 0x00) /* CTL_REG */
return s->mode;
OMAP_BAD_REG(addr);
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
uint16_t diff;
- int offset = addr - s->base;
static const int bypass_div[4] = { 1, 2, 4, 4 };
int div, mult;
- if (offset == 0x00) { /* CTL_REG */
+ if (addr == 0x00) { /* CTL_REG */
/* See omap_ulpd_pm_write() too */
diff = s->mode & value;
s->mode = value & 0x2fff;
int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
omap_dpll_writefn, s);
- s->base = base;
s->dpll = clk;
omap_dpll_reset(s);
- cpu_register_physical_memory(s->base, 0x100, iomemtype);
+ cpu_register_physical_memory(base, 0x100, iomemtype);
}
/* UARTs */
struct omap_uart_s {
+ target_phys_addr_t base;
SerialState *serial; /* TODO */
struct omap_target_agent_s *ta;
- target_phys_addr_t base;
omap_clk fclk;
qemu_irq irq;
static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ addr &= 0xff;
+ switch (addr) {
case 0x20: /* MDR1 */
return s->mdr[0];
case 0x24: /* MDR2 */
uint32_t value)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ addr &= 0xff;
+ switch (addr) {
case 0x20: /* MDR1 */
s->mdr[0] = value & 0x7f;
break;
s->ta = ta;
- cpu_register_physical_memory(s->base + 0x20, 0x100, iomemtype);
+ cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
return s;
}
static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->clkm.mpu_base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* ARM_CKCTL */
return s->clkm.arm_ckctl;
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->clkm.mpu_base;
uint16_t diff;
omap_clk clk;
static const char *clkschemename[8] = {
"mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
};
- switch (offset) {
+ switch (addr) {
case 0x00: /* ARM_CKCTL */
diff = s->clkm.arm_ckctl ^ value;
s->clkm.arm_ckctl = value & 0x7fff;
static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->clkm.dsp_base;
- switch (offset) {
+ switch (addr) {
case 0x04: /* DSP_IDLECT1 */
return s->clkm.dsp_idlect1;
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- int offset = addr - s->clkm.dsp_base;
uint16_t diff;
- switch (offset) {
+ switch (addr) {
case 0x04: /* DSP_IDLECT1 */
diff = s->clkm.dsp_idlect1 ^ value;
s->clkm.dsp_idlect1 = value & 0x01f7;
cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
};
- s->clkm.mpu_base = mpu_base;
- s->clkm.dsp_base = dsp_base;
s->clkm.arm_idlect1 = 0x03ff;
s->clkm.arm_idlect2 = 0x0100;
s->clkm.dsp_idlect1 = 0x0002;
omap_clkm_reset(s);
s->clkm.cold_start = 0x3a;
- cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
- cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
+ cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]);
+ cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]);
}
/* MPU I/O */
struct omap_mpuio_s {
- target_phys_addr_t base;
qemu_irq irq;
qemu_irq kbd_irq;
qemu_irq *in;
struct omap_mpuio_s *s = (struct omap_mpuio_s *)
qemu_mallocz(sizeof(struct omap_mpuio_s));
- s->base = base;
s->irq = gpio_int;
s->kbd_irq = kbd_int;
s->wakeup = wakeup;
iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
omap_mpuio_writefn, s);
- cpu_register_physical_memory(s->base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
/* General-Purpose I/O */
struct omap_gpio_s {
- target_phys_addr_t base;
qemu_irq irq;
qemu_irq *in;
qemu_irq handler[16];
struct omap_gpio_s *s = (struct omap_gpio_s *)
qemu_mallocz(sizeof(struct omap_gpio_s));
- s->base = base;
s->irq = irq;
s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
omap_gpio_reset(s);
iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
omap_gpio_writefn, s);
- cpu_register_physical_memory(s->base, 0x1000, iomemtype);
+ cpu_register_physical_memory(base, 0x1000, iomemtype);
return s;
}
/* MicroWire Interface */
struct omap_uwire_s {
- target_phys_addr_t base;
qemu_irq txirq;
qemu_irq rxirq;
qemu_irq txdrq;
struct omap_uwire_s *s = (struct omap_uwire_s *)
qemu_mallocz(sizeof(struct omap_uwire_s));
- s->base = base;
s->txirq = irq[0];
s->rxirq = irq[1];
s->txdrq = dma;
iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
omap_uwire_writefn, s);
- cpu_register_physical_memory(s->base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
}
/* Real-time Clock module */
struct omap_rtc_s {
- target_phys_addr_t base;
qemu_irq irq;
qemu_irq alarm;
QEMUTimer *clk;
struct omap_rtc_s *s = (struct omap_rtc_s *)
qemu_mallocz(sizeof(struct omap_rtc_s));
- s->base = base;
s->irq = irq[0];
s->alarm = irq[1];
s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);
iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
omap_rtc_writefn, s);
- cpu_register_physical_memory(s->base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
}
/* Multi-channel Buffered Serial Port interfaces */
struct omap_mcbsp_s {
- target_phys_addr_t base;
qemu_irq txirq;
qemu_irq rxirq;
qemu_irq txdrq;
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
qemu_mallocz(sizeof(struct omap_mcbsp_s));
- s->base = base;
s->txirq = irq[0];
s->rxirq = irq[1];
s->txdrq = dma[0];
iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
omap_mcbsp_writefn, s);
- cpu_register_physical_memory(s->base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
}
/* LED Pulse Generators */
struct omap_lpg_s {
- target_phys_addr_t base;
QEMUTimer *tm;
uint8_t control;
struct omap_lpg_s *s = (struct omap_lpg_s *)
qemu_mallocz(sizeof(struct omap_lpg_s));
- s->base = base;
s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s);
omap_lpg_reset(s);
iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
omap_lpg_writefn, s);
- cpu_register_physical_memory(s->base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
qemu_irq in;
qemu_irq out;
omap_clk clk;
- target_phys_addr_t base;
QEMUTimer *timer;
QEMUTimer *match;
struct omap_target_agent_s *ta;
static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* TIDR */
return 0x21;
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* TIDR */
case 0x14: /* TISTAT */
case 0x34: /* TWPS */
iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn,
omap_gp_timer_writefn, s);
- s->base = omap_l4_attach(ta, 0, iomemtype);
+ omap_l4_attach(ta, 0, iomemtype);
return s;
}
static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* 32KSYNCNT_REV */
return 0x21;
struct omap_synctimer_s *s = &mpu->synctimer;
omap_synctimer_reset(s);
- s->base = omap_l4_attach(ta, 0, l4_register_io_memory(0,
- omap_synctimer_readfn, omap_synctimer_writefn, s));
+ omap_l4_attach(ta, 0, l4_register_io_memory(0,
+ omap_synctimer_readfn, omap_synctimer_writefn, s));
}
/* General-Purpose Interface of OMAP2 */
struct omap2_gpio_s {
- target_phys_addr_t base;
qemu_irq irq[2];
qemu_irq wkup;
qemu_irq *in;
static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* GPIO_REVISION */
return 0x18;
uint32_t value)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
- int offset = addr - s->base;
uint32_t diff;
int ln;
- switch (offset) {
+ switch (addr) {
case 0x00: /* GPIO_REVISION */
case 0x14: /* GPIO_SYSSTATUS */
case 0x38: /* GPIO_DATAIN */
static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
- int offset = addr - s->base;
uint32_t cur = 0;
uint32_t mask = 0xffff;
- switch (offset & ~3) {
+ switch (addr & ~3) {
case 0x00: /* GPIO_REVISION */
case 0x14: /* GPIO_SYSSTATUS */
case 0x38: /* GPIO_DATAIN */
iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn,
omap_gpio_module_writefn, s);
- s->base = omap_l4_attach(ta, region, iomemtype);
+ omap_l4_attach(ta, region, iomemtype);
}
struct omap_gpif_s {
struct omap2_gpio_s module[5];
int modules;
- target_phys_addr_t topbase;
int autoidle;
int gpo;
};
static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
{
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
- int offset = addr - s->topbase;
- switch (offset) {
+ switch (addr) {
case 0x00: /* IPGENERICOCPSPL_REVISION */
return 0x18;
uint32_t value)
{
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
- int offset = addr - s->topbase;
- switch (offset) {
+ switch (addr) {
case 0x00: /* IPGENERICOCPSPL_REVISION */
case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn,
omap_gpif_top_writefn, s);
- s->topbase = omap_l4_attach(ta, 1, iomemtype);
+ omap_l4_attach(ta, 1, iomemtype);
return s;
}
/* Multichannel SPI */
struct omap_mcspi_s {
- target_phys_addr_t base;
qemu_irq irq;
int chnum;
static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
- int offset = addr - s->base;
int ch = 0;
uint32_t ret;
- switch (offset) {
+ switch (addr) {
case 0x00: /* MCSPI_REVISION */
return 0x91;
uint32_t value)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
- int offset = addr - s->base;
int ch = 0;
- switch (offset) {
+ switch (addr) {
case 0x00: /* MCSPI_REVISION */
case 0x14: /* MCSPI_SYSSTATUS */
case 0x30: /* MCSPI_CHSTAT0 */
iomemtype = l4_register_io_memory(0, omap_mcspi_readfn,
omap_mcspi_writefn, s);
- s->base = omap_l4_attach(ta, 0, iomemtype);
+ omap_l4_attach(ta, 0, iomemtype);
return s;
}
/* Enhanced Audio Controller (CODEC only) */
struct omap_eac_s {
- target_phys_addr_t base;
qemu_irq irq;
uint16_t sysconfig;
static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
- int offset = addr - s->base;
uint32_t ret;
- switch (offset) {
+ switch (addr) {
case 0x000: /* CPCFR1 */
return s->config[0];
case 0x004: /* CPCFR2 */
uint32_t value)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x098: /* APD1LCR */
case 0x09c: /* APD1RCR */
case 0x0a0: /* APD2LCR */
iomemtype = cpu_register_io_memory(0, omap_eac_readfn,
omap_eac_writefn, s);
- s->base = omap_l4_attach(ta, 0, iomemtype);
+ omap_l4_attach(ta, 0, iomemtype);
#endif
return s;
/* STI/XTI (emulation interface) console - reverse engineered only */
struct omap_sti_s {
- target_phys_addr_t base;
- target_phys_addr_t channel_base;
qemu_irq irq;
CharDriverState *chr;
static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* STI_REVISION */
return 0x10;
uint32_t value)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* STI_REVISION */
case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
OMAP_RO_REG(addr);
uint32_t value)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
- int offset = addr - s->channel_base;
- int ch = offset >> 6;
+ int ch = addr >> 6;
uint8_t byte = value;
if (ch == STI_TRACE_CONTROL_CHANNEL) {
iomemtype = l4_register_io_memory(0, omap_sti_readfn,
omap_sti_writefn, s);
- s->base = omap_l4_attach(ta, 0, iomemtype);
+ omap_l4_attach(ta, 0, iomemtype);
iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn,
omap_sti_fifo_writefn, s);
- s->channel_base = channel_base;
- cpu_register_physical_memory(s->channel_base, 0x10000, iomemtype);
+ cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
return s;
}
static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
- target_phys_addr_t reg = addr - s->base;
- switch (reg) {
+ switch (addr) {
case 0x00: /* COMPONENT */
return s->component;
uint32_t value)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
- target_phys_addr_t reg = addr - s->base;
- switch (reg) {
+ switch (addr) {
case 0x00: /* COMPONENT */
case 0x28: /* AGENT_STATUS */
OMAP_RO_REG(addr);
static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
- target_phys_addr_t reg = addr - s->tap_base;
- switch (reg) {
+ switch (addr) {
case 0x204: /* IDCODE_reg */
switch (s->mpu_model) {
case omap2420:
void omap_tap_init(struct omap_target_agent_s *ta,
struct omap_mpu_state_s *mpu)
{
- mpu->tap_base = omap_l4_attach(ta, 0, l4_register_io_memory(0,
+ omap_l4_attach(ta, 0, l4_register_io_memory(0,
omap_tap_readfn, omap_tap_writefn, mpu));
}
/* Power, Reset, and Clock Management */
struct omap_prcm_s {
- target_phys_addr_t base;
qemu_irq irq[3];
struct omap_mpu_state_s *mpu;
static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
- int offset = addr - s->base;
uint32_t ret;
- switch (offset) {
+ switch (addr) {
case 0x000: /* PRCM_REVISION */
return 0x10;
case 0x0f4: /* GENERAL_PURPOSE18 */
case 0x0f8: /* GENERAL_PURPOSE19 */
case 0x0fc: /* GENERAL_PURPOSE20 */
- return s->scratch[(offset - 0xb0) >> 2];
+ return s->scratch[(addr - 0xb0) >> 2];
case 0x140: /* CM_CLKSEL_MPU */
return s->clksel[0];
uint32_t value)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x000: /* PRCM_REVISION */
case 0x054: /* PRCM_VOLTST */
case 0x084: /* PRCM_CLKCFG_STATUS */
case 0x0f4: /* GENERAL_PURPOSE18 */
case 0x0f8: /* GENERAL_PURPOSE19 */
case 0x0fc: /* GENERAL_PURPOSE20 */
- s->scratch[(offset - 0xb0) >> 2] = value;
+ s->scratch[(addr - 0xb0) >> 2] = value;
break;
case 0x140: /* CM_CLKSEL_MPU */
iomemtype = l4_register_io_memory(0, omap_prcm_readfn,
omap_prcm_writefn, s);
- s->base = omap_l4_attach(ta, 0, iomemtype);
+ omap_l4_attach(ta, 0, iomemtype);
omap_l4_attach(ta, 1, iomemtype);
return s;
/* System and Pinout control */
struct omap_sysctl_s {
- target_phys_addr_t base;
struct omap_mpu_state_s *mpu;
uint32_t sysconfig;
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
- int offset = addr - s->base;
int pad_offset, byte_offset;
int value;
- switch (offset) {
+ switch (addr) {
case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
- pad_offset = (offset - 0x30) >> 2;
- byte_offset = (offset - 0x30) & (4 - 1);
+ pad_offset = (addr - 0x30) >> 2;
+ byte_offset = (addr - 0x30) & (4 - 1);
value = s->padconf[pad_offset];
value = (value >> (byte_offset * 8)) & 0xff;
static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x000: /* CONTROL_REVISION */
return 0x20;
return s->sysconfig;
case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
- return s->padconf[(offset - 0x30) >> 2];
+ return s->padconf[(addr - 0x30) >> 2];
case 0x270: /* CONTROL_DEBOBS */
return s->obs;
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
- int offset = addr - s->base;
int pad_offset, byte_offset;
int prev_value;
- switch (offset) {
+ switch (addr) {
case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
- pad_offset = (offset - 0x30) >> 2;
- byte_offset = (offset - 0x30) & (4 - 1);
+ pad_offset = (addr - 0x30) >> 2;
+ byte_offset = (addr - 0x30) & (4 - 1);
prev_value = s->padconf[pad_offset];
prev_value &= ~(0xff << (byte_offset * 8));
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x000: /* CONTROL_REVISION */
case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
case 0x2c0: /* CONTROL_PSA_VALUE */
case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
/* XXX: should check constant bits */
- s->padconf[(offset - 0x30) >> 2] = value & 0x1f1f1f1f;
+ s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
break;
case 0x270: /* CONTROL_DEBOBS */
iomemtype = l4_register_io_memory(0, omap_sysctl_readfn,
omap_sysctl_writefn, s);
- s->base = omap_l4_attach(ta, 0, iomemtype);
+ omap_l4_attach(ta, 0, iomemtype);
omap_l4_attach(ta, 0, iomemtype);
return s;
/* SDRAM Controller Subsystem */
struct omap_sdrc_s {
- target_phys_addr_t base;
-
uint8_t config;
};
static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* SDRC_REVISION */
return 0x20;
uint32_t value)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* SDRC_REVISION */
case 0x14: /* SDRC_SYSSTATUS */
case 0x48: /* SDRC_ERR_ADDR */
struct omap_sdrc_s *s = (struct omap_sdrc_s *)
qemu_mallocz(sizeof(struct omap_sdrc_s));
- s->base = base;
omap_sdrc_reset(s);
iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn,
omap_sdrc_writefn, s);
- cpu_register_physical_memory(s->base, 0x1000, iomemtype);
+ cpu_register_physical_memory(base, 0x1000, iomemtype);
return s;
}
/* General-Purpose Memory Controller */
struct omap_gpmc_s {
- target_phys_addr_t base;
qemu_irq irq;
uint8_t sysconfig;
static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
- int offset = addr - s->base;
int cs;
struct omap_gpmc_cs_file_s *f;
- switch (offset) {
+ switch (addr) {
case 0x000: /* GPMC_REVISION */
return 0x20;
return 0x001;
case 0x060 ... 0x1d4:
- cs = (offset - 0x060) / 0x30;
- offset -= cs * 0x30;
+ cs = (addr - 0x060) / 0x30;
+ addr -= cs * 0x30;
f = s->cs_file + cs;
- switch (offset) {
+ switch (addr) {
case 0x60: /* GPMC_CONFIG1 */
return f->config[0];
case 0x64: /* GPMC_CONFIG2 */
case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
return s->ecc_cfg;
case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
- cs = (offset & 0x1f) >> 2;
+ cs = (addr & 0x1f) >> 2;
/* TODO: check correctness */
return
((s->ecc[cs].cp & 0x07) << 0) |
uint32_t value)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
- int offset = addr - s->base;
int cs;
struct omap_gpmc_cs_file_s *f;
- switch (offset) {
+ switch (addr) {
case 0x000: /* GPMC_REVISION */
case 0x014: /* GPMC_SYSSTATUS */
case 0x054: /* GPMC_STATUS */
break;
case 0x060 ... 0x1d4:
- cs = (offset - 0x060) / 0x30;
- offset -= cs * 0x30;
+ cs = (addr - 0x060) / 0x30;
+ addr -= cs * 0x30;
f = s->cs_file + cs;
- switch (offset) {
+ switch (addr) {
case 0x60: /* GPMC_CONFIG1 */
f->config[0] = value & 0xffef3e13;
break;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
qemu_mallocz(sizeof(struct omap_gpmc_s));
- s->base = base;
omap_gpmc_reset(s);
iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn,
omap_gpmc_writefn, s);
- cpu_register_physical_memory(s->base, 0x1000, iomemtype);
+ cpu_register_physical_memory(base, 0x1000, iomemtype);
return s;
}
struct soc_dma_s *dma;
struct omap_mpu_state_s *mpu;
- target_phys_addr_t base;
omap_clk clk;
qemu_irq irq[4];
void (*intr_update)(struct omap_dma_s *s);
static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
- int reg, ch, offset = addr - s->base;
+ int reg, ch;
uint16_t ret;
- switch (offset) {
+ switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
- if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
+ if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
break;
return ret;
}
/* Fall through. */
case 0x000 ... 0x2fe:
- reg = offset & 0x3f;
- ch = (offset >> 6) & 0x0f;
+ reg = addr & 0x3f;
+ ch = (addr >> 6) & 0x0f;
if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
break;
return ret;
break;
/* Fall through. */
case 0x400:
- if (omap_dma_sys_read(s, offset, &ret))
+ if (omap_dma_sys_read(s, addr, &ret))
break;
return ret;
case 0xb00 ... 0xbfe:
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
- if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
+ if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
break;
return ret;
}
uint32_t value)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
- int reg, ch, offset = addr - s->base;
+ int reg, ch;
- switch (offset) {
+ switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
- if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
+ if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
break;
return;
}
/* Fall through. */
case 0x000 ... 0x2fe:
- reg = offset & 0x3f;
- ch = (offset >> 6) & 0x0f;
+ reg = addr & 0x3f;
+ ch = (addr >> 6) & 0x0f;
if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
break;
return;
break;
case 0x400:
/* Fall through. */
- if (omap_dma_sys_write(s, offset, value))
+ if (omap_dma_sys_write(s, addr, value))
break;
return;
case 0xb00 ... 0xbfe:
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
- if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
+ if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
break;
return;
}
num_irqs = 16;
memsize = 0xc00;
}
- s->base = base;
s->model = model;
s->mpu = mpu;
s->clk = clk;
iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
omap_dma_writefn, s);
- cpu_register_physical_memory(s->base, memsize, iomemtype);
+ cpu_register_physical_memory(base, memsize, iomemtype);
mpu->drq = s->dma->drq;
static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
- int irqn = 0, chnum, offset = addr - s->base;
+ int irqn = 0, chnum;
struct omap_dma_channel_s *ch;
- switch (offset) {
+ switch (addr) {
case 0x00: /* DMA4_REVISION */
return 0x40;
return s->gcr;
case 0x80 ... 0xfff:
- offset -= 0x80;
- chnum = offset / 0x60;
+ addr -= 0x80;
+ chnum = addr / 0x60;
ch = s->ch + chnum;
- offset -= chnum * 0x60;
+ addr -= chnum * 0x60;
break;
default:
}
/* Per-channel registers */
- switch (offset) {
+ switch (addr) {
case 0x00: /* DMA4_CCR */
return (ch->buf_disable << 25) |
(ch->src_sync << 24) |
uint32_t value)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
- int chnum, irqn = 0, offset = addr - s->base;
+ int chnum, irqn = 0;
struct omap_dma_channel_s *ch;
- switch (offset) {
+ switch (addr) {
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
case 0x10: /* DMA4_IRQSTATUS_L2 */
return;
case 0x80 ... 0xfff:
- offset -= 0x80;
- chnum = offset / 0x60;
+ addr -= 0x80;
+ chnum = addr / 0x60;
ch = s->ch + chnum;
- offset -= chnum * 0x60;
+ addr -= chnum * 0x60;
break;
case 0x00: /* DMA4_REVISION */
}
/* Per-channel registers */
- switch (offset) {
+ switch (addr) {
case 0x00: /* DMA4_CCR */
ch->buf_disable = (value >> 25) & 1;
ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
struct omap_dma_s *s = (struct omap_dma_s *)
qemu_mallocz(sizeof(struct omap_dma_s));
- s->base = base;
s->model = omap_dma_4;
s->chans = chans;
s->mpu = mpu;
iomemtype = cpu_register_io_memory(0, omap_dma4_readfn,
omap_dma4_writefn, s);
- cpu_register_physical_memory(s->base, 0x1000, iomemtype);
+ cpu_register_physical_memory(base, 0x1000, iomemtype);
mpu->drq = s->dma->drq;
#include "omap.h"
struct omap_dss_s {
- target_phys_addr_t diss_base;
- target_phys_addr_t disc_base;
- target_phys_addr_t rfbi_base;
- target_phys_addr_t venc_base;
- target_phys_addr_t im3_base;
qemu_irq irq;
qemu_irq drq;
DisplayState *state;
static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->diss_base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* DSS_REVISIONNUMBER */
return 0x20;
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->diss_base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* DSS_REVISIONNUMBER */
case 0x14: /* DSS_SYSSTATUS */
case 0x50: /* DSS_PSA_LCD_REG_1 */
static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->disc_base;
- switch (offset) {
+ switch (addr) {
case 0x000: /* DISPC_REVISION */
return 0x20;
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->disc_base;
- switch (offset) {
+ switch (addr) {
case 0x010: /* DISPC_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_dss_reset(s);
static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->rfbi_base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* RFBI_REVISION */
return 0x10;
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->rfbi_base;
- switch (offset) {
+ switch (addr) {
case 0x10: /* RFBI_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_rfbi_reset(s);
static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
{
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->venc_base;
-
- switch (offset) {
+ switch (addr) {
case 0x00: /* REV_ID */
case 0x04: /* STATUS */
case 0x08: /* F_CONTROL */
static void omap_venc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->venc_base;
-
- switch (offset) {
+ switch (addr) {
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
case 0x14: /* SYNC_CTRL */
static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
{
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->im3_base;
-
- switch (offset) {
+ switch (addr) {
case 0x0a8: /* SBIMERRLOGA */
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
static void omap_im3_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
- int offset = addr - s->im3_base;
-
- switch (offset) {
+ switch (addr) {
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
case 0x198: /* SBTMSTATE_L */
omap_venc1_writefn, s);
iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn,
omap_im3_writefn, s);
- s->diss_base = omap_l4_attach(ta, 0, iomemtype[0]);
- s->disc_base = omap_l4_attach(ta, 1, iomemtype[1]);
- s->rfbi_base = omap_l4_attach(ta, 2, iomemtype[2]);
- s->venc_base = omap_l4_attach(ta, 3, iomemtype[3]);
- s->im3_base = l3_base;
- cpu_register_physical_memory(s->im3_base, 0x1000, iomemtype[4]);
+ omap_l4_attach(ta, 0, iomemtype[0]);
+ omap_l4_attach(ta, 1, iomemtype[1]);
+ omap_l4_attach(ta, 3, iomemtype[3]);
+ cpu_register_physical_memory(l3_base, 0x1000, iomemtype[4]);
#if 0
if (ds)
#include "omap.h"
struct omap_i2c_s {
- target_phys_addr_t base;
qemu_irq irq;
qemu_irq drq[2];
i2c_slave slave;
/* TODO: set a value greater or equal to real hardware */
s->revision = 0x11;
- s->base = base;
s->irq = irq;
s->drq[0] = dma[0];
s->drq[1] = dma[1];
iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
omap_i2c_writefn, s);
- cpu_register_physical_memory(s->base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
}
iomemtype = l4_register_io_memory(0, omap_i2c_readfn,
omap_i2c_writefn, s);
- s->base = omap_l4_attach(ta, 0, iomemtype);
+ omap_l4_attach(ta, 0, iomemtype);
return s;
}
#include "omap.h"
struct omap_lcd_panel_s {
- target_phys_addr_t base;
qemu_irq irq;
DisplayState *state;
QEMUConsole *console;
static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* LCD_CONTROL */
return (s->tft << 23) | (s->plm << 20) |
(s->tft << 7) | (s->interrupts << 3) |
uint32_t value)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
- int offset = addr - s->base;
- switch (offset) {
+ switch (addr) {
case 0x00: /* LCD_CONTROL */
s->plm = (value >> 20) & 3;
s->tft = (value >> 7) & 1;
s->irq = irq;
s->dma = dma;
- s->base = base;
s->state = ds;
s->imif_base = imif_base;
s->emiff_base = emiff_base;
iomemtype = cpu_register_io_memory(0, omap_lcdc_readfn,
omap_lcdc_writefn, s);
- cpu_register_physical_memory(s->base, 0x100, iomemtype);
+ cpu_register_physical_memory(base, 0x100, iomemtype);
s->console = graphic_console_init(ds, omap_update_display,
omap_invalidate_display,
#include "sd.h"
struct omap_mmc_s {
- target_phys_addr_t base;
qemu_irq irq;
qemu_irq *dma;
qemu_irq coverswitch;
qemu_mallocz(sizeof(struct omap_mmc_s));
s->irq = irq;
- s->base = base;
s->dma = dma;
s->clk = clk;
s->lines = 1; /* TODO: needs to be settable per-board */
iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
omap_mmc_writefn, s);
- cpu_register_physical_memory(s->base, 0x800, iomemtype);
+ cpu_register_physical_memory(base, 0x800, iomemtype);
/* Instantiate the storage */
s->card = sd_init(bd, 0);
iomemtype = l4_register_io_memory(0, omap_mmc_readfn,
omap_mmc_writefn, s);
- s->base = omap_l4_attach(ta, 0, iomemtype);
+ omap_l4_attach(ta, 0, iomemtype);
/* Instantiate the storage */
s->card = sd_init(bd, 0);
0xbe00 << s->shift,
(s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
if (s->iomemtype)
- cpu_register_physical_memory(s->base + (0xc000 << s->shift),
- 0x4000 << s->shift, s->iomemtype);
+ cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift),
+ 0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift));
}
void onenand_base_unmap(void *opaque)
static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
{
struct onenand_s *s = (struct onenand_s *) opaque;
- int offset = (addr - s->base) >> s->shift;
+ int offset = addr >> s->shift;
switch (offset) {
case 0x0000 ... 0xc000:
- return lduw_le_p(s->boot[0] + (addr - s->base));
+ return lduw_le_p(s->boot[0] + addr);
case 0xf000: /* Manufacturer ID */
return (s->id >> 16) & 0xff;
uint32_t value)
{
struct onenand_s *s = (struct onenand_s *) opaque;
- int offset = (addr - s->base) >> s->shift;
+ int offset = addr >> s->shift;
int sec;
switch (offset) {
int epp_timeout;
uint32_t last_read_offset; /* For debugging */
/* Memory-mapped interface */
- target_phys_addr_t base;
int it_shift;
};
{
ParallelState *s = opaque;
- return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
+ return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
}
static void parallel_mm_writeb (void *opaque,
{
ParallelState *s = opaque;
- parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
+ parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}
static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
- return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
+ return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
}
static void parallel_mm_writew (void *opaque,
{
ParallelState *s = opaque;
- parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
+ parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}
static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
- return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
+ return parallel_ioport_read_sw(s, addr >> s->it_shift);
}
static void parallel_mm_writel (void *opaque,
{
ParallelState *s = opaque;
- parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
+ parallel_ioport_write_sw(s, addr >> s->it_shift, value);
}
static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
if (!s)
return NULL;
parallel_reset(s, irq, chr);
- s->base = base;
s->it_shift = it_shift;
io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
qemu_irq irq_kbd;
qemu_irq irq_mouse;
- target_phys_addr_t base;
int it_shift;
} KBDState;
{
KBDState *s = opaque;
- switch ((addr - s->base) >> s->it_shift) {
+ switch (addr >> s->it_shift) {
case 0:
return kbd_read_data(s, 0) & 0xff;
case 1:
{
KBDState *s = opaque;
- switch ((addr - s->base) >> s->it_shift) {
+ switch (addr >> s->it_shift) {
case 0:
kbd_write_data(s, 0, value & 0xff);
break;
s->irq_kbd = kbd_irq;
s->irq_mouse = mouse_irq;
- s->base = base;
s->it_shift = it_shift;
kbd_reset(s);
uint8_t *p;
ret = -1;
- offset -= pfl->base;
boff = offset & 0xFF; /* why this here ?? */
if (pfl->width == 2)
uint8_t cmd;
cmd = value;
- offset -= pfl->base;
DPRINTF("%s: writing offset " TARGET_FMT_lx " value %08x width %d wcycle 0x%x\n",
__func__, offset, value, width, pfl->wcycle);
DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
ret = -1;
- offset -= pfl->base;
if (pfl->rom_mode) {
/* Lazy reset of to ROMD mode */
if (pfl->wcycle == 0)
}
DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__,
offset, value, width, pfl->wcycle);
- offset -= pfl->base;
offset &= pfl->chip_len - 1;
DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
#include "primecell.h"
typedef struct {
- uint32_t base;
uint32_t readbuff;
uint32_t flags;
uint32_t lcr;
pl011_state *s = (pl011_state *)opaque;
uint32_t c;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
return pl011_id[s->type][(offset - 0xfe0) >> 2];
}
pl011_state *s = (pl011_state *)opaque;
unsigned char ch;
- offset -= s->base;
switch (offset >> 2) {
case 0: /* UARTDR */
/* ??? Check if transmitter is enabled. */
iomemtype = cpu_register_io_memory(0, pl011_readfn,
pl011_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->irq = irq;
s->type = type;
s->chr = chr;
#define PL022_INT_TX 0x08
typedef struct {
- uint32_t base;
uint32_t cr0;
uint32_t cr1;
uint32_t bitmask;
pl022_state *s = (pl022_state *)opaque;
int val;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
return pl022_id[(offset - 0xfe0) >> 2];
}
{
pl022_state *s = (pl022_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* CR0 */
s->cr0 = value;
iomemtype = cpu_register_io_memory(0, pl022_readfn,
pl022_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->irq = irq;
s->xfer_cb = xfer_cb;
s->opaque = opaque;
typedef struct {
QEMUTimer *timer;
qemu_irq irq;
- uint32_t base;
uint64_t start_time;
uint32_t tick_offset;
{
pl031_state *s = (pl031_state *)opaque;
- offset -= s->base;
-
if (offset >= 0xfe0 && offset < 0x1000)
return pl031_id[(offset - 0xfe0) >> 2];
{
pl031_state *s = (pl031_state *)opaque;
- offset -= s->base;
switch (offset) {
case RTC_LR:
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->irq = irq;
/* ??? We assume vm_clock is zero at this point. */
qemu_get_timedate(&tm, 0);
typedef struct {
void *dev;
- uint32_t base;
uint32_t cr;
uint32_t clk;
uint32_t last;
static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)
{
pl050_state *s = (pl050_state *)opaque;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000)
return pl050_id[(offset - 0xfe0) >> 2];
uint32_t value)
{
pl050_state *s = (pl050_state *)opaque;
- offset -= s->base;
switch (offset >> 2) {
case 0: /* KMICR */
s->cr = value;
iomemtype = cpu_register_io_memory(0, pl050_readfn,
pl050_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->irq = irq;
s->is_mouse = is_mouse;
if (is_mouse)
{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
typedef struct {
- uint32_t base;
int locked;
uint8_t data;
uint8_t old_data;
{
pl061_state *s = (pl061_state *)opaque;
- offset -= s->base;
if (offset >= 0xfd0 && offset < 0x1000) {
return pl061_id[(offset - 0xfd0) >> 2];
}
pl061_state *s = (pl061_state *)opaque;
uint8_t mask;
- offset -= s->base;
if (offset < 0x400) {
mask = (offset >> 2) & s->dir;
s->data = (s->data & ~mask) | (value & mask);
iomemtype = cpu_register_io_memory(0, pl061_readfn,
pl061_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->irq = irq;
pl061_reset(s);
if (out)
} pl080_channel;
typedef struct {
- uint32_t base;
uint8_t tc_int;
uint8_t tc_mask;
uint8_t err_int;
uint32_t i;
uint32_t mask;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
if (s->nchannels == 8) {
return pl080_id[(offset - 0xfe0) >> 2];
pl080_state *s = (pl080_state *)opaque;
int i;
- offset -= s->base;
if (offset >= 0x100 && offset < 0x200) {
i = (offset & 0xe0) >> 5;
if (i >= s->nchannels)
iomemtype = cpu_register_io_memory(0, pl080_readfn,
pl080_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->irq = irq;
s->nchannels = nchannels;
/* ??? Save/restore. */
};
typedef struct {
- uint32_t base;
DisplayState *ds;
QEMUConsole *console;
{
pl110_state *s = (pl110_state *)opaque;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
if (s->versatile)
return pl110_versatile_id[(offset - 0xfe0) >> 2];
/* For simplicity invalidate the display whenever a control register
is writen to. */
s->invalidate = 1;
- offset -= s->base;
if (offset >= 0x200 && offset < 0x400) {
/* Pallette. */
n = (offset - 0x200) >> 2;
iomemtype = cpu_register_io_memory(0, pl110_readfn,
pl110_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->ds = ds;
s->versatile = versatile;
s->irq = irq;
typedef struct {
SDState *card;
- uint32_t base;
uint32_t clock;
uint32_t power;
uint32_t cmdarg;
pl181_state *s = (pl181_state *)opaque;
uint32_t tmp;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
return pl181_id[(offset - 0xfe0) >> 2];
}
{
pl181_state *s = (pl181_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* Power */
s->power = value & 0xff;
iomemtype = cpu_register_io_memory(0, pl181_readfn,
pl181_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->card = sd_init(bd, 0);
s->irq[0] = irq0;
s->irq[1] = irq1;
#define PL190_NUM_PRIO 17
typedef struct {
- uint32_t base;
uint32_t level;
uint32_t soft_level;
uint32_t irq_enable;
pl190_state *s = (pl190_state *)opaque;
int i;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
return pl190_id[(offset - 0xfe0) >> 2];
}
{
pl190_state *s = (pl190_state *)opaque;
- offset -= s->base;
if (offset >= 0x100 && offset < 0x140) {
s->vect_addr[(offset - 0x100) >> 2] = val;
pl190_update_vectors(s);
pl190_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
qi = qemu_allocate_irqs(pl190_set_irq, s, 32);
- s->base = base;
s->irq = irq;
s->fiq = fiq;
pl190_reset(s);
*/
typedef struct ref405ep_fpga_t ref405ep_fpga_t;
struct ref405ep_fpga_t {
- uint32_t base;
uint8_t reg0;
uint8_t reg1;
};
uint32_t ret;
fpga = opaque;
- addr -= fpga->base;
switch (addr) {
case 0x0:
ret = fpga->reg0;
ref405ep_fpga_t *fpga;
fpga = opaque;
- addr -= fpga->base;
switch (addr) {
case 0x0:
/* Read only */
fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
if (fpga != NULL) {
- fpga->base = base;
fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
ref405ep_fpga_write, fpga);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
*/
typedef struct taihu_cpld_t taihu_cpld_t;
struct taihu_cpld_t {
- uint32_t base;
uint8_t reg0;
uint8_t reg1;
};
uint32_t ret;
cpld = opaque;
- addr -= cpld->base;
switch (addr) {
case 0x0:
ret = cpld->reg0;
taihu_cpld_t *cpld;
cpld = opaque;
- addr -= cpld->base;
switch (addr) {
case 0x0:
/* Read only */
cpld = qemu_mallocz(sizeof(taihu_cpld_t));
if (cpld != NULL) {
- cpld->base = base;
cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
taihu_cpld_write, cpld);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
uint32_t ret;
int idx;
- idx = MMIO_IDX(addr - mmio->base);
+ idx = MMIO_IDX(addr);
#if defined(DEBUG_MMIO)
printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
mmio, len, addr, idx);
#endif
mem_read = mmio->mem_read[idx];
- ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
+ ret = (*mem_read[len])(mmio->opaque[idx], addr);
return ret;
}
CPUWriteMemoryFunc **mem_write;
int idx;
- idx = MMIO_IDX(addr - mmio->base);
+ idx = MMIO_IDX(addr);
#if defined(DEBUG_MMIO)
printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
__func__, mmio, len, addr, idx, value);
#endif
mem_write = mmio->mem_write[idx];
- (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
+ (*mem_write[len])(mmio->opaque[idx], addr, value);
}
static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
- if (addr == 0xBFFFFFF0)
+ if (addr & 0xf == 0)
retval = pic_intack_read(isa_pic);
// printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
};
struct pxa2xx_i2s_s {
- target_phys_addr_t base;
qemu_irq irq;
struct pxa2xx_dma_state_s *dma;
void (*data_req)(void *, int, int);
static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->pm_base;
switch (addr) {
case PMCR ... PCMD31:
uint32_t value)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->pm_base;
switch (addr) {
case PMCR:
static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->cm_base;
switch (addr) {
case CCCR:
uint32_t value)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->cm_base;
switch (addr) {
case CCCR:
static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->mm_base;
switch (addr) {
case MDCNFG ... SA1110:
uint32_t value)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->mm_base;
switch (addr) {
case MDCNFG ... SA1110:
/* Synchronous Serial Ports */
struct pxa2xx_ssp_s {
- target_phys_addr_t base;
qemu_irq irq;
int enable;
{
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
uint32_t retval;
- addr -= s->base;
switch (addr) {
case SSCR0:
uint32_t value)
{
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
- addr -= s->base;
switch (addr) {
case SSCR0:
static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->rtc_base;
switch (addr) {
case RTTR:
uint32_t value)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->rtc_base;
switch (addr) {
case RTTR:
struct pxa2xx_i2c_s {
i2c_slave slave;
i2c_bus *bus;
- target_phys_addr_t base;
qemu_irq irq;
uint16_t control;
static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
- addr -= s->base;
+ addr &= 0xff;
switch (addr) {
case ICR:
return s->control;
{
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
int ack;
- addr -= s->base;
+ addr &= 0xff;
switch (addr) {
case ICR:
s->control = value & 0xfff7;
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s));
- s->base = base;
s->irq = irq;
s->slave.event = pxa2xx_i2c_event;
s->slave.recv = pxa2xx_i2c_rx;
iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
pxa2xx_i2c_writefn, s);
- cpu_register_physical_memory(s->base & ~page_size, page_size, iomemtype);
+ cpu_register_physical_memory(base & ~page_size, page_size + 1, iomemtype);
register_savevm("pxa2xx_i2c", base, 1,
pxa2xx_i2c_save, pxa2xx_i2c_load, s);
static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
- addr -= s->base;
switch (addr) {
case SACR0:
{
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
uint32_t *sample;
- addr -= s->base;
switch (addr) {
case SACR0:
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
- s->base = base;
s->irq = irq;
s->dma = dma;
s->data_req = pxa2xx_i2s_data_req;
iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
pxa2xx_i2s_writefn, s);
- cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
+ cpu_register_physical_memory(base, 0x100000, iomemtype);
register_savevm("pxa2xx_i2s", base, 0,
pxa2xx_i2s_save, pxa2xx_i2s_load, s);
/* PXA Fast Infra-red Communications Port */
struct pxa2xx_fir_s {
- target_phys_addr_t base;
qemu_irq irq;
struct pxa2xx_dma_state_s *dma;
int enable;
{
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
uint8_t ret;
- addr -= s->base;
switch (addr) {
case ICCR0:
{
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
uint8_t ch;
- addr -= s->base;
switch (addr) {
case ICCR0:
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
qemu_mallocz(sizeof(struct pxa2xx_fir_s));
- s->base = base;
s->irq = irq;
s->dma = dma;
s->chr = chr;
iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
pxa2xx_fir_writefn, s);
- cpu_register_physical_memory(s->base, 0x1000, iomemtype);
+ cpu_register_physical_memory(base, 0x1000, iomemtype);
if (chr)
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
ssp = (struct pxa2xx_ssp_s *)
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
for (i = 0; pxa27x_ssp[i].io_base; i ++) {
+ target_phys_addr_t ssp_base;
s->ssp[i] = &ssp[i];
- ssp[i].base = pxa27x_ssp[i].io_base;
+ ssp_base = pxa27x_ssp[i].io_base;
ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
pxa2xx_ssp_writefn, &ssp[i]);
- cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
+ cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
register_savevm("pxa2xx_ssp", i, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
}
ssp = (struct pxa2xx_ssp_s *)
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
for (i = 0; pxa255_ssp[i].io_base; i ++) {
+ target_phys_addr_t ssp_base;
s->ssp[i] = &ssp[i];
- ssp[i].base = pxa255_ssp[i].io_base;
+ ssp_base = pxa255_ssp[i].io_base;
ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
pxa2xx_ssp_writefn, &ssp[i]);
- cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
+ cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
register_savevm("pxa2xx_ssp", i, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
}
struct pxa2xx_dma_state_s {
pxa2xx_dma_handler_t handler;
- target_phys_addr_t base;
qemu_irq irq;
uint32_t stopintr;
{
struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
unsigned int channel;
- offset -= s->base;
switch (offset) {
case DRCMR64 ... DRCMR74:
{
struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
unsigned int channel;
- offset -= s->base;
switch (offset) {
case DRCMR64 ... DRCMR74:
s->channels = channels;
s->chan = qemu_mallocz(sizeof(struct pxa2xx_dma_channel_s) * s->channels);
- s->base = base;
s->irq = irq;
s->handler = (pxa2xx_dma_handler_t) pxa2xx_dma_request;
s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
#define PXA2XX_GPIO_BANKS 4
struct pxa2xx_gpio_info_s {
- target_phys_addr_t base;
qemu_irq *pic;
int lines;
CPUState *cpu_env;
struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
uint32_t ret;
int bank;
- offset -= s->base;
if (offset >= 0x200)
return 0;
{
struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
int bank;
- offset -= s->base;
if (offset >= 0x200)
return;
s = (struct pxa2xx_gpio_info_s *)
qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));
memset(s, 0, sizeof(struct pxa2xx_gpio_info_s));
- s->base = base;
s->pic = pic;
s->lines = lines;
s->cpu_env = env;
#define PXAKBD_MAXCOL 8
struct pxa2xx_keypad_s{
- target_phys_addr_t base;
qemu_irq irq;
struct keymap *map;
{
struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque;
uint32_t tmp;
- offset -= s->base;
switch (offset) {
case KPC:
target_phys_addr_t offset, uint32_t value)
{
struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque;
- offset -= s->base;
switch (offset) {
case KPC:
struct pxa2xx_keypad_s *s;
s = (struct pxa2xx_keypad_s *) qemu_mallocz(sizeof(struct pxa2xx_keypad_s));
- s->base = base;
s->irq = irq;
iomemtype = cpu_register_io_memory(0, pxa2xx_keypad_readfn,
typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int);
struct pxa2xx_lcdc_s {
- target_phys_addr_t base;
qemu_irq irq;
int irqlevel;
{
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
int ch;
- offset -= s->base;
switch (offset) {
case LCCR0:
{
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
int ch;
- offset -= s->base;
switch (offset) {
case LCCR0:
struct pxa2xx_lcdc_s *s;
s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
- s->base = base;
s->invalidated = 1;
s->irq = irq;
s->ds = ds;
#include "sd.h"
struct pxa2xx_mmci_s {
- target_phys_addr_t base;
qemu_irq irq;
void *dma;
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
uint32_t ret;
- offset -= s->base;
switch (offset) {
case MMC_STRPCL:
target_phys_addr_t offset, uint32_t value)
{
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
- offset -= s->base;
switch (offset) {
case MMC_STRPCL:
struct pxa2xx_mmci_s *s;
s = (struct pxa2xx_mmci_s *) qemu_mallocz(sizeof(struct pxa2xx_mmci_s));
- s->base = base;
s->irq = irq;
s->dma = dma;
struct pxa2xx_pcmcia_s {
struct pcmcia_socket_s slot;
struct pcmcia_card_s *card;
- target_phys_addr_t common_base;
- target_phys_addr_t attr_base;
- target_phys_addr_t io_base;
qemu_irq irq;
qemu_irq cd_irq;
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
- offset -= s->common_base;
return s->card->common_read(s->card->state, offset);
}
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
- offset -= s->common_base;
s->card->common_write(s->card->state, offset, value);
}
}
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
- offset -= s->attr_base;
return s->card->attr_read(s->card->state, offset);
}
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
- offset -= s->attr_base;
s->card->attr_write(s->card->state, offset, value);
}
}
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
- offset -= s->io_base;
return s->card->io_read(s->card->state, offset);
}
struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque;
if (s->slot.attached) {
- offset -= s->io_base;
s->card->io_write(s->card->state, offset, value);
}
}
qemu_mallocz(sizeof(struct pxa2xx_pcmcia_s));
/* Socket I/O Memory Space */
- s->io_base = base | 0x00000000;
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_io_readfn,
pxa2xx_pcmcia_io_writefn, s);
- cpu_register_physical_memory(s->io_base, 0x04000000, iomemtype);
+ cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);
/* Then next 64 MB is reserved */
/* Socket Attribute Memory Space */
- s->attr_base = base | 0x08000000;
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_attr_readfn,
pxa2xx_pcmcia_attr_writefn, s);
- cpu_register_physical_memory(s->attr_base, 0x04000000, iomemtype);
+ cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);
/* Socket Common Memory Space */
- s->common_base = base | 0x0c000000;
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_common_readfn,
pxa2xx_pcmcia_common_writefn, s);
- cpu_register_physical_memory(s->common_base, 0x04000000, iomemtype);
+ cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);
if (base == 0x30000000)
s->slot.slot_string = "PXA PC Card Socket 1";
#define PXA2XX_PIC_SRCS 40
struct pxa2xx_pic_state_s {
- target_phys_addr_t base;
CPUState *cpu_env;
uint32_t int_enabled[2];
uint32_t int_pending[2];
static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
{
struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
- offset -= s->base;
switch (offset) {
case ICIP: /* IRQ Pending register */
uint32_t value)
{
struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
- offset -= s->base;
switch (offset) {
case ICMR: /* Mask register */
static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm)
{
- struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
target_phys_addr_t offset;
if (pxa2xx_cp_reg_map[reg] == -1) {
return 0;
}
- offset = s->base + pxa2xx_cp_reg_map[reg];
+ offset = pxa2xx_cp_reg_map[reg];
return pxa2xx_pic_mem_read(opaque, offset);
}
static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
uint32_t value)
{
- struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
target_phys_addr_t offset;
if (pxa2xx_cp_reg_map[reg] == -1) {
return;
}
- offset = s->base + pxa2xx_cp_reg_map[reg];
+ offset = pxa2xx_cp_reg_map[reg];
pxa2xx_pic_mem_write(opaque, offset, value);
}
return NULL;
s->cpu_env = env;
- s->base = base;
s->int_pending[0] = 0;
s->int_pending[1] = 0;
};
typedef struct {
- target_phys_addr_t base;
int32_t clock;
int32_t oldclock;
uint64_t lastload;
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
int tm = 0;
- offset -= s->base;
-
switch (offset) {
case OSMR3: tm ++;
case OSMR2: tm ++;
int i, tm = 0;
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
- offset -= s->base;
-
switch (offset) {
case OSMR3: tm ++;
case OSMR2: tm ++;
pxa2xx_timer_info *s;
s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
- s->base = base;
s->irq_enabled = 0;
s->oldclock = 0;
s->clock = 0;
#define PA_OUTPORT 0x36
typedef struct {
- target_phys_addr_t base;
-
uint16_t bcr;
uint16_t irlmon;
uint16_t cfctl;
{
r2d_fpga_t *s = opaque;
- addr -= s->base;
-
switch (addr) {
case PA_OUTPORT:
return s->outport;
{
r2d_fpga_t *s = opaque;
- addr -= s->base;
-
switch (addr) {
case PA_OUTPORT:
s->outport = value;
if (!s)
return;
- s->base = base;
iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
r2d_fpga_writefn, s);
cpu_register_physical_memory(base, 0x40, iomemtype);
static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
{
gic_state *s = (gic_state *)opaque;
- offset -= s->base;
return gic_cpu_read(s, gic_get_current_cpu(), offset);
}
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
- offset -= s->base;
gic_cpu_write(s, gic_get_current_cpu(), offset, value);
}
gic_state *s;
int iomemtype;
- s = gic_init(base, &parent_irq);
+ s = gic_init(base + 0x1000, &parent_irq);
if (!s)
return NULL;
iomemtype = cpu_register_io_memory(0, realview_gic_cpu_readfn,
qemu_irq irq;
CharDriverState *chr;
int last_break_enable;
- target_phys_addr_t base;
int it_shift;
int baudbase;
int tsr_retry;
{
SerialState *s = opaque;
- return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
+ return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
}
void serial_mm_writeb (void *opaque,
{
SerialState *s = opaque;
- serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
+ serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
SerialState *s = opaque;
uint32_t val;
- val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
+ val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
- serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
+ serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
SerialState *s = opaque;
uint32_t val;
- val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
+ val = serial_ioport_read(s, addr >> s->it_shift);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
- serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
+ serial_ioport_write(s, addr >> s->it_shift, value);
}
static CPUReadMemoryFunc *serial_mm_read[] = {
if (!s)
return NULL;
- s->base = base;
s->it_shift = it_shift;
serial_init_core(s, irq, baudbase, chr);
sh7750_io_memory = cpu_register_io_memory(0,
sh7750_mem_read,
sh7750_mem_write, s);
- cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
+ cpu_register_physical_memory_offset(0x1c000000, 0x04000000,
+ sh7750_io_memory, 0x1c000000);
sh7750_mm_cache_and_tlb = cpu_register_io_memory(0,
sh7750_mmct_read,
unsigned long address)
{
if (address)
- cpu_register_physical_memory(INTC_A7(address), 4, desc->iomemtype);
+ cpu_register_physical_memory_offset(INTC_A7(address), 4,
+ desc->iomemtype, INTC_A7(address));
}
static void sh_intc_register_source(struct intc_desc *desc,
uint8_t rx_tail;
uint8_t rx_head;
- target_phys_addr_t base;
int freq;
int feat;
int flags;
unsigned char ch;
#ifdef DEBUG_SERIAL
- printf("sh_serial: write base=0x%08lx offs=0x%02x val=0x%02x\n",
- (unsigned long) s->base, offs, val);
+ printf("sh_serial: write offs=0x%02x val=0x%02x\n",
+ offs, val);
#endif
switch(offs) {
case 0x00: /* SMR */
#endif
}
#ifdef DEBUG_SERIAL
- printf("sh_serial: read base=0x%08lx offs=0x%02x val=0x%x\n",
- (unsigned long) s->base, offs, ret);
+ printf("sh_serial: read offs=0x%02x val=0x%x\n",
+ offs, ret);
#endif
if (ret & ~((1 << 16) - 1)) {
static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
{
sh_serial_state *s = opaque;
- return sh_serial_ioport_read(s, addr - s->base);
+ return sh_serial_ioport_read(s, addr);
}
static void sh_serial_write (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
sh_serial_state *s = opaque;
- sh_serial_ioport_write(s, addr - s->base, value);
+ sh_serial_ioport_write(s, addr, value);
}
static CPUReadMemoryFunc *sh_serial_readfn[] = {
if (!s)
return;
- s->base = base;
s->feat = feat;
s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
s->rtrg = 1;
int level[3];
uint32_t tocr;
uint32_t tstr;
- target_phys_addr_t base;
int feat;
} tmu012_state;
#ifdef DEBUG_TIMER
printf("tmu012_read 0x%lx\n", (unsigned long) offset);
#endif
- offset -= s->base;
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN))
#ifdef DEBUG_TIMER
printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
#endif
- offset -= s->base;
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN))
int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
- s->base = base;
s->feat = feat;
s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
slavio_intctl_mem_read,
slavio_intctl_mem_write,
s);
- cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
- slavio_intctl_io_memory);
+ cpu_register_physical_memory_offset(addr + i * TARGET_PAGE_SIZE,
+ INTCTL_SIZE, slavio_intctl_io_memory, i * TARGET_PAGE_SIZE);
s->cpu_irqs[i] = parent_irq[i];
}
io = cpu_register_io_memory(0, slavio_misc_mem_read,
slavio_misc_mem_write, s);
// Slavio control
- cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
+ cpu_register_physical_memory_offset(base + MISC_CFG, MISC_SIZE, io,
+ MISC_CFG);
// Diagnostics
- cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
+ cpu_register_physical_memory_offset(base + MISC_DIAG, MISC_SIZE, io,
+ MISC_DIAG);
// Modem control
- cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
+ cpu_register_physical_memory_offset(base + MISC_MDM, MISC_SIZE, io,
+ MISC_MDM);
/* 16 bit registers */
io = cpu_register_io_memory(0, slavio_led_mem_read,
static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
{
SM501State * s = (SM501State *)opaque;
- uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
uint32_t ret = 0;
- SM501_DPRINTF("sm501 system config regs : read addr=%x, offset=%x\n",
- addr, offset);
+ SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
- switch(offset) {
+ switch(addr) {
case SM501_SYSTEM_CONTROL:
ret = s->system_control;
break;
default:
printf("sm501 system config : not implemented register read."
- " addr=%x, offset=%x\n", addr, offset);
+ " addr=%x\n", (int)addr);
assert(0);
}
target_phys_addr_t addr, uint32_t value)
{
SM501State * s = (SM501State *)opaque;
- uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
- SM501_DPRINTF("sm501 system config regs : write addr=%x, ofs=%x, val=%x\n",
- addr, offset, value);
+ SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
+ addr, value);
- switch(offset) {
+ switch(addr) {
case SM501_SYSTEM_CONTROL:
s->system_control = value & 0xE300B8F7;
break;
default:
printf("sm501 system config : not implemented register write."
- " addr=%x, val=%x\n", addr, value);
+ " addr=%x, val=%x\n", (int)addr, value);
assert(0);
}
}
&sm501_system_config_write,
};
-static uint32_t sm501_disp_ctrl_read(void *opaque,
- target_phys_addr_t addr)
+static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr)
{
SM501State * s = (SM501State *)opaque;
- uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
uint32_t ret = 0;
- SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x, offset=%x\n",
- addr, offset);
+ SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
- switch(offset) {
+ switch(addr) {
case SM501_DC_PANEL_CONTROL:
ret = s->dc_panel_control;
default:
printf("sm501 disp ctrl : not implemented register read."
- " addr=%x, offset=%x\n", addr, offset);
+ " addr=%x\n", (int)addr);
assert(0);
}
uint32_t value)
{
SM501State * s = (SM501State *)opaque;
- uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
- SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, ofs=%x, val=%x\n",
- addr, offset, value);
+ SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
+ addr, value);
- switch(offset) {
+ switch(addr) {
case SM501_DC_PANEL_CONTROL:
s->dc_panel_control = value & 0x0FFF73FF;
break;
default:
printf("sm501 disp ctrl : not implemented register write."
- " addr=%x, val=%x\n", addr, value);
+ " addr=%x, val=%x\n", (int)addr, value);
assert(0);
}
}
static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
{
SM501State * s = (SM501State *)opaque;
- uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
- + SM501_DC + SM501_DC_PANEL_PALETTE);
- SM501_DPRINTF("sm501 palette read addr=%x, offset=%x\n", addr, offset);
+ SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
/* TODO : consider BYTE/WORD access */
/* TODO : consider endian */
- assert(0 <= offset && offset < 0x400 * 3);
- return *(uint32_t*)&s->dc_palette[offset];
+ assert(0 <= addr && addr < 0x400 * 3);
+ return *(uint32_t*)&s->dc_palette[addr];
}
static void sm501_palette_write(void *opaque,
target_phys_addr_t addr, uint32_t value)
{
SM501State * s = (SM501State *)opaque;
- uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
- + SM501_DC + SM501_DC_PANEL_PALETTE);
- SM501_DPRINTF("sm501 palette write addr=%x, ofs=%x, val=%x\n",
- addr, offset, value);
+ SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
+ (int)addr, value);
/* TODO : consider BYTE/WORD access */
/* TODO : consider endian */
- assert(0 <= offset && offset < 0x400 * 3);
- *(uint32_t*)&s->dc_palette[offset] = value;
+ assert(0 <= addr && addr < 0x400 * 3);
+ *(uint32_t*)&s->dc_palette[addr] = value;
}
static CPUReadMemoryFunc *sm501_palette_readfn[] = {
#define NUM_PACKETS 4
typedef struct {
- uint32_t base;
VLANClientState *vc;
uint16_t tcr;
uint16_t rcr;
{
smc91c111_state *s = (smc91c111_state *)opaque;
- offset -= s->base;
if (offset == 14) {
s->bank = value;
return;
{
smc91c111_state *s = (smc91c111_state *)opaque;
- offset -= s->base;
if (offset == 14) {
return s->bank;
}
static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
- smc91c111_state *s = (smc91c111_state *)opaque;
/* 32-bit writes to offset 0xc only actually write to the bank select
register (offset 0xe) */
- if (offset != s->base + 0xc)
+ if (offset != 0xc)
smc91c111_writew(opaque, offset, value & 0xffff);
smc91c111_writew(opaque, offset + 2, value >> 16);
}
iomemtype = cpu_register_io_memory(0, smc91c111_readfn,
smc91c111_writefn, s);
cpu_register_physical_memory(base, 16, iomemtype);
- s->base = base;
s->irq = irq;
memcpy(s->macaddr, nd->macaddr, 6);
#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
struct sl_nand_s {
- target_phys_addr_t target_base;
struct nand_flash_s *nand;
uint8_t ctl;
struct ecc_state_s ecc;
{
struct sl_nand_s *s = (struct sl_nand_s *) opaque;
int ryby;
- addr -= s->target_base;
switch (addr) {
#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
{
struct sl_nand_s *s = (struct sl_nand_s *) opaque;
- addr -= s->target_base;
if (addr == FLASH_FLASHIO)
return ecc_digest(&s->ecc, nand_getio(s->nand)) |
uint32_t value)
{
struct sl_nand_s *s = (struct sl_nand_s *) opaque;
- addr -= s->target_base;
switch (addr) {
case FLASH_ECCCLRR:
};
s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s));
- s->target_base = FLASH_BASE;
s->ctl = 0;
if (size == FLASH_128M)
s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
iomemtype = cpu_register_io_memory(0, sl_readfn,
sl_writefn, s);
- cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
+ cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);
register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
}
uint32_t rtc;
int64_t tick[2];
struct gptm_state *opaque[2];
- uint32_t base;
QEMUTimer *timer[2];
/* The timers have an alternate output used to trigger the ADC. */
qemu_irq trigger;
{
gptm_state *s = (gptm_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* CFG */
return s->config;
gptm_state *s = (gptm_state *)opaque;
uint32_t oldval;
- offset -= s->base;
/* The timers should be disabled before changing the configuration.
We take advantage of this and defer everything until the timer
is enabled. */
gptm_state *s;
s = (gptm_state *)qemu_mallocz(sizeof(gptm_state));
- s->base = base;
s->irq = irq;
s->trigger = trigger;
s->opaque[0] = s->opaque[1] = s;
/* System controller. */
typedef struct {
- uint32_t base;
uint32_t pborctl;
uint32_t ldopctl;
uint32_t int_status;
{
ssys_state *s = (ssys_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x000: /* DID0 */
return s->board->did0;
{
ssys_state *s = (ssys_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x030: /* PBORCTL */
s->pborctl = value & 0xffff;
ssys_state *s;
s = (ssys_state *)qemu_mallocz(sizeof(ssys_state));
- s->base = base;
s->irq = irq;
s->board = board;
/* Most devices come preprogrammed with a MAC address in the user data. */
typedef struct {
i2c_bus *bus;
qemu_irq irq;
- uint32_t base;
uint32_t msa;
uint32_t mcs;
uint32_t mdr;
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* MSA */
return s->msa;
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* MSA */
s->msa = value & 0xff;
int iomemtype;
s = (stellaris_i2c_state *)qemu_mallocz(sizeof(stellaris_i2c_state));
- s->base = base;
s->irq = irq;
s->bus = bus;
typedef struct
{
- uint32_t base;
uint32_t actss;
uint32_t ris;
uint32_t im;
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
/* TODO: Implement this. */
- offset -= s->base;
if (offset >= 0x40 && offset < 0xc0) {
int n;
n = (offset - 0x40) >> 5;
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
/* TODO: Implement this. */
- offset -= s->base;
if (offset >= 0x40 && offset < 0xc0) {
int n;
n = (offset - 0x40) >> 5;
qemu_irq *qi;
s = (stellaris_adc_state *)qemu_mallocz(sizeof(stellaris_adc_state));
- s->base = base;
s->irq = irq;
iomemtype = cpu_register_io_memory(0, stellaris_adc_readfn,
#define SE_TCTL_DUPLEX 0x08
typedef struct {
- uint32_t base;
uint32_t ris;
uint32_t im;
uint32_t rctl;
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
uint32_t val;
- offset -= s->base;
switch (offset) {
case 0x00: /* RIS */
DPRINTF("IRQ status %02x\n", s->ris);
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* IACK */
s->ris &= ~value;
iomemtype = cpu_register_io_memory(0, stellaris_enet_readfn,
stellaris_enet_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->irq = irq;
memcpy(s->macaddr, nd->macaddr, 6);
#define NAND_MODE_ECC_RST 0x60
struct tc6393xb_s {
- target_phys_addr_t target_base;
qemu_irq irq;
qemu_irq *sub_irqs;
struct {
static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) {
struct tc6393xb_s *s = opaque;
- addr -= s->target_base;
switch (addr >> 8) {
case 0:
static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) {
struct tc6393xb_s *s = opaque;
- addr -= s->target_base;
switch (addr >> 8) {
case 0:
};
s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s));
- s->target_base = base;
s->irq = irq;
s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
iomemtype = cpu_register_io_memory(0, tc6393xb_readfn,
tc6393xb_writefn, s);
- cpu_register_physical_memory(s->target_base, 0x10000, iomemtype);
+ cpu_register_physical_memory(base, 0x10000, iomemtype);
if (ds) {
s->ds = ds;
s->vram_addr = qemu_ram_alloc(0x100000);
- cpu_register_physical_memory(s->target_base + 0x100000, 0x100000, s->vram_addr);
+ cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr);
s->scr_width = 480;
s->scr_height = 640;
s->console = graphic_console_init(ds,
typedef struct {
qemu_irq irq;
enum ohci_type type;
- target_phys_addr_t mem_base;
int mem;
int num_ports;
const char *name;
{
OHCIState *ohci = ptr;
- addr -= ohci->mem_base;
-
/* Only aligned reads are allowed on OHCI */
if (addr & 3) {
fprintf(stderr, "usb-ohci: Mis-aligned read\n");
{
OHCIState *ohci = ptr;
- addr -= ohci->mem_base;
-
/* Only aligned reads are allowed on OHCI */
if (addr & 3) {
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
uint32_t addr, uint32_t size, int type)
{
OHCIPCIState *ohci = (OHCIPCIState *)pci_dev;
- ohci->state.mem_base = addr;
cpu_register_physical_memory(addr, size, ohci->state.mem);
}
usb_ohci_init(ohci, num_ports, devfn, irq,
OHCI_TYPE_PXA, "OHCI USB");
- ohci->mem_base = base;
- cpu_register_physical_memory(ohci->mem_base, 0x1000, ohci->mem);
+ cpu_register_physical_memory(base, 0x1000, ohci->mem);
}
typedef struct vpb_sic_state
{
- uint32_t base;
uint32_t level;
uint32_t mask;
uint32_t pic_enable;
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
- offset -= s->base;
switch (offset >> 2) {
case 0: /* STATUS */
return s->level & s->mask;
uint32_t value)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
- offset -= s->base;
switch (offset >> 2) {
case 2: /* ENSET */
if (!s)
return NULL;
qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
- s->base = base;
s->parent = parent;
s->irq = irq;
iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
{
VGAState *s = opaque;
- return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xff;
+ return vga_ioport_read(s, addr >> s->it_shift) & 0xff;
}
static void vga_mm_writeb (void *opaque,
{
VGAState *s = opaque;
- vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xff);
+ vga_ioport_write(s, addr >> s->it_shift, value & 0xff);
}
static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
{
VGAState *s = opaque;
- return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xffff;
+ return vga_ioport_read(s, addr >> s->it_shift) & 0xffff;
}
static void vga_mm_writew (void *opaque,
{
VGAState *s = opaque;
- vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xffff);
+ vga_ioport_write(s, addr >> s->it_shift, value & 0xffff);
}
static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
{
VGAState *s = opaque;
- return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift);
+ return vga_ioport_read(s, addr >> s->it_shift);
}
static void vga_mm_writel (void *opaque,
{
VGAState *s = opaque;
- vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value);
+ vga_ioport_write(s, addr >> s->it_shift, value);
}
static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
{
int s_ioport_ctrl, vga_io_memory;
- s->base_ctrl = ctrl_base;
s->it_shift = it_shift;
s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);
vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */ \
unsigned long bios_offset; \
unsigned int bios_size; \
- target_phys_addr_t base_ctrl; \
int it_shift; \
PCIDevice *pci_dev; \
uint32_t latch; \
static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
{
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
- addr -= s->vram_base;
if (addr < s->fb_size)
return *(uint8_t *) (ds_get_data(s->ds) + addr);
else
static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
{
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
- addr -= s->vram_base;
if (addr < s->fb_size)
return *(uint16_t *) (ds_get_data(s->ds) + addr);
else
static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
{
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
- addr -= s->vram_base;
if (addr < s->fb_size)
return *(uint32_t *) (ds_get_data(s->ds) + addr);
else
uint32_t value)
{
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
- addr -= s->vram_base;
if (addr < s->fb_size)
*(uint8_t *) (ds_get_data(s->ds) + addr) = value;
else
uint32_t value)
{
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
- addr -= s->vram_base;
if (addr < s->fb_size)
*(uint16_t *) (ds_get_data(s->ds) + addr) = value;
else
uint32_t value)
{
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
- addr -= s->vram_base;
if (addr < s->fb_size)
*(uint32_t *) (ds_get_data(s->ds) + addr) = value;
else
/* SCOOP devices */
struct scoop_info_s {
- target_phys_addr_t target_base;
qemu_irq handler[16];
qemu_irq *in;
uint16_t status;
static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
- addr -= s->target_base;
switch (addr) {
case SCOOP_MCR:
static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
- addr -= s->target_base;
value &= 0xffff;
switch (addr) {
qemu_mallocz(sizeof(struct scoop_info_s));
memset(s, 0, sizeof(struct scoop_info_s));
- s->target_base = target_base;
s->status = 0x02;
s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
iomemtype = cpu_register_io_memory(0, scoop_readfn,
scoop_writefn, s);
- cpu_register_physical_memory(s->target_base, 0x1000, iomemtype);
+ cpu_register_physical_memory(target_base, 0x1000, iomemtype);
register_savevm("scoop", instance, 1, scoop_save, scoop_load, s);
return s;
projects / qemu.git / commitdiff