]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
drm/bridge: anx7625: Set HPD irq detect window to 2ms
authorXin Ji <xji@analogixsemi.com>
Sat, 3 Sep 2022 13:08:33 +0000 (21:08 +0800)
committerRobert Foss <robert.foss@linaro.org>
Tue, 6 Sep 2022 12:09:01 +0000 (14:09 +0200)
Some panels trigger HPD irq due to noise, the HPD debounce
may be 1.8ms, exceeding the default irq detect window, ~1.4ms.
This patch set HPD irq detection window to 2ms to
tolerate the HPD noise.

Signed-off-by: Xin Ji <xji@analogixsemi.com>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220903130833.541463-1-xji@analogixsemi.com
drivers/gpu/drm/bridge/analogix/anx7625.c
drivers/gpu/drm/bridge/analogix/anx7625.h

index c74b5df4cadee1f3fcf7629360063105f8a8c3ac..0c323b5a1c99122ab531573dd95b15fa63786f50 100644 (file)
@@ -1440,6 +1440,20 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx)
 
 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
 {
+       int ret;
+
+       /* Set irq detect window to 2ms */
+       ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
+                               HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF);
+       ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
+                                HPD_DET_TIMER_BIT8_15,
+                                (HPD_TIME >> 8) & 0xFF);
+       ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
+                                HPD_DET_TIMER_BIT16_23,
+                                (HPD_TIME >> 16) & 0xFF);
+       if (ret < 0)
+               return ret;
+
        return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
 }
 
index e257a84db9626a7a3c687136cd8620149c8e9004..14f33d6be289fca9f5495e4ee2b2d7ead837fcef 100644 (file)
 #define I2S_SLAVE_MODE 0x08
 #define AUDIO_LAYOUT   0x01
 
+#define HPD_DET_TIMER_BIT0_7   0xea
+#define HPD_DET_TIMER_BIT8_15  0xeb
+#define HPD_DET_TIMER_BIT16_23 0xec
+/* HPD debounce time 2ms for 27M clock */
+#define HPD_TIME               54000
+
 #define AUDIO_CONTROL_REGISTER 0xe6
 #define TDM_TIMING_MODE 0x08