The ForceParWrRMW setting needs to be enabled for ECC, but disabled
when ECC is not enabled.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
bool enable);
void (*get_clockgating_state)(struct amdgpu_device *adev,
u32 *flags);
+ void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
+ bool enable);
};
/* Define the HW IP blocks will be used in driver , add more if necessary */
enum amd_hw_ip_block_type {