drm/xe: Add missing DG2 gt workarounds and tunings

Synchronize with i915 the DG2 gt workarounds as of
commit 4d14d7717f19 ("drm/i915/selftest: Fix ktime_get() and h/w access
order").

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230314003012.2600353-9-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index e55c2f83b353245d8d103d374dfd1547595a834d..f1a9d065120e4d604e0a3bc3fc4b31c285bb9aa3 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -168,7 +168,6 @@
 #define   GAMTLBVEBOX0_CLKGATE_DIS             REG_BIT(16)
 #define   LTCDD_CLKGATE_DIS                    REG_BIT(10)
 
-#define GEN11_SLICE_UNIT_LEVEL_CLKGATE         _MMIO(0x94d4)
 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE          MCR_REG(0x94d4)
 #define   SARBUNIT_CLKGATE_DIS                 (1 << 5)
 #define   RCCUNIT_CLKGATE_DIS                  (1 << 7)
@@ -222,12 +221,28 @@
 #define XEHPC_LNCFMISCCFGREG0                  MCR_REG(0xb01c)
 #define   XEHPC_OVRLSCCC                       REG_BIT(0)
 
+#define XEHP_L3NODEARBCFG                      MCR_REG(0xb0b4)
+#define   XEHP_LNESPARE                                REG_BIT(19)
+
+#define XEHP_L3SCQREG7                         MCR_REG(0xb188)
+#define   BLEND_FILL_CACHING_OPT_DIS           REG_BIT(3)
+
+#define XEHP_MERT_MOD_CTRL                     MCR_REG(0xcf28)
 #define RENDER_MOD_CTRL                                MCR_REG(0xcf2c)
 #define COMP_MOD_CTRL                          MCR_REG(0xcf30)
 #define XEHP_VDBX_MOD_CTRL                     MCR_REG(0xcf34)
 #define XEHP_VEBX_MOD_CTRL                     MCR_REG(0xcf38)
 #define   FORCE_MISS_FTLB                      REG_BIT(3)
 
+#define XEHP_GAMSTLB_CTRL                      MCR_REG(0xcf4c)
+#define   CONTROL_BLOCK_CLKGATE_DIS            REG_BIT(12)
+#define   EGRESS_BLOCK_CLKGATE_DIS             REG_BIT(11)
+#define   TAG_BLOCK_CLKGATE_DIS                        REG_BIT(7)
+
+#define XEHP_GAMCNTRL_CTRL                     MCR_REG(0xcf54)
+#define   INVALIDATION_BROADCAST_MODE_DIS      REG_BIT(12)
+#define   GLOBAL_INVALIDATION_MODE             REG_BIT(2)
+
 #define GEN10_SAMPLER_MODE                     MCR_REG(0xe18c)
 #define   ENABLE_SMALLPL                       REG_BIT(15)
 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB    REG_BIT(9)

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 2861a014c85c437f1e13bbf60387a44a7fa40d1a..47b27dccb38542f87e8d044f243650af20d972f4 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -16,6 +16,10 @@
 #define MCR_REG(x)     _XE_RTP_MCR_REG(x)
 
 static const struct xe_rtp_entry gt_tunings[] = {
+       { XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
+       },
        { XE_RTP_NAME("Tuning: 32B Access Enable"),
          XE_RTP_RULES(PLATFORM(DG2)),
          XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 4fe01168f45f11f47733545259bcb5e1cb20ad68..13c8dbf49cbaca44369cfd564f6365046c3fe355 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -132,6 +132,14 @@ static const struct xe_rtp_entry gt_was[] = {
          XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
          XE_RTP_ACTIONS(SET(GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
        },
+       { XE_RTP_NAME("14012362059"),
+         XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
+         XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))
+       },
+       { XE_RTP_NAME("14012362059"),
+         XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0)),
+         XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))
+       },
        { XE_RTP_NAME("14010948348"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
          XE_RTP_ACTIONS(SET(UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS))
@@ -142,7 +150,7 @@ static const struct xe_rtp_entry gt_was[] = {
        },
        { XE_RTP_NAME("14011371254"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
-         XE_RTP_ACTIONS(SET(GEN11_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS))
+         XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS))
        },
        { XE_RTP_NAME("14011431319"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
@@ -172,6 +180,13 @@ static const struct xe_rtp_entry gt_was[] = {
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
          XE_RTP_ACTIONS(SET(SSMCGCTL9530, RTFUNIT_CLKGATE_DIS))
        },
+       { XE_RTP_NAME("14010680813"),
+         XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
+         XE_RTP_ACTIONS(SET(XEHP_GAMSTLB_CTRL,
+                            CONTROL_BLOCK_CLKGATE_DIS |
+                            EGRESS_BLOCK_CLKGATE_DIS |
+                            TAG_BLOCK_CLKGATE_DIS))
+       },
        { XE_RTP_NAME("14014830051"),
          XE_RTP_RULES(PLATFORM(DG2)),
          XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
@@ -180,6 +195,23 @@ static const struct xe_rtp_entry gt_was[] = {
          XE_RTP_RULES(PLATFORM(DG2)),
          XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE))
        },
+       { XE_RTP_NAME("18018781329"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
+                        SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
+                        SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
+                        SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
+       },
+       { XE_RTP_NAME("1509235366"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
+                            INVALIDATION_BROADCAST_MODE_DIS |
+                            GLOBAL_INVALIDATION_MODE))
+       },
+       { XE_RTP_NAME("14010648519"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(SET(XEHP_L3NODEARBCFG, XEHP_LNESPARE))
+       },
 
        /* PVC */