drm/i915/gt: Replace I915_READ with intel_uncore_read

Get rid of the last remaining I915_READ in gt/ and make gt-land
the first I915_READ-free happy island.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191205164422.727968-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 01765a7ec18f0b862ae6b54a6413b18dc79fb1f9..c294ea80605e68637cf75ebb71754dbc919a73dd 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -296,7 +296,7 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
 struct i915_request *
 intel_engine_find_active_request(struct intel_engine_cs *engine);
 
-u32 intel_engine_context_size(struct drm_i915_private *i915, u8 class);
+u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index df3369c3f330d68241851c04516a91dc1712c9e4..49473c25916cc9cd4f27a3c5adbe2d54e46724ec 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -141,7 +141,7 @@ static const struct engine_info intel_engines[] = {
 
 /**
  * intel_engine_context_size() - return the size of the context for an engine
- * @dev_priv: i915 device private
+ * @gt: the gt
  * @class: engine class
  *
  * Each engine class may require a different amount of space for a context
@@ -153,17 +153,18 @@ static const struct engine_info intel_engines[] = {
  * in LRC mode, but does not include the "shared data page" used with
  * GuC submission. The caller should account for this if using the GuC.
  */
-u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
+u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
 {
+       struct intel_uncore *uncore = gt->uncore;
        u32 cxt_size;
 
        BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
 
        switch (class) {
        case RENDER_CLASS:
-               switch (INTEL_GEN(dev_priv)) {
+               switch (INTEL_GEN(gt->i915)) {
                default:
-                       MISSING_CASE(INTEL_GEN(dev_priv));
+                       MISSING_CASE(INTEL_GEN(gt->i915));
                        return DEFAULT_LR_CONTEXT_RENDER_SIZE;
                case 12:
                case 11:
@@ -175,14 +176,14 @@ u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
                case 8:
                        return GEN8_LR_CONTEXT_RENDER_SIZE;
                case 7:
-                       if (IS_HASWELL(dev_priv))
+                       if (IS_HASWELL(gt->i915))
                                return HSW_CXT_TOTAL_SIZE;
 
-                       cxt_size = I915_READ(GEN7_CXT_SIZE);
+                       cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
                        return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
                                        PAGE_SIZE);
                case 6:
-                       cxt_size = I915_READ(CXT_SIZE);
+                       cxt_size = intel_uncore_read(uncore, CXT_SIZE);
                        return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
                                        PAGE_SIZE);
                case 5:
@@ -197,9 +198,9 @@ u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
                         * minimum allocation anyway so it should all come
                         * out in the wash.
                         */
-                       cxt_size = I915_READ(CXT_SIZE) + 1;
+                       cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
                        DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
-                                        INTEL_GEN(dev_priv),
+                                        INTEL_GEN(gt->i915),
                                         cxt_size * 64,
                                         cxt_size - 1);
                        return round_up(cxt_size * 64, PAGE_SIZE);
@@ -216,7 +217,7 @@ u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
        case VIDEO_DECODE_CLASS:
        case VIDEO_ENHANCEMENT_CLASS:
        case COPY_ENGINE_CLASS:
-               if (INTEL_GEN(dev_priv) < 8)
+               if (INTEL_GEN(gt->i915) < 8)
                        return 0;
                return GEN8_LR_CONTEXT_OTHER_SIZE;
        }
@@ -324,8 +325,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
         */
        engine->destroy = (typeof(engine->destroy))kfree;
 
-       engine->context_size = intel_engine_context_size(gt->i915,
-                                                        engine->class);
+       engine->context_size = intel_engine_context_size(gt, engine->class);
        if (WARN_ON(engine->context_size > BIT(20)))
                engine->context_size = 0;
        if (engine->context_size)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index ca6674b8e00c01dc4d09fd4a0b5588242336cdb2..05ca90456a2ca8e38423f047c62a84dee236cbd4 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -93,7 +93,8 @@ static void __guc_ads_init(struct intel_guc *guc)
                 */
                blob->ads.golden_context_lrca[engine_class] = 0;
                blob->ads.eng_state_size[engine_class] =
-                       intel_engine_context_size(dev_priv, engine_class) -
+                       intel_engine_context_size(guc_to_gt(guc),
+                                                 engine_class) -
                        skipped_size;
        }