]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/commitdiff
Update the initialization sequence to enable DB410c.
authorYin, Fengwei <fengwei.yin@linaro.org>
Sun, 13 Sep 2015 14:00:06 +0000 (22:00 +0800)
committerKhalid Elmously <khalid.elmously@canonical.com>
Wed, 14 Mar 2018 02:42:09 +0000 (02:42 +0000)
The soc on DB410c board is not same as MTP8916. It doesn't support
48M operation frequency.

Signed-off-by: Yin, Fengwei <fengwei.yin@linaro.org>
drivers/net/wireless/ath/wcn36xx/wcnss_core.c
drivers/net/wireless/ath/wcn36xx/wcnss_core.h

index 66e31440f3c34d1cbdb36afa0ea334e0bc158ed2..b3e4b826d887c6de13492c4b1412f2cb341fa47e 100644 (file)
@@ -15,7 +15,8 @@
 static int wcnss_core_config(struct platform_device *pdev, void __iomem *base)
 {
        int ret = 0;
-       u32 value;
+       u32 value, iris_read = INVALID_IRIS_REG;
+       int clk_48m = 0;
 
        value = readl_relaxed(base + SPARE_OFFSET);
        value |= WCNSS_FW_DOWNLOAD_ENABLE;
@@ -24,11 +25,34 @@ static int wcnss_core_config(struct platform_device *pdev, void __iomem *base)
        writel_relaxed(0, base + PMU_OFFSET);
        value = readl_relaxed(base + PMU_OFFSET);
        value |= WCNSS_PMU_CFG_GC_BUS_MUX_SEL_TOP |
-                       WCNSS_PMU_CFG_IRIS_XO_EN;
+               WCNSS_PMU_CFG_IRIS_XO_EN;
        writel_relaxed(value, base + PMU_OFFSET);
 
-       value &= ~(WCNSS_PMU_CFG_IRIS_XO_MODE);
-       value |= WCNSS_PMU_CFG_IRIS_XO_MODE_48;
+       iris_read_v = readl_relaxed(base + IRIS_REG_OFFSET);
+       pr_info("iris_read_v: 0x%x\n", iris_read_v);
+
+       iris_read_v &= 0xffff;
+       iris_read_v |= 0x04;
+       writel_relaxed(iris_read_v, base + IRIS_REG_OFFSET);
+
+       value = readl_relaxed(base + PMU_OFFSET);
+       value |= WCNSS_PMU_CFG_IRIS_XO_READ;
+       writel_relaxed(value, base + PMU_OFFSET);
+
+       while (readl_relaxed(base + PMU_OFFSET) &
+                       WCNSS_PMU_CFG_IRIS_XO_READ_STS)
+               cpu_relax();
+
+       iris_read_v = readl_relaxed(base + 0x1134);
+       pr_info("wcnss: IRIS Reg: 0x%08x\n", iris_read_v);
+       clk_48m = (iris_read_v >> 30) ? 0 : 1;
+       value &= ~WCNSS_PMU_CFG_IRIS_XO_READ;
+
+       /* XO_MODE[b2:b1]. Clear implies 19.2MHz */
+       value &= ~WCNSS_PMU_CFG_IRIS_XO_MODE;
+
+       if (clk_48m)
+               value |= WCNSS_PMU_CFG_IRIS_XO_MODE_48;
 
        writel_relaxed(value, base + PMU_OFFSET);
 
index d81fc472f62fc29d478aafaef5f241048657a568..4c3517b99c30379bd7bce9f14870180cd5160ab3 100644 (file)
@@ -3,6 +3,9 @@
 
 #define        PMU_OFFSET      0x1004
 #define        SPARE_OFFSET    0x1088
+#define IRIS_REG_OFFSET 0x1134
+
+#define INVALID_IRIS_REG        0xbaadbaad
 
 #define WCNSS_PMU_CFG_IRIS_XO_CFG          BIT(3)
 #define WCNSS_PMU_CFG_IRIS_XO_EN           BIT(4)