+++ /dev/null
-Ingenic XBurst pin controller
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
-be used as GPIOs, multiplexed device functions are configured within the
-GPIO port configuration registers and it is typical to refer to pins using the
-naming scheme "PxN" where x is a character identifying the GPIO port with
-which the pin is associated and N is an integer from 0 to 31 identifying the
-pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
-PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
-contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
-jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
-
-
-Required properties:
---------------------
-
- - compatible: One of:
- - "ingenic,jz4740-pinctrl"
- - "ingenic,jz4725b-pinctrl"
- - "ingenic,jz4760-pinctrl"
- - "ingenic,jz4760b-pinctrl"
- - "ingenic,jz4770-pinctrl"
- - "ingenic,jz4780-pinctrl"
- - "ingenic,x1000-pinctrl"
- - "ingenic,x1000e-pinctrl"
- - "ingenic,x1500-pinctrl"
- - "ingenic,x1830-pinctrl"
- - reg: Address range of the pinctrl registers.
-
-
-Required properties for sub-nodes (GPIO chips):
------------------------------------------------
-
- - compatible: Must contain one of:
- - "ingenic,jz4740-gpio"
- - "ingenic,jz4760-gpio"
- - "ingenic,jz4770-gpio"
- - "ingenic,jz4780-gpio"
- - "ingenic,x1000-gpio"
- - "ingenic,x1830-gpio"
- - reg: The GPIO bank number.
- - interrupt-controller: Marks the device node as an interrupt controller.
- - interrupts: Interrupt specifier for the controllers interrupt.
- - #interrupt-cells: Should be 2. Refer to
- ../interrupt-controller/interrupts.txt for more details.
- - gpio-controller: Marks the device node as a GPIO controller.
- - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
- cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
- GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
- ../gpio/gpio.txt for more details.
-
-
-Example:
---------
-
-pinctrl: pin-controller@10010000 {
- compatible = "ingenic,jz4740-pinctrl";
- reg = <0x10010000 0x400>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpa: gpio@0 {
- compatible = "ingenic,jz4740-gpio";
- reg = <0>;
-
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&intc>;
- interrupts = <28>;
- };
-};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs pin controller devicetree bindings
+
+description: >
+ Please refer to pinctrl-bindings.txt in this directory for details of the
+ common pinctrl bindings used by client devices, including the meaning of the
+ phrase "pin configuration node".
+
+ For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
+ may be used as GPIOs, multiplexed device functions are configured within the
+ GPIO port configuration registers and it is typical to refer to pins using the
+ naming scheme "PxN" where x is a character identifying the GPIO port with
+ which the pin is associated and N is an integer from 0 to 31 identifying the
+ pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
+ and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
+ contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
+ JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
+ pins.
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+properties:
+ nodename:
+ pattern: "^pinctrl@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4740-pinctrl
+ - ingenic,jz4725b-pinctrl
+ - ingenic,jz4760-pinctrl
+ - ingenic,jz4770-pinctrl
+ - ingenic,jz4780-pinctrl
+ - ingenic,x1000-pinctrl
+ - ingenic,x1500-pinctrl
+ - ingenic,x1830-pinctrl
+ - items:
+ - const: ingenic,jz4760b-pinctrl
+ - const: ingenic,jz4760-pinctrl
+ - items:
+ - const: ingenic,x1000e-pinctrl
+ - const: ingenic,x1000-pinctrl
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^gpio@[0-9]$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - ingenic,jz4740-gpio
+ - ingenic,jz4725b-gpio
+ - ingenic,jz4760-gpio
+ - ingenic,jz4770-gpio
+ - ingenic,jz4780-gpio
+ - ingenic,x1000-gpio
+ - ingenic,x1500-gpio
+ - ingenic,x1830-gpio
+
+ reg:
+ items:
+ - description: The GPIO bank number
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+ description:
+ Refer to ../interrupt-controller/interrupts.txt for more details.
+
+ interrupts:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties:
+ anyOf:
+ - type: object
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ properties:
+ phandle: true
+ function: true
+ groups: true
+ pins: true
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-down: true
+ output-low: true
+ output-high: true
+ additionalProperties: false
+
+ - type: object
+ properties:
+ phandle: true
+ additionalProperties:
+ type: object
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ properties:
+ phandle: true
+ function: true
+ groups: true
+ pins: true
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-down: true
+ output-low: true
+ output-high: true
+ additionalProperties: false
+
+examples:
+ - |
+ pin-controller@10010000 {
+ compatible = "ingenic,jz4770-pinctrl";
+ reg = <0x10010000 0x600>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@0 {
+ compatible = "ingenic,jz4770-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT6779 Pin Controller Device Tree Bindings
+
+maintainers:
+ - Andy Teng <andy.teng@mediatek.com>
+
+description: |+
+ The pin controller node should be the child of a syscon node with the
+ required property:
+ - compatible: "syscon"
+
+properties:
+ compatible:
+ const: mediatek,mt6779-pinctrl
+
+ reg:
+ minItems: 9
+ maxItems: 9
+
+ reg-names:
+ items:
+ - const: "gpio"
+ - const: "iocfg_rm"
+ - const: "iocfg_br"
+ - const: "iocfg_lm"
+ - const: "iocfg_lb"
+ - const: "iocfg_rt"
+ - const: "iocfg_lt"
+ - const: "iocfg_tl"
+ - const: "eint"
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ Number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+
+ gpio-ranges:
+ minItems: 1
+ maxItems: 5
+ description: |
+ GPIO valid number range.
+
+ interrupt-controller: true
+
+ interrupts:
+ maxItems: 1
+ description: |
+ Specifies the summary IRQ.
+
+ "#interrupt-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - interrupt-controller
+ - interrupts
+ - "#interrupt-cells"
+
+patternProperties:
+ '-[0-9]*$':
+ type: object
+ patternProperties:
+ '-pins*$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to muxer
+ configuration, pullups, drive strength, input enable/disable and input schmitt.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pinmux:
+ description:
+ integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are defined
+ as macros in boot/dts/<soc>-pinfunc.h directly.
+
+ bias-disable: true
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ input-enable: true
+
+ input-disable: true
+
+ output-low: true
+
+ output-high: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ mediatek,pull-up-adv:
+ description: |
+ Pull up setings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+
+ mediatek,pull-down-adv:
+ description: |
+ Pull down settings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+
+ required:
+ - pinmux
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt6779-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11c20000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11e70000 0 0x1000>,
+ <0 0x11ea0000 0 0x1000>,
+ <0 0x11f20000 0 0x1000>,
+ <0 0x11f30000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio", "iocfg_rm",
+ "iocfg_br", "iocfg_lm",
+ "iocfg_lb", "iocfg_rt",
+ "iocfg_lt", "iocfg_tl",
+ "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 210>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+
+ mmc0_pins_default: mmc0-0 {
+ cmd-dat-pins {
+ pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
+ input-enable;
+ mediatek,pull-up-adv = <1>;
+ };
+ clk-pins {
+ pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
+ mediatek,pull-down-adv = <2>;
+ };
+ rst-pins {
+ pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
+ mediatek,pull-up-adv = <0>;
+ };
+ };
+ };
+
+ mmc0 {
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-names = "default";
+ };
+ };
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength.
+ pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
+ drive-strength.
Non-empty subnodes must specify the 'pins' property.
Note that not all properties are valid for all pins.
"qcom,pmi8994-gpio"
"qcom,pmi8998-gpio"
"qcom,pms405-gpio"
+ "qcom,pm660-gpio"
+ "qcom,pm660l-gpio"
"qcom,pm8150-gpio"
"qcom,pm8150b-gpio"
"qcom,pm6150-gpio"
- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
- "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.
- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
+ - "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
+++ /dev/null
-Renesas RZ/A2 combined Pin and GPIO controller
-
-The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
-Pin multiplexing and GPIO configuration is performed on a per-pin basis.
-Each port features up to 8 pins, each of them configurable for GPIO
-function (port mode) or in alternate function mode.
-Up to 8 different alternate function modes exist for each single pin.
-
-Pin controller node
--------------------
-
-Required properties:
- - compatible: shall be:
- - "renesas,r7s9210-pinctrl": for RZ/A2M
- - reg
- Address base and length of the memory area where the pin controller
- hardware is mapped to.
- - gpio-controller
- This pin controller also controls pins as GPIO
- - #gpio-cells
- Must be 2
- - gpio-ranges
- Expresses the total number of GPIO ports/pins in this SoC
-
-Example: Pin controller node for RZ/A2M SoC (r7s9210)
-
- pinctrl: pin-controller@fcffe000 {
- compatible = "renesas,r7s9210-pinctrl";
- reg = <0xfcffe000 0x1000>;
-
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 0 176>;
- };
-
-Sub-nodes
----------
-
-The child nodes of the pin controller designate pins to be used for
-specific peripheral functions or as GPIO.
-
-- Pin multiplexing sub-nodes:
- A pin multiplexing sub-node describes how to configure a set of
- (or a single) pin in some desired alternate function mode.
- The values for the pinmux properties are a combination of port name, pin
- number and the desired function index. Use the RZA2_PINMUX macro located
- in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
- For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h
- to express the desired port pin.
-
- Required properties:
- - pinmux:
- integer array representing pin number and pin multiplexing configuration.
- When a pin has to be configured in alternate function mode, use this
- property to identify the pin by its global index, and provide its
- alternate function configuration number along with it.
- When multiple pins are required to be configured as part of the same
- alternate function they shall be specified as members of the same
- argument list of a single "pinmux" property.
- Helper macros to ease assembling the pin index from its position
- (port where it sits on and pin number) and alternate function identifier
- are provided by the pin controller header file at:
- <dt-bindings/pinctrl/r7s9210-pinctrl.h>
- Integers values in "pinmux" argument list are assembled as:
- ((PORT * 8 + PIN) | MUX_FUNC << 16)
-
- Example: Board specific pins configuration
-
- &pinctrl {
- /* Serial Console */
- scif4_pins: serial4 {
- pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
- <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
- };
- };
-
- Example: Assigning a GPIO:
-
- leds {
- status = "okay";
- compatible = "gpio-leds";
-
- led0 {
- /* P6_0 */
- gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/A2 combined Pin and GPIO controller
+
+maintainers:
+ - Chris Brandt <chris.brandt@renesas.com>
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
+ controller.
+ Pin multiplexing and GPIO configuration is performed on a per-pin basis.
+ Each port features up to 8 pins, each of them configurable for GPIO function
+ (port mode) or in alternate function mode.
+ Up to 8 different alternate function modes exist for each single pin.
+
+properties:
+ compatible:
+ const: "renesas,r7s9210-pinctrl" # RZ/A2M
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+ description:
+ The first cell contains the global GPIO port index, constructed using the
+ RZA2_PIN() helper macro in r7s9210-pinctrl.h.
+ E.g. "RZA2_PIN(PORT6, 0)" for P6_0.
+
+ gpio-ranges:
+ maxItems: 1
+
+patternProperties:
+ "^.*$":
+ if:
+ type: object
+ then:
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+ description:
+ The child nodes of the pin controller designate pins to be used for
+ specific peripheral functions or as GPIO.
+
+ A pin multiplexing sub-node describes how to configure a set of
+ (or a single) pin in some desired alternate function mode.
+ The values for the pinmux properties are a combination of port name,
+ pin number and the desired function index. Use the RZA2_PINMUX macro
+ located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
+ define these.
+ For assigning GPIO pins, use the macro RZA2_PIN also in
+ to express the desired port pin.
+
+ properties:
+ phandle: true
+
+ pinmux:
+ description:
+ Values are constructed from GPIO port number, pin number, and
+ alternate function configuration number using the RZA2_PINMUX()
+ helper macro in r7s9210-pinctrl.h.
+
+ required:
+ - pinmux
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
+ pinctrl: pin-controller@fcffe000 {
+ compatible = "renesas,r7s9210-pinctrl";
+ reg = <0xfcffe000 0x1000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 176>;
+
+ /* Serial Console */
+ scif4_pins: serial4 {
+ pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
+ <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
+ };
+ };
am33xx_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x238>;
- #pinctrl-cells = <1>;
+ #pinctrl-cells = <2>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
* @pctrldev: pinctrl handle
* @chip: gpio chip
* @lock: spinlock to protect registers
+ * @clk: clock control
* @soc: reference to soc_data
* @base: pinctrl register base address
+ * @irq_chip: IRQ chip information
+ * @num_irq: number of possible interrupts
+ * @irq: interrupt numbers
*/
struct owl_pinctrl {
struct device *dev;
#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
#define SCU694 0x694 /* Multi-function Pin Control #25 */
+#define SCU69C 0x69C /* Multi-function Pin Control #27 */
#define SCUC20 0xC20 /* PCIE configuration Setting Control */
#define ASPEED_G6_NR_PINS 256
#define Y23 127
SIG_EXPR_LIST_DECL_SEMG(Y23, PWM15, PWM15G1, PWM15, SIG_DESC_SET(SCU41C, 31));
SIG_EXPR_LIST_DECL_SESG(Y23, THRUOUT3, THRU3, SIG_DESC_SET(SCU4BC, 31));
-PIN_DECL_2(Y23, GPIOP7, PWM15, THRUOUT3);
+SIG_EXPR_LIST_DECL_SESG(Y23, HEARTBEAT, HEARTBEAT, SIG_DESC_SET(SCU69C, 31));
+PIN_DECL_3(Y23, GPIOP7, PWM15, THRUOUT3, HEARTBEAT);
GROUP_DECL(PWM15G1, Y23);
FUNC_DECL_2(PWM15, PWM15G0, PWM15G1);
FUNC_GROUP_DECL(THRU3, AB24, Y23);
+FUNC_GROUP_DECL(HEARTBEAT, Y23);
#define AA25 128
SSSF_PIN_DECL(AA25, GPIOQ0, TACH0, SIG_DESC_SET(SCU430, 0));
ASPEED_PINCTRL_GROUP(GPIU5),
ASPEED_PINCTRL_GROUP(GPIU6),
ASPEED_PINCTRL_GROUP(GPIU7),
+ ASPEED_PINCTRL_GROUP(HEARTBEAT),
ASPEED_PINCTRL_GROUP(HVI3C3),
ASPEED_PINCTRL_GROUP(HVI3C4),
ASPEED_PINCTRL_GROUP(I2C1),
ASPEED_PINCTRL_FUNC(GPIU5),
ASPEED_PINCTRL_FUNC(GPIU6),
ASPEED_PINCTRL_FUNC(GPIU7),
+ ASPEED_PINCTRL_FUNC(HEARTBEAT),
ASPEED_PINCTRL_FUNC(I2C1),
ASPEED_PINCTRL_FUNC(I2C10),
ASPEED_PINCTRL_FUNC(I2C11),
{
int ret;
+ pr_debug("Enabling signal %s for %s\n", expr->signal,
+ expr->function);
+
ret = aspeed_sig_expr_eval(ctx, expr, true);
if (ret < 0)
return ret;
{
int ret;
+ pr_debug("Disabling signal %s for %s\n", expr->signal,
+ expr->function);
+
ret = aspeed_sig_expr_eval(ctx, expr, true);
if (ret < 0)
return ret;
const struct aspeed_sig_expr **funcs;
const struct aspeed_sig_expr ***prios;
- pr_debug("Muxing pin %d for %s\n", pin, pfunc->name);
+ pr_debug("Muxing pin %s for %s\n", pdesc->name, pfunc->name);
if (!pdesc)
return -EINVAL;
ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
if (ret)
return ret;
+
+ pr_debug("Muxed pin %s as %s for %s\n", pdesc->name, expr->signal,
+ expr->function);
}
return 0;
if (!prios)
return -ENXIO;
+ pr_debug("Muxing pin %s for GPIO\n", pdesc->name);
+
/* Disable any functions of higher priority than GPIO */
while ((funcs = *prios)) {
if (aspeed_gpio_in_exprs(funcs))
* lowest-priority signal type. As such it has no associated
* expression.
*/
- if (!expr)
+ if (!expr) {
+ pr_debug("Muxed pin %s as GPIO\n", pdesc->name);
return 0;
+ }
/*
* If GPIO is not the lowest priority signal type, assume there is only
* one expression defined to enable the GPIO function
*/
- return aspeed_sig_expr_enable(&pdata->pinmux, expr);
+ ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
+ if (ret)
+ return ret;
+
+ pr_debug("Muxed pin %s as %s\n", pdesc->name, expr->signal);
+
+ return 0;
}
int aspeed_pinctrl_probe(struct platform_device *pdev,
#define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010
#define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4
-/**
+/*
* bcm281xx_pin_type - types of pin register
*/
enum bcm281xx_pin_type {
static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;
static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;
-/**
+/*
* bcm281xx_pin_function- define pin function
*/
struct bcm281xx_pin_function {
const unsigned ngroups;
};
-/**
+/*
* bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
* @reg_base - base of pinctrl registers
*/
* iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
* Iproc GPIO register
*
- * @iproc_gpio: Iproc GPIO device
+ * @chip: Iproc GPIO device
* @reg: register offset
* @gpio: GPIO pin
* @set: set or clear
level &= readl(chip->base + NSP_GPIO_INT_MASK);
int_bits = level | event;
- for_each_set_bit(bit, &int_bits, gc->ngpio) {
- /*
- * Clear the interrupt before invoking the
- * handler, so we do not leave any window
- */
- writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
+ for_each_set_bit(bit, &int_bits, gc->ngpio)
generic_handle_irq(
irq_linear_revmap(gc->irq.domain, bit));
- }
}
return int_bits ? IRQ_HANDLED : IRQ_NONE;
trigger_type = irq_get_trigger_type(d->irq);
if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
- nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val);
+ writel(val, chip->base + NSP_GPIO_EVENT);
}
/*
nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
+
+ if (type & IRQ_TYPE_EDGE_BOTH)
+ irq_set_handler_locked(d, handle_edge_irq);
+ else
+ irq_set_handler_locked(d, handle_level_irq);
+
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
- girq->handler = handle_simple_irq;
+ girq->handler = handle_bad_irq;
}
ret = devm_gpiochip_add_data(dev, gc, chip);
#include <linux/pinctrl/machine.h>
#ifdef CONFIG_GPIOLIB
+#include "../gpio/gpiolib.h"
#include <asm-generic/gpio.h>
#endif
/**
* pin_get_name_from_id() - look up a pin name from a pin id
* @pctldev: the pin control device to lookup the pin on
- * @name: the name of the pin to look up
+ * @pin: pin number/id to look up
*/
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
{
/**
* pinctrl_generic_get_group() - returns a pin group based on the number
* @pctldev: pin controller device
- * @gselector: group number
+ * @selector: group number
*/
struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev,
unsigned int selector)
}
/**
- * struct devm_pinctrl_get() - Resource managed pinctrl_get()
+ * devm_pinctrl_get() - Resource managed pinctrl_get()
* @dev: the device to obtain the handle for
*
* If there is a need to explicitly destroy the returned struct pinctrl,
/**
* pinctrl_unregister_mappings() - unregister a set of pin controller mappings
- * @maps: the pincontrol mappings table passed to pinctrl_register_mappings()
+ * @map: the pincontrol mappings table passed to pinctrl_register_mappings()
* when registering the mappings.
*/
void pinctrl_unregister_mappings(const struct pinctrl_map *map)
struct pinctrl_dev *pctldev = s->private;
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
unsigned i, pin;
+ struct pinctrl_gpio_range *range;
+ unsigned int gpio_num;
+ struct gpio_chip *chip;
seq_printf(s, "registered pins: %d\n", pctldev->desc->npins);
seq_printf(s, "pin %d (%s) ", pin, desc->name);
+#ifdef CONFIG_GPIOLIB
+ gpio_num = 0;
+ list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+ if ((pin >= range->pin_base) &&
+ (pin < (range->pin_base + range->npins))) {
+ gpio_num = range->base + (pin - range->pin_base);
+ break;
+ }
+ }
+ chip = gpio_to_chip(gpio_num);
+ if (chip && chip->gpiodev && chip->gpiodev->base)
+ seq_printf(s, "%u:%s ", gpio_num -
+ chip->gpiodev->base, chip->label);
+ else
+ seq_puts(s, "0:? ");
+#endif
+
/* Driver-specific info per pin */
if (ops->pin_dbg_show)
ops->pin_dbg_show(pctldev, s, pin);
* @dev: parent device for this pin controller
* @pctldesc: descriptor for this pin controller
* @driver_data: private pin controller data for this pin controller
+ * @pctldev: pin controller device
*
- * Returns an error pointer if pincontrol register failed. Otherwise
- * it returns valid pinctrl handle.
+ * Returns zero on success or an error number on failure.
*
* The pinctrl device will be automatically released when the device is unbound.
*/
* struct pinctrl_dt_map - mapping table chunk parsed from device tree
* @node: list node for struct pinctrl's @dt_maps field
* @pctldev: the pin controller that allocated this struct, and will free it
- * @maps: the mapping table entries
+ * @map: the mapping table entries
+ * @num_maps: number of mapping table entries
*/
struct pinctrl_dt_map {
struct list_head node;
* @np: pointer to device node with the property
* @list_name: property that contains the list
* @index: index within the list
- * @out_arts: entries in the list pointed by index
+ * @out_args: entries in the list pointed by index
*
* Finds the selected element in a pinctrl array consisting of an index
* within the controller and a number of u32 entries specified for each
Say Y here to enable the imx7ulp pinctrl driver
config PINCTRL_IMX8MM
- bool "IMX8MM pinctrl driver"
+ tristate "IMX8MM pinctrl driver"
depends on ARCH_MXC
select PINCTRL_IMX
help
Say Y here to enable the imx8mm pinctrl driver
config PINCTRL_IMX8MN
- bool "IMX8MN pinctrl driver"
+ tristate "IMX8MN pinctrl driver"
depends on ARCH_MXC
select PINCTRL_IMX
help
Say Y here to enable the imx8mn pinctrl driver
config PINCTRL_IMX8MP
- bool "IMX8MP pinctrl driver"
+ tristate "IMX8MP pinctrl driver"
depends on ARCH_MXC
select PINCTRL_IMX
help
Say Y here to enable the imx8mp pinctrl driver
config PINCTRL_IMX8MQ
- bool "IMX8MQ pinctrl driver"
+ tristate "IMX8MQ pinctrl driver"
depends on ARCH_MXC
select PINCTRL_IMX
help
Say Y here to enable the imx8mq pinctrl driver
config PINCTRL_IMX8QM
- bool "IMX8QM pinctrl driver"
+ tristate "IMX8QM pinctrl driver"
depends on IMX_SCU && ARCH_MXC && ARM64
select PINCTRL_IMX_SCU
help
Say Y here to enable the imx8qm pinctrl driver
config PINCTRL_IMX8QXP
- bool "IMX8QXP pinctrl driver"
+ tristate "IMX8QXP pinctrl driver"
depends on IMX_SCU && ARCH_MXC && ARM64
select PINCTRL_IMX_SCU
help
Say Y here to enable the imx8qxp pinctrl driver
config PINCTRL_IMX8DXL
- bool "IMX8DXL pinctrl driver"
+ tristate "IMX8DXL pinctrl driver"
depends on IMX_SCU && ARCH_MXC && ARM64
select PINCTRL_IMX_SCU
help
return pinctrl_enable(ipctl->pctl);
}
+EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
{
SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
imx_pinctrl_resume)
};
+EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
{ .compatible = "fsl,imx8dxl-iomuxc", },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, imx8dxl_pinctrl_of_match);
static int imx8dxl_pinctrl_probe(struct platform_device *pdev)
{
return platform_driver_register(&imx8dxl_pinctrl_driver);
}
arch_initcall(imx8dxl_pinctrl_init);
+
+MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
+MODULE_DESCRIPTION("NXP i.MX8DXL pinctrl driver");
+MODULE_LICENSE("GPL v2");
#include <linux/err.h>
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
{ .compatible = "fsl,imx8mm-iomuxc", .data = &imx8mm_pinctrl_info, },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, imx8mm_pinctrl_of_match);
static int imx8mm_pinctrl_probe(struct platform_device *pdev)
{
return platform_driver_register(&imx8mm_pinctrl_driver);
}
arch_initcall(imx8mm_pinctrl_init);
+
+MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
+MODULE_DESCRIPTION("NXP i.MX8MM pinctrl driver");
+MODULE_LICENSE("GPL v2");
#include <linux/err.h>
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
{ .compatible = "fsl,imx8mn-iomuxc", .data = &imx8mn_pinctrl_info, },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, imx8mn_pinctrl_of_match);
static int imx8mn_pinctrl_probe(struct platform_device *pdev)
{
return platform_driver_register(&imx8mn_pinctrl_driver);
}
arch_initcall(imx8mn_pinctrl_init);
+
+MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
+MODULE_DESCRIPTION("NXP i.MX8MN pinctrl driver");
+MODULE_LICENSE("GPL v2");
#include <linux/err.h>
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
{ .compatible = "fsl,imx8mp-iomuxc", .data = &imx8mp_pinctrl_info, },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, imx8mp_pinctrl_of_match);
static int imx8mp_pinctrl_probe(struct platform_device *pdev)
{
return platform_driver_register(&imx8mp_pinctrl_driver);
}
arch_initcall(imx8mp_pinctrl_init);
+
+MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
+MODULE_DESCRIPTION("NXP i.MX8MP pinctrl driver");
+MODULE_LICENSE("GPL v2");
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
{ .compatible = "fsl,imx8mq-iomuxc", .data = &imx8mq_pinctrl_info, },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, imx8mq_pinctrl_of_match);
static int imx8mq_pinctrl_probe(struct platform_device *pdev)
{
return platform_driver_register(&imx8mq_pinctrl_driver);
}
arch_initcall(imx8mq_pinctrl_init);
+
+MODULE_AUTHOR("Lucas Stach <l.stach@pengutronix.de>");
+MODULE_DESCRIPTION("NXP i.MX8MQ pinctrl driver");
+MODULE_LICENSE("GPL v2");
{ .compatible = "fsl,imx8qm-iomuxc", },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, imx8qm_pinctrl_of_match);
static int imx8qm_pinctrl_probe(struct platform_device *pdev)
{
return platform_driver_register(&imx8qm_pinctrl_driver);
}
arch_initcall(imx8qm_pinctrl_init);
+
+MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
+MODULE_DESCRIPTION("NXP i.MX8QM pinctrl driver");
+MODULE_LICENSE("GPL v2");
{ .compatible = "fsl,imx8qxp-iomuxc", },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, imx8qxp_pinctrl_of_match);
static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
{
return platform_driver_register(&imx8qxp_pinctrl_driver);
}
arch_initcall(imx8qxp_pinctrl_init);
+
+MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
+MODULE_DESCRIPTION("NXP i.MX8QXP pinctrl driver");
+MODULE_LICENSE("GPL v2");
{
return imx_scu_get_handle(&pinctrl_ipc_handle);
}
+EXPORT_SYMBOL_GPL(imx_pinctrl_sc_ipc_init);
int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *config)
return 0;
}
+EXPORT_SYMBOL_GPL(imx_pinconf_get_scu);
int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *configs, unsigned num_configs)
return ret;
}
+EXPORT_SYMBOL_GPL(imx_pinconf_set_scu);
void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
pin_scu->mux_mode, pin_scu->config);
}
+EXPORT_SYMBOL_GPL(imx_pinctrl_parse_pin_scu);
This pinctrl driver provides an interface that allows configuring
of Intel Denverton SoC pins and using them as GPIOs.
+config PINCTRL_EMMITSBURG
+ tristate "Intel Emmitsburg pinctrl and GPIO driver"
+ depends on ACPI
+ select PINCTRL_INTEL
+ help
+ This pinctrl driver provides an interface that allows configuring
+ of Intel Emmitsburg pins and using them as GPIOs.
+
config PINCTRL_GEMINILAKE
tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
depends on ACPI
obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o
obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o
+obj-$(CONFIG_PINCTRL_EMMITSBURG) += pinctrl-emmitsburg.o
obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o
switch (irqd_get_trigger_type(d)) {
case IRQ_TYPE_LEVEL_HIGH:
value |= BYT_TRIG_LVL;
- /* fall through */
+ fallthrough;
case IRQ_TYPE_EDGE_RISING:
value |= BYT_TRIG_POS;
break;
case IRQ_TYPE_LEVEL_LOW:
value |= BYT_TRIG_LVL;
- /* fall through */
+ fallthrough;
case IRQ_TYPE_EDGE_FALLING:
value |= BYT_TRIG_NEG;
break;
.driver = {
.name = "byt_gpio",
.pm = &byt_gpio_pm_ops,
+ .acpi_match_table = byt_gpio_acpi_match,
.suppress_bind_attrs = true,
-
- .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
},
};
/*
* Cherryview/Braswell pinctrl driver
*
- * Copyright (C) 2014, Intel Corporation
+ * Copyright (C) 2014, 2020 Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This driver is based on the original Cherryview GPIO driver by
#define CHV_PADCTRL1_INTWAKECFG_BOTH 3
#define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
-/**
- * struct chv_community - A community specific configuration
- * @uid: ACPI _UID used to match the community
- * @pins: All pins in this community
- * @npins: Number of pins
- * @groups: All groups in this community
- * @ngroups: Number of groups
- * @functions: All functions in this community
- * @nfunctions: Number of functions
- * @gpps: Pad groups
- * @ngpps: Number of pad groups in this community
- * @nirqs: Total number of IRQs this community can generate
- * @acpi_space_id: An address space ID for ACPI OpRegion handler
- */
-struct chv_community {
- const char *uid;
- const struct pinctrl_pin_desc *pins;
- size_t npins;
- const struct intel_pingroup *groups;
- size_t ngroups;
- const struct intel_function *functions;
- size_t nfunctions;
- const struct intel_padgroup *gpps;
- size_t ngpps;
- size_t nirqs;
- acpi_adr_space_type acpi_space_id;
-};
-
-struct chv_pin_context {
+struct intel_pad_context {
u32 padctrl0;
u32 padctrl1;
};
* @pctldev: Pointer to the pin controller device
* @chip: GPIO chip in this pin controller
* @irqchip: IRQ chip in this pin controller
- * @regs: MMIO registers
+ * @soc: Community specific pin configuration data
+ * @communities: All communities in this pin controller
+ * @ncommunities: Number of communities in this pin controller
+ * @context: Configuration saved over system sleep
* @irq: Our parent irq
- * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
- * offset (in GPIO number space)
- * @community: Community this pinctrl instance represents
+ * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
* @saved_intmask: Interrupt mask saved for system sleep
- * @saved_pin_context: Pointer to a context of the pins saved for system sleep
*
* The first group in @groups is expected to contain all pins that can be
* used as GPIOs.
struct pinctrl_dev *pctldev;
struct gpio_chip chip;
struct irq_chip irqchip;
- void __iomem *regs;
- unsigned int irq;
+ const struct intel_pinctrl_soc_data *soc;
+ struct intel_community *communities;
+ size_t ncommunities;
+ struct intel_pinctrl_context context;
+ int irq;
+
unsigned int intr_lines[16];
- const struct chv_community *community;
u32 saved_intmask;
- struct chv_pin_context *saved_pin_context;
};
#define PINMODE_INVERT_OE BIT(15)
#define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE))
-#define CHV_GPP(start, end) \
+#define CHV_GPP(start, end) \
{ \
.base = (start), \
.size = (end) - (start) + 1, \
}
+#define CHV_COMMUNITY(g, i, a) \
+ { \
+ .gpps = (g), \
+ .ngpps = ARRAY_SIZE(g), \
+ .nirqs = (i), \
+ .acpi_space_id = (a), \
+ }
+
static const struct pinctrl_pin_desc southwest_pins[] = {
PINCTRL_PIN(0, "FST_SPI_D2"),
PINCTRL_PIN(1, "FST_SPI_D0"),
CHV_GPP(90, 97),
};
-static const struct chv_community southwest_community = {
+/*
+ * Southwest community can generate GPIO interrupts only for the first 8
+ * interrupts. The upper half (8-15) can only be used to trigger GPEs.
+ */
+static const struct intel_community southwest_communities[] = {
+ CHV_COMMUNITY(southwest_gpps, 8, 0x91),
+};
+
+static const struct intel_pinctrl_soc_data southwest_soc_data = {
.uid = "1",
.pins = southwest_pins,
.npins = ARRAY_SIZE(southwest_pins),
.ngroups = ARRAY_SIZE(southwest_groups),
.functions = southwest_functions,
.nfunctions = ARRAY_SIZE(southwest_functions),
- .gpps = southwest_gpps,
- .ngpps = ARRAY_SIZE(southwest_gpps),
- /*
- * Southwest community can generate GPIO interrupts only for the
- * first 8 interrupts. The upper half (8-15) can only be used to
- * trigger GPEs.
- */
- .nirqs = 8,
- .acpi_space_id = 0x91,
+ .communities = southwest_communities,
+ .ncommunities = ARRAY_SIZE(southwest_communities),
};
static const struct pinctrl_pin_desc north_pins[] = {
CHV_GPP(60, 72),
};
-static const struct chv_community north_community = {
+/*
+ * North community can generate GPIO interrupts only for the first 8
+ * interrupts. The upper half (8-15) can only be used to trigger GPEs.
+ */
+static const struct intel_community north_communities[] = {
+ CHV_COMMUNITY(north_gpps, 8, 0x92),
+};
+
+static const struct intel_pinctrl_soc_data north_soc_data = {
.uid = "2",
.pins = north_pins,
.npins = ARRAY_SIZE(north_pins),
- .gpps = north_gpps,
- .ngpps = ARRAY_SIZE(north_gpps),
- /*
- * North community can generate GPIO interrupts only for the first
- * 8 interrupts. The upper half (8-15) can only be used to trigger
- * GPEs.
- */
- .nirqs = 8,
- .acpi_space_id = 0x92,
+ .communities = north_communities,
+ .ncommunities = ARRAY_SIZE(north_communities),
};
static const struct pinctrl_pin_desc east_pins[] = {
CHV_GPP(15, 26),
};
-static const struct chv_community east_community = {
+static const struct intel_community east_communities[] = {
+ CHV_COMMUNITY(east_gpps, 16, 0x93),
+};
+
+static const struct intel_pinctrl_soc_data east_soc_data = {
.uid = "3",
.pins = east_pins,
.npins = ARRAY_SIZE(east_pins),
- .gpps = east_gpps,
- .ngpps = ARRAY_SIZE(east_gpps),
- .nirqs = 16,
- .acpi_space_id = 0x93,
+ .communities = east_communities,
+ .ncommunities = ARRAY_SIZE(east_communities),
};
static const struct pinctrl_pin_desc southeast_pins[] = {
CHV_GPP(75, 85),
};
-static const struct chv_community southeast_community = {
+static const struct intel_community southeast_communities[] = {
+ CHV_COMMUNITY(southeast_gpps, 16, 0x94),
+};
+
+static const struct intel_pinctrl_soc_data southeast_soc_data = {
.uid = "4",
.pins = southeast_pins,
.npins = ARRAY_SIZE(southeast_pins),
.ngroups = ARRAY_SIZE(southeast_groups),
.functions = southeast_functions,
.nfunctions = ARRAY_SIZE(southeast_functions),
- .gpps = southeast_gpps,
- .ngpps = ARRAY_SIZE(southeast_gpps),
- .nirqs = 16,
- .acpi_space_id = 0x94,
+ .communities = southeast_communities,
+ .ncommunities = ARRAY_SIZE(southeast_communities),
};
-static const struct chv_community *chv_communities[] = {
- &southwest_community,
- &north_community,
- &east_community,
- &southeast_community,
+static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
+ &southwest_soc_data,
+ &north_soc_data,
+ &east_soc_data,
+ &southeast_soc_data,
+ NULL
};
/*
*/
static DEFINE_RAW_SPINLOCK(chv_lock);
+static u32 chv_pctrl_readl(struct chv_pinctrl *pctrl, unsigned int offset)
+{
+ const struct intel_community *community = &pctrl->communities[0];
+
+ return readl(community->regs + offset);
+}
+
+static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32 value)
+{
+ const struct intel_community *community = &pctrl->communities[0];
+ void __iomem *reg = community->regs + offset;
+
+ /* Write and simple read back to confirm the bus transferring done */
+ writel(value, reg);
+ readl(reg);
+}
+
static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
unsigned int reg)
{
+ const struct intel_community *community = &pctrl->communities[0];
unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
- offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
- GPIO_REGS_SIZE * pad_no;
+ offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
- return pctrl->regs + offset + reg;
+ return community->pad_regs + offset + reg;
}
-static void chv_writel(u32 value, void __iomem *reg)
+static u32 chv_readl(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset)
{
+ return readl(chv_padreg(pctrl, pin, offset));
+}
+
+static void chv_writel(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
+{
+ void __iomem *reg = chv_padreg(pctrl, pin, offset);
+
+ /* Write and simple read back to confirm the bus transferring done */
writel(value, reg);
- /* simple readback to confirm the bus transferring done */
readl(reg);
}
/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
{
- void __iomem *reg;
-
- reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
- return readl(reg) & CHV_PADCTRL1_CFGLOCK;
+ return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
}
static int chv_get_groups_count(struct pinctrl_dev *pctldev)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- return pctrl->community->ngroups;
+ return pctrl->soc->ngroups;
}
static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- return pctrl->community->groups[group].name;
+ return pctrl->soc->groups[group].name;
}
static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- *pins = pctrl->community->groups[group].pins;
- *npins = pctrl->community->groups[group].npins;
+ *pins = pctrl->soc->groups[group].pins;
+ *npins = pctrl->soc->groups[group].npins;
return 0;
}
raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
- ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
+ ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
+ ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
locked = chv_pad_locked(pctrl, offset);
raw_spin_unlock_irqrestore(&chv_lock, flags);
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- return pctrl->community->nfunctions;
+ return pctrl->soc->nfunctions;
}
static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- return pctrl->community->functions[function].name;
+ return pctrl->soc->functions[function].name;
}
static int chv_get_function_groups(struct pinctrl_dev *pctldev,
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- *groups = pctrl->community->functions[function].groups;
- *ngroups = pctrl->community->functions[function].ngroups;
+ *groups = pctrl->soc->functions[function].groups;
+ *ngroups = pctrl->soc->functions[function].ngroups;
return 0;
}
unsigned long flags;
int i;
- grp = &pctrl->community->groups[group];
+ grp = &pctrl->soc->groups[group];
raw_spin_lock_irqsave(&chv_lock, flags);
for (i = 0; i < grp->npins; i++) {
int pin = grp->pins[i];
- void __iomem *reg;
unsigned int mode;
bool invert_oe;
u32 value;
invert_oe = mode & PINMODE_INVERT_OE;
mode &= ~PINMODE_INVERT_OE;
- reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
- value = readl(reg);
+ value = chv_readl(pctrl, pin, CHV_PADCTRL0);
/* Disable GPIO mode */
value &= ~CHV_PADCTRL0_GPIOEN;
/* Set to desired mode */
value &= ~CHV_PADCTRL0_PMODE_MASK;
value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
- chv_writel(value, reg);
+ chv_writel(pctrl, pin, CHV_PADCTRL0, value);
/* Update for invert_oe */
- reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
- value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
+ value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
if (invert_oe)
value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
- chv_writel(value, reg);
+ chv_writel(pctrl, pin, CHV_PADCTRL1, value);
dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
pin, mode, invert_oe ? "" : "not ");
static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
unsigned int offset)
{
- void __iomem *reg;
u32 value;
- reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
- value = readl(reg);
+ value = chv_readl(pctrl, offset, CHV_PADCTRL1);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~CHV_PADCTRL1_INVRXTX_MASK;
- chv_writel(value, reg);
+ chv_writel(pctrl, offset, CHV_PADCTRL1, value);
}
static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
- void __iomem *reg;
u32 value;
raw_spin_lock_irqsave(&chv_lock, flags);
if (chv_pad_locked(pctrl, offset)) {
- value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
+ value = chv_readl(pctrl, offset, CHV_PADCTRL0);
if (!(value & CHV_PADCTRL0_GPIOEN)) {
/* Locked so cannot enable */
raw_spin_unlock_irqrestore(&chv_lock, flags);
/* Disable interrupt generation */
chv_gpio_clear_triggering(pctrl, offset);
- reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
- value = readl(reg);
+ value = chv_readl(pctrl, offset, CHV_PADCTRL0);
/*
* If the pin is in HiZ mode (both TX and RX buffers are
if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
(CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
- value |= CHV_PADCTRL0_GPIOCFG_GPI <<
- CHV_PADCTRL0_GPIOCFG_SHIFT;
+ value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
}
/* Switch to a GPIO mode */
value |= CHV_PADCTRL0_GPIOEN;
- chv_writel(value, reg);
+ chv_writel(pctrl, offset, CHV_PADCTRL0, value);
}
raw_spin_unlock_irqrestore(&chv_lock, flags);
unsigned int offset, bool input)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
unsigned long flags;
u32 ctrl0;
raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
+ ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
if (input)
ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
else
ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
- chv_writel(ctrl0, reg);
+ chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
u32 term;
raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
- ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
+ ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
+ ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
raw_spin_unlock_irqrestore(&chv_lock, flags);
term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
enum pin_config_param param, u32 arg)
{
- void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
unsigned long flags;
u32 ctrl0, pull;
raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl0 = readl(reg);
+ ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
return -EINVAL;
}
- chv_writel(ctrl0, reg);
+ chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
bool enable)
{
- void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
unsigned long flags;
u32 ctrl1;
raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl1 = readl(reg);
+ ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
if (enable)
ctrl1 |= CHV_PADCTRL1_ODEN;
else
ctrl1 &= ~CHV_PADCTRL1_ODEN;
- chv_writel(ctrl1, reg);
+ chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
u32 ctrl0, cfg;
raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
+ ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
unsigned long flags;
- void __iomem *reg;
u32 ctrl0;
raw_spin_lock_irqsave(&chv_lock, flags);
- reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
- ctrl0 = readl(reg);
+ ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
if (value)
ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
else
ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
- chv_writel(ctrl0, reg);
+ chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
unsigned long flags;
raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
+ ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
raw_spin_lock(&chv_lock);
- intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
+ intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
- chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
+ chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
raw_spin_unlock(&chv_lock);
}
raw_spin_lock_irqsave(&chv_lock, flags);
- intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
+ intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
- value = readl(pctrl->regs + CHV_INTMASK);
+ value = chv_pctrl_readl(pctrl, CHV_INTMASK);
if (mask)
value &= ~BIT(intr_line);
else
value |= BIT(intr_line);
- chv_writel(value, pctrl->regs + CHV_INTMASK);
+ chv_pctrl_writel(pctrl, CHV_INTMASK, value);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
u32 intsel, value;
raw_spin_lock_irqsave(&chv_lock, flags);
- intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
+ intsel = chv_readl(pctrl, pin, CHV_PADCTRL0);
intsel &= CHV_PADCTRL0_INTSEL_MASK;
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
- value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
+ value = chv_readl(pctrl, pin, CHV_PADCTRL1);
if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
handler = handle_level_irq;
else
* Driver programs the IntWakeCfg bits and save the mapping.
*/
if (!chv_pad_locked(pctrl, pin)) {
- void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
-
- value = readl(reg);
+ value = chv_readl(pctrl, pin, CHV_PADCTRL1);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~CHV_PADCTRL1_INVRXTX_MASK;
value |= CHV_PADCTRL1_INVRXTX_RXDATA;
}
- chv_writel(value, reg);
+ chv_writel(pctrl, pin, CHV_PADCTRL1, value);
}
- value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
+ value = chv_readl(pctrl, pin, CHV_PADCTRL0);
value &= CHV_PADCTRL0_INTSEL_MASK;
value >>= CHV_PADCTRL0_INTSEL_SHIFT;
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
+ const struct intel_community *community = &pctrl->communities[0];
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long pending;
unsigned long flags;
chained_irq_enter(chip, desc);
raw_spin_lock_irqsave(&chv_lock, flags);
- pending = readl(pctrl->regs + CHV_INTSTAT);
+ pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
raw_spin_unlock_irqrestore(&chv_lock, flags);
- for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
+ for_each_set_bit(intr_line, &pending, community->nirqs) {
unsigned int irq, offset;
offset = pctrl->intr_lines[intr_line];
unsigned int ngpios)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
- const struct chv_community *community = pctrl->community;
+ const struct intel_community *community = &pctrl->communities[0];
int i;
/* Do not add GPIOs that can only generate GPEs to the IRQ domain */
- for (i = 0; i < community->npins; i++) {
+ for (i = 0; i < pctrl->soc->npins; i++) {
const struct pinctrl_pin_desc *desc;
u32 intsel;
- desc = &community->pins[i];
+ desc = &pctrl->soc->pins[i];
- intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
+ intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
intsel &= CHV_PADCTRL0_INTSEL_MASK;
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
+ const struct intel_community *community = &pctrl->communities[0];
/*
* The same set of machines in chv_no_valid_mask[] have incorrectly
* Mask all interrupts the community is able to generate
* but leave the ones that can only generate GPEs unmasked.
*/
- chv_writel(GENMASK(31, pctrl->community->nirqs),
- pctrl->regs + CHV_INTMASK);
+ chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
}
/* Clear all interrupts */
- chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
+ chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
return 0;
}
static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
- const struct chv_community *community = pctrl->community;
+ const struct intel_community *community = &pctrl->communities[0];
const struct intel_padgroup *gpp;
int ret, i;
static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
{
+ const struct intel_community *community = &pctrl->communities[0];
const struct intel_padgroup *gpp;
struct gpio_chip *chip = &pctrl->chip;
bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
- const struct chv_community *community = pctrl->community;
int ret, i, irq_base;
*chip = chv_gpio_chip;
- chip->ngpio = community->pins[community->npins - 1].number + 1;
+ chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
chip->label = dev_name(pctrl->dev);
chip->add_pin_ranges = chv_gpio_add_pin_ranges;
chip->parent = pctrl->dev;
chip->irq.init_valid_mask = chv_init_irq_valid_mask;
} else {
irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
- community->npins, NUMA_NO_NODE);
+ pctrl->soc->npins, NUMA_NO_NODE);
if (irq_base < 0) {
dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
return irq_base;
raw_spin_lock_irqsave(&chv_lock, flags);
if (function == ACPI_WRITE)
- chv_writel((u32)(*value), pctrl->regs + (u32)address);
+ chv_pctrl_writel(pctrl, address, *value);
else if (function == ACPI_READ)
- *value = readl(pctrl->regs + (u32)address);
+ *value = chv_pctrl_readl(pctrl, address);
else
ret = AE_BAD_PARAMETER;
static int chv_pinctrl_probe(struct platform_device *pdev)
{
+ const struct intel_pinctrl_soc_data *soc_data = NULL;
+ const struct intel_pinctrl_soc_data **soc_table;
+ struct intel_community *community;
+ struct device *dev = &pdev->dev;
struct chv_pinctrl *pctrl;
struct acpi_device *adev;
acpi_status status;
if (!adev)
return -ENODEV;
- pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
- if (!pctrl)
- return -ENOMEM;
-
- for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
- if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
- pctrl->community = chv_communities[i];
+ soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
+ for (i = 0; soc_table[i]; i++) {
+ if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
+ soc_data = soc_table[i];
break;
}
- if (i == ARRAY_SIZE(chv_communities))
+ }
+ if (!soc_data)
return -ENODEV;
+ pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
+ if (!pctrl)
+ return -ENOMEM;
+
pctrl->dev = &pdev->dev;
+ pctrl->soc = soc_data;
+
+ pctrl->ncommunities = pctrl->soc->ncommunities;
+ pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
+ pctrl->ncommunities * sizeof(*pctrl->communities),
+ GFP_KERNEL);
+ if (!pctrl->communities)
+ return -ENOMEM;
+
+ community = &pctrl->communities[0];
+ community->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(community->regs))
+ return PTR_ERR(community->regs);
+
+ community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
#ifdef CONFIG_PM_SLEEP
- pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
- pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
- GFP_KERNEL);
- if (!pctrl->saved_pin_context)
+ pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
+ sizeof(*pctrl->context.pads),
+ GFP_KERNEL);
+ if (!pctrl->context.pads)
return -ENOMEM;
#endif
- pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(pctrl->regs))
- return PTR_ERR(pctrl->regs);
-
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
pctrl->pctldesc = chv_pinctrl_desc;
pctrl->pctldesc.name = dev_name(&pdev->dev);
- pctrl->pctldesc.pins = pctrl->community->pins;
- pctrl->pctldesc.npins = pctrl->community->npins;
+ pctrl->pctldesc.pins = pctrl->soc->pins;
+ pctrl->pctldesc.npins = pctrl->soc->npins;
pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
pctrl);
return ret;
status = acpi_install_address_space_handler(adev->handle,
- pctrl->community->acpi_space_id,
+ community->acpi_space_id,
chv_pinctrl_mmio_access_handler,
NULL, pctrl);
if (ACPI_FAILURE(status))
static int chv_pinctrl_remove(struct platform_device *pdev)
{
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
+ const struct intel_community *community = &pctrl->communities[0];
acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
- pctrl->community->acpi_space_id,
+ community->acpi_space_id,
chv_pinctrl_mmio_access_handler);
return 0;
raw_spin_lock_irqsave(&chv_lock, flags);
- pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
+ pctrl->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
- for (i = 0; i < pctrl->community->npins; i++) {
+ for (i = 0; i < pctrl->soc->npins; i++) {
const struct pinctrl_pin_desc *desc;
- struct chv_pin_context *ctx;
- void __iomem *reg;
+ struct intel_pad_context *ctx = &pctrl->context.pads[i];
- desc = &pctrl->community->pins[i];
+ desc = &pctrl->soc->pins[i];
if (chv_pad_locked(pctrl, desc->number))
continue;
- ctx = &pctrl->saved_pin_context[i];
-
- reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
- ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
+ ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
+ ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
- reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
- ctx->padctrl1 = readl(reg);
+ ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
}
raw_spin_unlock_irqrestore(&chv_lock, flags);
* registers because we don't know in which state BIOS left them
* upon exiting suspend.
*/
- chv_writel(0, pctrl->regs + CHV_INTMASK);
+ chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
- for (i = 0; i < pctrl->community->npins; i++) {
+ for (i = 0; i < pctrl->soc->npins; i++) {
const struct pinctrl_pin_desc *desc;
- const struct chv_pin_context *ctx;
- void __iomem *reg;
+ struct intel_pad_context *ctx = &pctrl->context.pads[i];
u32 val;
- desc = &pctrl->community->pins[i];
+ desc = &pctrl->soc->pins[i];
if (chv_pad_locked(pctrl, desc->number))
continue;
- ctx = &pctrl->saved_pin_context[i];
-
/* Only restore if our saved state differs from the current */
- reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
- val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
+ val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
+ val &= ~CHV_PADCTRL0_GPIORXSTATE;
if (ctx->padctrl0 != val) {
- chv_writel(ctx->padctrl0, reg);
+ chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
- desc->number, readl(reg));
+ desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0));
}
- reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
- val = readl(reg);
+ val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
if (ctx->padctrl1 != val) {
- chv_writel(ctx->padctrl1, reg);
+ chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
- desc->number, readl(reg));
+ desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1));
}
}
* Now that all pins are restored to known state, we can restore
* the interrupt mask register as well.
*/
- chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
- chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
+ chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
+ chv_pctrl_writel(pctrl, CHV_INTMASK, pctrl->saved_intmask);
raw_spin_unlock_irqrestore(&chv_lock, flags);
};
static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
- { "INT33FF" },
+ { "INT33FF", (kernel_ulong_t)chv_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel Emmitsburg PCH pinctrl/GPIO driver
+ *
+ * Copyright (C) 2020, Intel Corporation
+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+#define EBG_PAD_OWN 0x0a0
+#define EBG_PADCFGLOCK 0x100
+#define EBG_HOSTSW_OWN 0x130
+#define EBG_GPI_IS 0x200
+#define EBG_GPI_IE 0x210
+
+#define EBG_GPP(r, s, e) \
+ { \
+ .reg_num = (r), \
+ .base = (s), \
+ .size = ((e) - (s) + 1), \
+ }
+
+#define EBG_COMMUNITY(b, s, e, g) \
+ { \
+ .barno = (b), \
+ .padown_offset = EBG_PAD_OWN, \
+ .padcfglock_offset = EBG_PADCFGLOCK, \
+ .hostown_offset = EBG_HOSTSW_OWN, \
+ .is_offset = EBG_GPI_IS, \
+ .ie_offset = EBG_GPI_IE, \
+ .pin_base = (s), \
+ .npins = ((e) - (s) + 1), \
+ .gpps = (g), \
+ .ngpps = ARRAY_SIZE(g), \
+ }
+
+/* Emmitsburg */
+static const struct pinctrl_pin_desc ebg_pins[] = {
+ /* GPP_A */
+ PINCTRL_PIN(0, "ESPI_ALERT0B"),
+ PINCTRL_PIN(1, "ESPI_ALERT1B"),
+ PINCTRL_PIN(2, "ESPI_IO_0"),
+ PINCTRL_PIN(3, "ESPI_IO_1"),
+ PINCTRL_PIN(4, "ESPI_IO_2"),
+ PINCTRL_PIN(5, "ESPI_IO_3"),
+ PINCTRL_PIN(6, "ESPI_CS0B"),
+ PINCTRL_PIN(7, "ESPI_CS1B"),
+ PINCTRL_PIN(8, "ESPI_RESETB"),
+ PINCTRL_PIN(9, "ESPI_CLK"),
+ PINCTRL_PIN(10, "SRCCLKREQB_0"),
+ PINCTRL_PIN(11, "SRCCLKREQB_1"),
+ PINCTRL_PIN(12, "SRCCLKREQB_2"),
+ PINCTRL_PIN(13, "SRCCLKREQB_3"),
+ PINCTRL_PIN(14, "SRCCLKREQB_4"),
+ PINCTRL_PIN(15, "SRCCLKREQB_5"),
+ PINCTRL_PIN(16, "SRCCLKREQB_6"),
+ PINCTRL_PIN(17, "SRCCLKREQB_7"),
+ PINCTRL_PIN(18, "SRCCLKREQB_8"),
+ PINCTRL_PIN(19, "SRCCLKREQB_9"),
+ PINCTRL_PIN(20, "ESPI_CLK_LOOPBK"),
+ /* GPP_B */
+ PINCTRL_PIN(21, "GSXDOUT"),
+ PINCTRL_PIN(22, "GSXSLOAD"),
+ PINCTRL_PIN(23, "GSXDIN"),
+ PINCTRL_PIN(24, "GSXSRESETB"),
+ PINCTRL_PIN(25, "GSXCLK"),
+ PINCTRL_PIN(26, "USB2_OCB_0"),
+ PINCTRL_PIN(27, "USB2_OCB_1"),
+ PINCTRL_PIN(28, "USB2_OCB_2"),
+ PINCTRL_PIN(29, "USB2_OCB_3"),
+ PINCTRL_PIN(30, "USB2_OCB_4"),
+ PINCTRL_PIN(31, "USB2_OCB_5"),
+ PINCTRL_PIN(32, "USB2_OCB_6"),
+ PINCTRL_PIN(33, "HS_UART0_RXD"),
+ PINCTRL_PIN(34, "HS_UART0_TXD"),
+ PINCTRL_PIN(35, "HS_UART0_RTSB"),
+ PINCTRL_PIN(36, "HS_UART0_CTSB"),
+ PINCTRL_PIN(37, "HS_UART1_RXD"),
+ PINCTRL_PIN(38, "HS_UART1_TXD"),
+ PINCTRL_PIN(39, "HS_UART1_RTSB"),
+ PINCTRL_PIN(40, "HS_UART1_CTSB"),
+ PINCTRL_PIN(41, "GPPC_B_20"),
+ PINCTRL_PIN(42, "GPPC_B_21"),
+ PINCTRL_PIN(43, "GPPC_B_22"),
+ PINCTRL_PIN(44, "PS_ONB"),
+ /* SPI */
+ PINCTRL_PIN(45, "SPI0_IO_2"),
+ PINCTRL_PIN(46, "SPI0_IO_3"),
+ PINCTRL_PIN(47, "SPI0_MOSI_IO_0"),
+ PINCTRL_PIN(48, "SPI0_MISO_IO_1"),
+ PINCTRL_PIN(49, "SPI0_TPM_CSB"),
+ PINCTRL_PIN(50, "SPI0_FLASH_0_CSB"),
+ PINCTRL_PIN(51, "SPI0_FLASH_1_CSB"),
+ PINCTRL_PIN(52, "SPI0_CLK"),
+ PINCTRL_PIN(53, "TIME_SYNC_0"),
+ PINCTRL_PIN(54, "SPKR"),
+ PINCTRL_PIN(55, "CPU_GP_0"),
+ PINCTRL_PIN(56, "CPU_GP_1"),
+ PINCTRL_PIN(57, "CPU_GP_2"),
+ PINCTRL_PIN(58, "CPU_GP_3"),
+ PINCTRL_PIN(59, "SUSWARNB_SUSPWRDNACK"),
+ PINCTRL_PIN(60, "SUSACKB"),
+ PINCTRL_PIN(61, "NMIB"),
+ PINCTRL_PIN(62, "SMIB"),
+ PINCTRL_PIN(63, "GPPC_S_10"),
+ PINCTRL_PIN(64, "GPPC_S_11"),
+ PINCTRL_PIN(65, "SPI_CLK_LOOPBK"),
+ /* GPP_C */
+ PINCTRL_PIN(66, "ME_SML0CLK"),
+ PINCTRL_PIN(67, "ME_SML0DATA"),
+ PINCTRL_PIN(68, "ME_SML0ALERTB"),
+ PINCTRL_PIN(69, "ME_SML0BDATA"),
+ PINCTRL_PIN(70, "ME_SML0BCLK"),
+ PINCTRL_PIN(71, "ME_SML0BALERTB"),
+ PINCTRL_PIN(72, "ME_SML1CLK"),
+ PINCTRL_PIN(73, "ME_SML1DATA"),
+ PINCTRL_PIN(74, "ME_SML1ALERTB"),
+ PINCTRL_PIN(75, "ME_SML2CLK"),
+ PINCTRL_PIN(76, "ME_SML2DATA"),
+ PINCTRL_PIN(77, "ME_SML2ALERTB"),
+ PINCTRL_PIN(78, "ME_SML3CLK"),
+ PINCTRL_PIN(79, "ME_SML3DATA"),
+ PINCTRL_PIN(80, "ME_SML3ALERTB"),
+ PINCTRL_PIN(81, "ME_SML4CLK"),
+ PINCTRL_PIN(82, "ME_SML4DATA"),
+ PINCTRL_PIN(83, "ME_SML4ALERTB"),
+ PINCTRL_PIN(84, "GPPC_C_18"),
+ PINCTRL_PIN(85, "MC_SMBCLK"),
+ PINCTRL_PIN(86, "MC_SMBDATA"),
+ PINCTRL_PIN(87, "MC_SMBALERTB"),
+ /* GPP_D */
+ PINCTRL_PIN(88, "HS_SMBCLK"),
+ PINCTRL_PIN(89, "HS_SMBDATA"),
+ PINCTRL_PIN(90, "HS_SMBALERTB"),
+ PINCTRL_PIN(91, "GBE_SMB_ALRT_N"),
+ PINCTRL_PIN(92, "GBE_SMB_CLK"),
+ PINCTRL_PIN(93, "GBE_SMB_DATA"),
+ PINCTRL_PIN(94, "GBE_GPIO10"),
+ PINCTRL_PIN(95, "GBE_GPIO11"),
+ PINCTRL_PIN(96, "CRASHLOG_TRIG_N"),
+ PINCTRL_PIN(97, "PMEB"),
+ PINCTRL_PIN(98, "BM_BUSYB"),
+ PINCTRL_PIN(99, "PLTRSTB"),
+ PINCTRL_PIN(100, "PCHHOTB"),
+ PINCTRL_PIN(101, "ADR_COMPLETE"),
+ PINCTRL_PIN(102, "ADR_TRIGGER_N"),
+ PINCTRL_PIN(103, "VRALERTB"),
+ PINCTRL_PIN(104, "ADR_ACK"),
+ PINCTRL_PIN(105, "THERMTRIP_N"),
+ PINCTRL_PIN(106, "MEMTRIP_N"),
+ PINCTRL_PIN(107, "MSMI_N"),
+ PINCTRL_PIN(108, "CATERR_N"),
+ PINCTRL_PIN(109, "GLB_RST_WARN_B"),
+ PINCTRL_PIN(110, "USB2_OCB_7"),
+ PINCTRL_PIN(111, "GPP_D_23"),
+ /* GPP_E */
+ PINCTRL_PIN(112, "SATA1_XPCIE_0"),
+ PINCTRL_PIN(113, "SATA1_XPCIE_1"),
+ PINCTRL_PIN(114, "SATA1_XPCIE_2"),
+ PINCTRL_PIN(115, "SATA1_XPCIE_3"),
+ PINCTRL_PIN(116, "SATA0_XPCIE_2"),
+ PINCTRL_PIN(117, "SATA0_XPCIE_3"),
+ PINCTRL_PIN(118, "SATA0_USB3_XPCIE_0"),
+ PINCTRL_PIN(119, "SATA0_USB3_XPCIE_1"),
+ PINCTRL_PIN(120, "SATA0_SCLOCK"),
+ PINCTRL_PIN(121, "SATA0_SLOAD"),
+ PINCTRL_PIN(122, "SATA0_SDATAOUT"),
+ PINCTRL_PIN(123, "SATA1_SCLOCK"),
+ PINCTRL_PIN(124, "SATA1_SLOAD"),
+ PINCTRL_PIN(125, "SATA1_SDATAOUT"),
+ PINCTRL_PIN(126, "SATA2_SCLOCK"),
+ PINCTRL_PIN(127, "SATA2_SLOAD"),
+ PINCTRL_PIN(128, "SATA2_SDATAOUT"),
+ PINCTRL_PIN(129, "ERR0_N"),
+ PINCTRL_PIN(130, "ERR1_N"),
+ PINCTRL_PIN(131, "ERR2_N"),
+ PINCTRL_PIN(132, "GBE_UART_RXD"),
+ PINCTRL_PIN(133, "GBE_UART_TXD"),
+ PINCTRL_PIN(134, "GBE_UART_RTSB"),
+ PINCTRL_PIN(135, "GBE_UART_CTSB"),
+ /* JTAG */
+ PINCTRL_PIN(136, "JTAG_TDO"),
+ PINCTRL_PIN(137, "JTAG_TDI"),
+ PINCTRL_PIN(138, "JTAG_TCK"),
+ PINCTRL_PIN(139, "JTAG_TMS"),
+ PINCTRL_PIN(140, "JTAGX"),
+ PINCTRL_PIN(141, "PRDYB"),
+ PINCTRL_PIN(142, "PREQB"),
+ PINCTRL_PIN(143, "GLB_PC_DISABLE"),
+ PINCTRL_PIN(144, "DBG_PMODE"),
+ PINCTRL_PIN(145, "GLB_EXT_ACC_DISABLE"),
+ /* GPP_H */
+ PINCTRL_PIN(146, "GBE_GPIO12"),
+ PINCTRL_PIN(147, "GBE_GPIO13"),
+ PINCTRL_PIN(148, "GBE_SDP_TIMESYNC0_S2N"),
+ PINCTRL_PIN(149, "GBE_SDP_TIMESYNC1_S2N"),
+ PINCTRL_PIN(150, "GBE_SDP_TIMESYNC2_S2N"),
+ PINCTRL_PIN(151, "GBE_SDP_TIMESYNC3_S2N"),
+ PINCTRL_PIN(152, "GPPC_H_6"),
+ PINCTRL_PIN(153, "GPPC_H_7"),
+ PINCTRL_PIN(154, "NCSI_CLK_IN"),
+ PINCTRL_PIN(155, "NCSI_CRS_DV"),
+ PINCTRL_PIN(156, "NCSI_RXD0"),
+ PINCTRL_PIN(157, "NCSI_RXD1"),
+ PINCTRL_PIN(158, "NCSI_TX_EN"),
+ PINCTRL_PIN(159, "NCSI_TXD0"),
+ PINCTRL_PIN(160, "NCSI_TXD1"),
+ PINCTRL_PIN(161, "NAC_NCSI_CLK_OUT_0"),
+ PINCTRL_PIN(162, "NAC_NCSI_CLK_OUT_1"),
+ PINCTRL_PIN(163, "NAC_NCSI_CLK_OUT_2"),
+ PINCTRL_PIN(164, "PMCALERTB"),
+ PINCTRL_PIN(165, "GPPC_H_19"),
+ /* GPP_J */
+ PINCTRL_PIN(166, "CPUPWRGD"),
+ PINCTRL_PIN(167, "CPU_THRMTRIP_N"),
+ PINCTRL_PIN(168, "PLTRST_CPUB"),
+ PINCTRL_PIN(169, "TRIGGER0_N"),
+ PINCTRL_PIN(170, "TRIGGER1_N"),
+ PINCTRL_PIN(171, "CPU_PWR_DEBUG_N"),
+ PINCTRL_PIN(172, "CPU_MEMTRIP_N"),
+ PINCTRL_PIN(173, "CPU_MSMI_N"),
+ PINCTRL_PIN(174, "ME_PECI"),
+ PINCTRL_PIN(175, "NAC_SPARE0"),
+ PINCTRL_PIN(176, "NAC_SPARE1"),
+ PINCTRL_PIN(177, "NAC_SPARE2"),
+ PINCTRL_PIN(178, "CPU_ERR0_N"),
+ PINCTRL_PIN(179, "CPU_CATERR_N"),
+ PINCTRL_PIN(180, "CPU_ERR1_N"),
+ PINCTRL_PIN(181, "CPU_ERR2_N"),
+ PINCTRL_PIN(182, "GPP_J_16"),
+ PINCTRL_PIN(183, "GPP_J_17"),
+ /* GPP_I */
+ PINCTRL_PIN(184, "GBE_GPIO4"),
+ PINCTRL_PIN(185, "GBE_GPIO5"),
+ PINCTRL_PIN(186, "GBE_GPIO6"),
+ PINCTRL_PIN(187, "GBE_GPIO7"),
+ PINCTRL_PIN(188, "GBE1_LED1"),
+ PINCTRL_PIN(189, "GBE1_LED2"),
+ PINCTRL_PIN(190, "GBE2_LED0"),
+ PINCTRL_PIN(191, "GBE2_LED1"),
+ PINCTRL_PIN(192, "GBE2_LED2"),
+ PINCTRL_PIN(193, "GBE3_LED0"),
+ PINCTRL_PIN(194, "GBE3_LED1"),
+ PINCTRL_PIN(195, "GBE3_LED2"),
+ PINCTRL_PIN(196, "GBE0_I2C_CLK"),
+ PINCTRL_PIN(197, "GBE0_I2C_DATA"),
+ PINCTRL_PIN(198, "GBE1_I2C_CLK"),
+ PINCTRL_PIN(199, "GBE1_I2C_DATA"),
+ PINCTRL_PIN(200, "GBE2_I2C_CLK"),
+ PINCTRL_PIN(201, "GBE2_I2C_DATA"),
+ PINCTRL_PIN(202, "GBE3_I2C_CLK"),
+ PINCTRL_PIN(203, "GBE3_I2C_DATA"),
+ PINCTRL_PIN(204, "GBE4_I2C_CLK"),
+ PINCTRL_PIN(205, "GBE4_I2C_DATA"),
+ PINCTRL_PIN(206, "GBE_GPIO8"),
+ PINCTRL_PIN(207, "GBE_GPIO9"),
+ /* GPP_L */
+ PINCTRL_PIN(208, "PM_SYNC_0"),
+ PINCTRL_PIN(209, "PM_DOWN_0"),
+ PINCTRL_PIN(210, "PM_SYNC_CLK_0"),
+ PINCTRL_PIN(211, "GPP_L_3"),
+ PINCTRL_PIN(212, "GPP_L_4"),
+ PINCTRL_PIN(213, "GPP_L_5"),
+ PINCTRL_PIN(214, "GPP_L_6"),
+ PINCTRL_PIN(215, "GPP_L_7"),
+ PINCTRL_PIN(216, "GPP_L_8"),
+ PINCTRL_PIN(217, "NAC_GBE_GPIO0_S2N"),
+ PINCTRL_PIN(218, "NAC_GBE_GPIO1_S2N"),
+ PINCTRL_PIN(219, "NAC_GBE_GPIO2_S2N"),
+ PINCTRL_PIN(220, "NAC_GBE_GPIO3_S2N"),
+ PINCTRL_PIN(221, "NAC_GBE_SMB_DATA_IN"),
+ PINCTRL_PIN(222, "NAC_GBE_SMB_DATA_OUT"),
+ PINCTRL_PIN(223, "NAC_GBE_SMB_ALRT_N"),
+ PINCTRL_PIN(224, "NAC_GBE_SMB_CLK_IN"),
+ PINCTRL_PIN(225, "NAC_GBE_SMB_CLK_OUT"),
+ /* GPP_M */
+ PINCTRL_PIN(226, "GPP_M_0"),
+ PINCTRL_PIN(227, "GPP_M_1"),
+ PINCTRL_PIN(228, "GPP_M_2"),
+ PINCTRL_PIN(229, "GPP_M_3"),
+ PINCTRL_PIN(230, "NAC_WAKE_N"),
+ PINCTRL_PIN(231, "GPP_M_5"),
+ PINCTRL_PIN(232, "GPP_M_6"),
+ PINCTRL_PIN(233, "GPP_M_7"),
+ PINCTRL_PIN(234, "GPP_M_8"),
+ PINCTRL_PIN(235, "NAC_SBLINK_S2N"),
+ PINCTRL_PIN(236, "NAC_SBLINK_N2S"),
+ PINCTRL_PIN(237, "NAC_SBLINK_CLK_N2S"),
+ PINCTRL_PIN(238, "NAC_SBLINK_CLK_S2N"),
+ PINCTRL_PIN(239, "NAC_XTAL_VALID"),
+ PINCTRL_PIN(240, "NAC_RESET_NAC_N"),
+ PINCTRL_PIN(241, "GPP_M_15"),
+ PINCTRL_PIN(242, "GPP_M_16"),
+ PINCTRL_PIN(243, "GPP_M_17"),
+ /* GPP_N */
+ PINCTRL_PIN(244, "GPP_N_0"),
+ PINCTRL_PIN(245, "NAC_NCSI_TXD0"),
+ PINCTRL_PIN(246, "GPP_N_2"),
+ PINCTRL_PIN(247, "GPP_N_3"),
+ PINCTRL_PIN(248, "NAC_NCSI_REFCLK_IN"),
+ PINCTRL_PIN(249, "GPP_N_5"),
+ PINCTRL_PIN(250, "GPP_N_6"),
+ PINCTRL_PIN(251, "GPP_N_7"),
+ PINCTRL_PIN(252, "NAC_NCSI_RXD0"),
+ PINCTRL_PIN(253, "NAC_NCSI_RXD1"),
+ PINCTRL_PIN(254, "NAC_NCSI_CRS_DV"),
+ PINCTRL_PIN(255, "NAC_NCSI_CLK_IN"),
+ PINCTRL_PIN(256, "NAC_NCSI_REFCLK_OUT"),
+ PINCTRL_PIN(257, "NAC_NCSI_TX_EN"),
+ PINCTRL_PIN(258, "NAC_NCSI_TXD1"),
+ PINCTRL_PIN(259, "NAC_NCSI_OE_N"),
+ PINCTRL_PIN(260, "NAC_GR_N"),
+ PINCTRL_PIN(261, "NAC_INIT_SX_WAKE_N"),
+};
+
+static const struct intel_padgroup ebg_community0_gpps[] = {
+ EBG_GPP(0, 0, 20), /* GPP_A */
+ EBG_GPP(1, 21, 44), /* GPP_B */
+ EBG_GPP(2, 45, 65), /* SPI */
+};
+
+static const struct intel_padgroup ebg_community1_gpps[] = {
+ EBG_GPP(0, 66, 87), /* GPP_C */
+ EBG_GPP(1, 88, 111), /* GPP_D */
+};
+
+static const struct intel_padgroup ebg_community3_gpps[] = {
+ EBG_GPP(0, 112, 135), /* GPP_E */
+ EBG_GPP(1, 136, 145), /* JTAG */
+};
+
+static const struct intel_padgroup ebg_community4_gpps[] = {
+ EBG_GPP(0, 146, 165), /* GPP_H */
+ EBG_GPP(1, 166, 183), /* GPP_J */
+};
+
+static const struct intel_padgroup ebg_community5_gpps[] = {
+ EBG_GPP(0, 184, 207), /* GPP_I */
+ EBG_GPP(1, 208, 225), /* GPP_L */
+ EBG_GPP(2, 226, 243), /* GPP_M */
+ EBG_GPP(3, 244, 261), /* GPP_N */
+};
+
+static const struct intel_community ebg_communities[] = {
+ EBG_COMMUNITY(0, 0, 65, ebg_community0_gpps),
+ EBG_COMMUNITY(1, 66, 111, ebg_community1_gpps),
+ EBG_COMMUNITY(2, 112, 145, ebg_community3_gpps),
+ EBG_COMMUNITY(3, 146, 183, ebg_community4_gpps),
+ EBG_COMMUNITY(4, 184, 261, ebg_community5_gpps),
+};
+
+static const struct intel_pinctrl_soc_data ebg_soc_data = {
+ .pins = ebg_pins,
+ .npins = ARRAY_SIZE(ebg_pins),
+ .communities = ebg_communities,
+ .ncommunities = ARRAY_SIZE(ebg_communities),
+};
+
+static const struct acpi_device_id ebg_pinctrl_acpi_match[] = {
+ { "INTC1071", (kernel_ulong_t)&ebg_soc_data },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, ebg_pinctrl_acpi_match);
+
+static INTEL_PINCTRL_PM_OPS(ebg_pinctrl_pm_ops);
+
+static struct platform_driver ebg_pinctrl_driver = {
+ .probe = intel_pinctrl_probe_by_hid,
+ .driver = {
+ .name = "emmitsburg-pinctrl",
+ .acpi_match_table = ebg_pinctrl_acpi_match,
+ .pm = &ebg_pinctrl_pm_ops,
+ },
+};
+
+module_platform_driver(ebg_pinctrl_driver);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_DESCRIPTION("Intel Emmitsburg PCH pinctrl/GPIO driver");
+MODULE_LICENSE("GPL v2");
{
u32 value;
+ value = readl(padcfg0);
+
/* Put the pad into GPIO mode */
- value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
+ value &= ~PADCFG0_PMODE_MASK;
+ value |= PADCFG0_PMODE_GPIO;
+
+ /* Disable input and output buffers */
+ value &= ~PADCFG0_GPIORXDIS;
+ value &= ~PADCFG0_GPIOTXDIS;
+
/* Disable SCI/SMI/NMI generation */
value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
+
writel(value, padcfg0);
}
void __iomem *padcfg0;
unsigned long flags;
+ padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
+
raw_spin_lock_irqsave(&pctrl->lock, flags);
if (!intel_pad_owned_by_host(pctrl, pin)) {
return 0;
}
- padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
-
/*
* If pin is already configured in GPIO mode, we assume that
* firmware provides correct settings. In such case we avoid
void __iomem *padcfg0;
unsigned long flags;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
-
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
- __intel_gpio_set_direction(padcfg0, input);
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+ __intel_gpio_set_direction(padcfg0, input);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
.gpio_set_direction = intel_gpio_set_direction,
};
-static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *config)
+static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
+ enum pin_config_param param, u32 *arg)
{
- struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param = pinconf_to_config_param(*config);
const struct intel_community *community;
+ void __iomem *padcfg1;
+ unsigned long flags;
u32 value, term;
- u32 arg = 0;
-
- if (!intel_pad_owned_by_host(pctrl, pin))
- return -ENOTSUPP;
community = intel_get_community(pctrl, pin);
- value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
+ padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+ value = readl(padcfg1);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+
term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
switch (param) {
switch (term) {
case PADCFG1_TERM_1K:
- arg = 1000;
+ *arg = 1000;
break;
case PADCFG1_TERM_2K:
- arg = 2000;
+ *arg = 2000;
break;
case PADCFG1_TERM_5K:
- arg = 5000;
+ *arg = 5000;
break;
case PADCFG1_TERM_20K:
- arg = 20000;
+ *arg = 20000;
break;
}
case PADCFG1_TERM_1K:
if (!(community->features & PINCTRL_FEATURE_1K_PD))
return -EINVAL;
- arg = 1000;
+ *arg = 1000;
break;
case PADCFG1_TERM_5K:
- arg = 5000;
+ *arg = 5000;
break;
case PADCFG1_TERM_20K:
- arg = 20000;
+ *arg = 20000;
break;
}
break;
- case PIN_CONFIG_INPUT_DEBOUNCE: {
- void __iomem *padcfg2;
- u32 v;
+ default:
+ return -EINVAL;
+ }
- padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
- if (!padcfg2)
- return -ENOTSUPP;
+ return 0;
+}
- v = readl(padcfg2);
- if (!(v & PADCFG2_DEBEN))
- return -EINVAL;
+static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
+ enum pin_config_param param, u32 *arg)
+{
+ void __iomem *padcfg2;
+ unsigned long flags;
+ unsigned long v;
+ u32 value2;
+
+ padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
+ if (!padcfg2)
+ return -ENOTSUPP;
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+ value2 = readl(padcfg2);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ if (!(value2 & PADCFG2_DEBEN))
+ return -EINVAL;
+
+ v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
+ *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
+
+ return 0;
+}
+
+static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u32 arg = 0;
+ int ret;
- v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
- arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
+ if (!intel_pad_owned_by_host(pctrl, pin))
+ return -ENOTSUPP;
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = intel_config_get_pull(pctrl, pin, param, &arg);
+ if (ret)
+ return ret;
+ break;
+
+ case PIN_CONFIG_INPUT_DEBOUNCE:
+ ret = intel_config_get_debounce(pctrl, pin, param, &arg);
+ if (ret)
+ return ret;
break;
- }
default:
return -ENOTSUPP;
int ret = 0;
u32 value;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
-
community = intel_get_community(pctrl, pin);
padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+
value = readl(padcfg1);
switch (param) {
void __iomem *padcfg0, *padcfg2;
unsigned long flags;
u32 value0, value2;
- int ret = 0;
padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
if (!padcfg2)
v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
if (v < 3 || v > 15) {
- ret = -EINVAL;
- goto exit_unlock;
- } else {
- /* Enable glitch filter and debouncer */
- value0 |= PADCFG0_PREGFRXSEL;
- value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
- value2 |= PADCFG2_DEBEN;
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ return -EINVAL;
}
+
+ /* Enable glitch filter and debouncer */
+ value0 |= PADCFG0_PREGFRXSEL;
+ value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
+ value2 |= PADCFG2_DEBEN;
}
writel(value0, padcfg0);
writel(value2, padcfg2);
-exit_unlock:
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
- return ret;
+ return 0;
}
static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
+ unsigned long flags;
void __iomem *reg;
u32 padcfg0;
int pin;
if (!reg)
return -EINVAL;
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
padcfg0 = readl(reg);
-
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
if (padcfg0 & PADCFG0_PMODE_MASK)
return -EINVAL;
intel_gpio_set_gpio_mode(reg);
+ /* Disable TX buffer and enable RX (this will be input) */
+ __intel_gpio_set_direction(reg, true);
+
value = readl(reg);
value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
return 0;
}
-static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
- const struct intel_community *community)
+static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
+ const struct intel_community *community)
{
struct gpio_chip *gc = &pctrl->chip;
- irqreturn_t ret = IRQ_NONE;
- int gpp;
+ unsigned int gpp;
+ int ret = 0;
for (gpp = 0; gpp < community->ngpps; gpp++) {
const struct intel_padgroup *padgrp = &community->gpps[gpp];
unsigned long pending, enabled, gpp_offset;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
pending = readl(community->regs + community->is_offset +
padgrp->reg_num * 4);
enabled = readl(community->regs + community->ie_offset +
padgrp->reg_num * 4);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+
/* Only interrupts that are enabled */
pending &= enabled;
irq = irq_find_mapping(gc->irq.domain,
padgrp->gpio_base + gpp_offset);
generic_handle_irq(irq);
-
- ret |= IRQ_HANDLED;
}
+
+ ret += pending ? 1 : 0;
}
return ret;
{
const struct intel_community *community;
struct intel_pinctrl *pctrl = data;
- irqreturn_t ret = IRQ_NONE;
- int i;
+ unsigned int i;
+ int ret = 0;
/* Need to check all communities for pending interrupts */
for (i = 0; i < pctrl->ncommunities; i++) {
community = &pctrl->communities[i];
- ret |= intel_gpio_community_irq_handler(pctrl, community);
+ ret += intel_gpio_community_irq_handler(pctrl, community);
}
- return ret;
+ return IRQ_RETVAL(ret);
}
static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
}
}
-static u32
-intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
-{
- u32 requested = 0;
- unsigned int i;
-
- for (i = 0; i < size; i++)
- if (gpiochip_is_requested(chip, base + i))
- requested |= BIT(i);
-
- return requested;
-}
-
static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
{
u32 curr, updated;
const struct intel_community *community = &pctrl->communities[c];
const struct intel_padgroup *padgrp = &community->gpps[gpp];
struct device *dev = pctrl->dev;
- u32 requested;
+ const char *dummy;
+ u32 requested = 0;
+ unsigned int i;
if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
return;
- requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size);
+ for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
+ requested |= BIT(i);
+
if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
return;
* @gpps: Pad groups if the controller has variable size pad groups
* @ngpps: Number of pad groups in this community
* @pad_map: Optional non-linear mapping of the pads
+ * @nirqs: Optional total number of IRQs this community can generate
+ * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
* @regs: Community specific common registers (reserved for core driver)
* @pad_regs: Community specific pad registers (reserved for core driver)
*
const struct intel_padgroup *gpps;
size_t ngpps;
const unsigned int *pad_map;
+ unsigned short nirqs;
+ unsigned short acpi_space_id;
/* Reserved for the core driver */
void __iomem *regs;
return 0;
}
+static void lp_gpio_enable_input(void __iomem *reg)
+{
+ iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg);
+}
+
+static void lp_gpio_disable_input(void __iomem *reg)
+{
+ iowrite32(ioread32(reg) | GPINDIS_BIT, reg);
+}
+
static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
}
/* Enable input sensing */
- iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2);
+ lp_gpio_enable_input(conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
raw_spin_lock_irqsave(&lg->lock, flags);
/* Disable input sensing */
- iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2);
+ lp_gpio_disable_input(conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
static int lp_gpio_resume(struct device *dev)
{
struct intel_pinctrl *lg = dev_get_drvdata(dev);
- void __iomem *reg;
+ struct gpio_chip *chip = &lg->chip;
+ const char *dummy;
int i;
/* on some hardware suspend clears input sensing, re-enable it here */
- for (i = 0; i < lg->chip.ngpio; i++) {
- if (gpiochip_is_requested(&lg->chip, i) != NULL) {
- reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
- iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg);
- }
- }
+ for_each_requested_gpio(chip, i, dummy)
+ lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2));
+
return 0;
}
.driver = {
.name = "lp_gpio",
.pm = &lp_gpio_pm_ops,
- .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
+ .acpi_match_table = lynxpoint_gpio_acpi_match,
},
};
PINCTRL_PIN(43, "GP83_SD_D3"),
PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
- PINCTRL_PIN(46, "GP86_SD_LVL_D_DIR"),
+ PINCTRL_PIN(46, "GP86_SD_LS_D_DIR"),
PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
PINCTRL_PIN(48, "GP87_SD_PD"),
PINCTRL_PIN(49, "GP89_SD_WP"),
PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
/* Family 6: GP SSP (22 pins) */
- PINCTRL_PIN(79, "GP120_SPI_3_CLK"),
- PINCTRL_PIN(80, "GP121_SPI_3_SS"),
- PINCTRL_PIN(81, "GP122_SPI_3_RXD"),
- PINCTRL_PIN(82, "GP123_SPI_3_TXD"),
- PINCTRL_PIN(83, "GP102_SPI_4_CLK"),
- PINCTRL_PIN(84, "GP103_SPI_4_SS_0"),
- PINCTRL_PIN(85, "GP104_SPI_4_SS_1"),
- PINCTRL_PIN(86, "GP105_SPI_4_SS_2"),
- PINCTRL_PIN(87, "GP106_SPI_4_SS_3"),
- PINCTRL_PIN(88, "GP107_SPI_4_RXD"),
- PINCTRL_PIN(89, "GP108_SPI_4_TXD"),
- PINCTRL_PIN(90, "GP109_SPI_5_CLK"),
- PINCTRL_PIN(91, "GP110_SPI_5_SS_0"),
- PINCTRL_PIN(92, "GP111_SPI_5_SS_1"),
- PINCTRL_PIN(93, "GP112_SPI_5_SS_2"),
- PINCTRL_PIN(94, "GP113_SPI_5_SS_3"),
- PINCTRL_PIN(95, "GP114_SPI_5_RXD"),
- PINCTRL_PIN(96, "GP115_SPI_5_TXD"),
- PINCTRL_PIN(97, "GP116_SPI_6_CLK"),
- PINCTRL_PIN(98, "GP117_SPI_6_SS"),
- PINCTRL_PIN(99, "GP118_SPI_6_RXD"),
- PINCTRL_PIN(100, "GP119_SPI_6_TXD"),
+ PINCTRL_PIN(79, "GP120_SPI_0_CLK"),
+ PINCTRL_PIN(80, "GP121_SPI_0_SS"),
+ PINCTRL_PIN(81, "GP122_SPI_0_RXD"),
+ PINCTRL_PIN(82, "GP123_SPI_0_TXD"),
+ PINCTRL_PIN(83, "GP102_SPI_1_CLK"),
+ PINCTRL_PIN(84, "GP103_SPI_1_SS0"),
+ PINCTRL_PIN(85, "GP104_SPI_1_SS1"),
+ PINCTRL_PIN(86, "GP105_SPI_1_SS2"),
+ PINCTRL_PIN(87, "GP106_SPI_1_SS3"),
+ PINCTRL_PIN(88, "GP107_SPI_1_RXD"),
+ PINCTRL_PIN(89, "GP108_SPI_1_TXD"),
+ PINCTRL_PIN(90, "GP109_SPI_2_CLK"),
+ PINCTRL_PIN(91, "GP110_SPI_2_SS0"),
+ PINCTRL_PIN(92, "GP111_SPI_2_SS1"),
+ PINCTRL_PIN(93, "GP112_SPI_2_SS2"),
+ PINCTRL_PIN(94, "GP113_SPI_2_SS3"),
+ PINCTRL_PIN(95, "GP114_SPI_2_RXD"),
+ PINCTRL_PIN(96, "GP115_SPI_2_TXD"),
+ PINCTRL_PIN(97, "GP116_SPI_3_CLK"),
+ PINCTRL_PIN(98, "GP117_SPI_3_SS"),
+ PINCTRL_PIN(99, "GP118_SPI_3_RXD"),
+ PINCTRL_PIN(100, "GP119_SPI_3_TXD"),
/* Family 7: I2C (14 pins) */
PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
};
static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
+static const unsigned int mrfld_i2s2_pins[] = { 75, 76, 77, 78 };
static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
static const struct intel_pingroup mrfld_groups[] = {
PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
+ PIN_GROUP("i2s2_grp", mrfld_i2s2_pins, 1),
PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
};
static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
+static const char * const mrfld_i2s2_groups[] = { "i2s2_grp" };
static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
static const struct intel_function mrfld_functions[] = {
FUNCTION("sdio", mrfld_sdio_groups),
+ FUNCTION("i2s2", mrfld_i2s2_groups),
FUNCTION("spi5", mrfld_spi5_groups),
FUNCTION("uart0", mrfld_uart0_groups),
FUNCTION("uart1", mrfld_uart1_groups),
.ncommunities = ARRAY_SIZE(tgllp_communities),
};
+/* Tiger Lake-H */
+static const struct pinctrl_pin_desc tglh_pins[] = {
+ /* GPP_A */
+ PINCTRL_PIN(0, "SPI0_IO_2"),
+ PINCTRL_PIN(1, "SPI0_IO_3"),
+ PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
+ PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
+ PINCTRL_PIN(4, "SPI0_TPM_CSB"),
+ PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
+ PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
+ PINCTRL_PIN(7, "SPI0_CLK"),
+ PINCTRL_PIN(8, "ESPI_IO_0"),
+ PINCTRL_PIN(9, "ESPI_IO_1"),
+ PINCTRL_PIN(10, "ESPI_IO_2"),
+ PINCTRL_PIN(11, "ESPI_IO_3"),
+ PINCTRL_PIN(12, "ESPI_CS0B"),
+ PINCTRL_PIN(13, "ESPI_CLK"),
+ PINCTRL_PIN(14, "ESPI_RESETB"),
+ PINCTRL_PIN(15, "ESPI_CS1B"),
+ PINCTRL_PIN(16, "ESPI_CS2B"),
+ PINCTRL_PIN(17, "ESPI_CS3B"),
+ PINCTRL_PIN(18, "ESPI_ALERT0B"),
+ PINCTRL_PIN(19, "ESPI_ALERT1B"),
+ PINCTRL_PIN(20, "ESPI_ALERT2B"),
+ PINCTRL_PIN(21, "ESPI_ALERT3B"),
+ PINCTRL_PIN(22, "GPPC_A_14"),
+ PINCTRL_PIN(23, "SPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
+ /* GPP_R */
+ PINCTRL_PIN(25, "HDA_BCLK"),
+ PINCTRL_PIN(26, "HDA_SYNC"),
+ PINCTRL_PIN(27, "HDA_SDO"),
+ PINCTRL_PIN(28, "HDA_SDI_0"),
+ PINCTRL_PIN(29, "HDA_RSTB"),
+ PINCTRL_PIN(30, "HDA_SDI_1"),
+ PINCTRL_PIN(31, "GPP_R_6"),
+ PINCTRL_PIN(32, "GPP_R_7"),
+ PINCTRL_PIN(33, "GPP_R_8"),
+ PINCTRL_PIN(34, "PCIE_LNK_DOWN"),
+ PINCTRL_PIN(35, "ISH_UART0_RTSB"),
+ PINCTRL_PIN(36, "SX_EXIT_HOLDOFFB"),
+ PINCTRL_PIN(37, "CLKOUT_48"),
+ PINCTRL_PIN(38, "ISH_GP_7"),
+ PINCTRL_PIN(39, "ISH_GP_0"),
+ PINCTRL_PIN(40, "ISH_GP_1"),
+ PINCTRL_PIN(41, "ISH_GP_2"),
+ PINCTRL_PIN(42, "ISH_GP_3"),
+ PINCTRL_PIN(43, "ISH_GP_4"),
+ PINCTRL_PIN(44, "ISH_GP_5"),
+ /* GPP_B */
+ PINCTRL_PIN(45, "GSPI0_CS1B"),
+ PINCTRL_PIN(46, "GSPI1_CS1B"),
+ PINCTRL_PIN(47, "VRALERTB"),
+ PINCTRL_PIN(48, "CPU_GP_2"),
+ PINCTRL_PIN(49, "CPU_GP_3"),
+ PINCTRL_PIN(50, "SRCCLKREQB_0"),
+ PINCTRL_PIN(51, "SRCCLKREQB_1"),
+ PINCTRL_PIN(52, "SRCCLKREQB_2"),
+ PINCTRL_PIN(53, "SRCCLKREQB_3"),
+ PINCTRL_PIN(54, "SRCCLKREQB_4"),
+ PINCTRL_PIN(55, "SRCCLKREQB_5"),
+ PINCTRL_PIN(56, "I2S_MCLK"),
+ PINCTRL_PIN(57, "SLP_S0B"),
+ PINCTRL_PIN(58, "PLTRSTB"),
+ PINCTRL_PIN(59, "SPKR"),
+ PINCTRL_PIN(60, "GSPI0_CS0B"),
+ PINCTRL_PIN(61, "GSPI0_CLK"),
+ PINCTRL_PIN(62, "GSPI0_MISO"),
+ PINCTRL_PIN(63, "GSPI0_MOSI"),
+ PINCTRL_PIN(64, "GSPI1_CS0B"),
+ PINCTRL_PIN(65, "GSPI1_CLK"),
+ PINCTRL_PIN(66, "GSPI1_MISO"),
+ PINCTRL_PIN(67, "GSPI1_MOSI"),
+ PINCTRL_PIN(68, "SML1ALERTB"),
+ PINCTRL_PIN(69, "GSPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(70, "GSPI1_CLK_LOOPBK"),
+ /* vGPIO_0 */
+ PINCTRL_PIN(71, "ESPI_USB_OCB_0"),
+ PINCTRL_PIN(72, "ESPI_USB_OCB_1"),
+ PINCTRL_PIN(73, "ESPI_USB_OCB_2"),
+ PINCTRL_PIN(74, "ESPI_USB_OCB_3"),
+ PINCTRL_PIN(75, "USB_CPU_OCB_0"),
+ PINCTRL_PIN(76, "USB_CPU_OCB_1"),
+ PINCTRL_PIN(77, "USB_CPU_OCB_2"),
+ PINCTRL_PIN(78, "USB_CPU_OCB_3"),
+ /* GPP_D */
+ PINCTRL_PIN(79, "SPI1_CSB"),
+ PINCTRL_PIN(80, "SPI1_CLK"),
+ PINCTRL_PIN(81, "SPI1_MISO_IO_1"),
+ PINCTRL_PIN(82, "SPI1_MOSI_IO_0"),
+ PINCTRL_PIN(83, "SML1CLK"),
+ PINCTRL_PIN(84, "I2S2_SFRM"),
+ PINCTRL_PIN(85, "I2S2_TXD"),
+ PINCTRL_PIN(86, "I2S2_RXD"),
+ PINCTRL_PIN(87, "I2S2_SCLK"),
+ PINCTRL_PIN(88, "SML0CLK"),
+ PINCTRL_PIN(89, "SML0DATA"),
+ PINCTRL_PIN(90, "GPP_D_11"),
+ PINCTRL_PIN(91, "ISH_UART0_CTSB"),
+ PINCTRL_PIN(92, "SPI1_IO_2"),
+ PINCTRL_PIN(93, "SPI1_IO_3"),
+ PINCTRL_PIN(94, "SML1DATA"),
+ PINCTRL_PIN(95, "GSPI3_CS0B"),
+ PINCTRL_PIN(96, "GSPI3_CLK"),
+ PINCTRL_PIN(97, "GSPI3_MISO"),
+ PINCTRL_PIN(98, "GSPI3_MOSI"),
+ PINCTRL_PIN(99, "UART3_RXD"),
+ PINCTRL_PIN(100, "UART3_TXD"),
+ PINCTRL_PIN(101, "UART3_RTSB"),
+ PINCTRL_PIN(102, "UART3_CTSB"),
+ PINCTRL_PIN(103, "SPI1_CLK_LOOPBK"),
+ PINCTRL_PIN(104, "GSPI3_CLK_LOOPBK"),
+ /* GPP_C */
+ PINCTRL_PIN(105, "SMBCLK"),
+ PINCTRL_PIN(106, "SMBDATA"),
+ PINCTRL_PIN(107, "SMBALERTB"),
+ PINCTRL_PIN(108, "ISH_UART0_RXD"),
+ PINCTRL_PIN(109, "ISH_UART0_TXD"),
+ PINCTRL_PIN(110, "SML0ALERTB"),
+ PINCTRL_PIN(111, "ISH_I2C2_SDA"),
+ PINCTRL_PIN(112, "ISH_I2C2_SCL"),
+ PINCTRL_PIN(113, "UART0_RXD"),
+ PINCTRL_PIN(114, "UART0_TXD"),
+ PINCTRL_PIN(115, "UART0_RTSB"),
+ PINCTRL_PIN(116, "UART0_CTSB"),
+ PINCTRL_PIN(117, "UART1_RXD"),
+ PINCTRL_PIN(118, "UART1_TXD"),
+ PINCTRL_PIN(119, "UART1_RTSB"),
+ PINCTRL_PIN(120, "UART1_CTSB"),
+ PINCTRL_PIN(121, "I2C0_SDA"),
+ PINCTRL_PIN(122, "I2C0_SCL"),
+ PINCTRL_PIN(123, "I2C1_SDA"),
+ PINCTRL_PIN(124, "I2C1_SCL"),
+ PINCTRL_PIN(125, "UART2_RXD"),
+ PINCTRL_PIN(126, "UART2_TXD"),
+ PINCTRL_PIN(127, "UART2_RTSB"),
+ PINCTRL_PIN(128, "UART2_CTSB"),
+ /* GPP_S */
+ PINCTRL_PIN(129, "SNDW1_CLK"),
+ PINCTRL_PIN(130, "SNDW1_DATA"),
+ PINCTRL_PIN(131, "SNDW2_CLK"),
+ PINCTRL_PIN(132, "SNDW2_DATA"),
+ PINCTRL_PIN(133, "SNDW3_CLK"),
+ PINCTRL_PIN(134, "SNDW3_DATA"),
+ PINCTRL_PIN(135, "SNDW4_CLK"),
+ PINCTRL_PIN(136, "SNDW4_DATA"),
+ /* GPP_G */
+ PINCTRL_PIN(137, "DDPA_CTRLCLK"),
+ PINCTRL_PIN(138, "DDPA_CTRLDATA"),
+ PINCTRL_PIN(139, "DNX_FORCE_RELOAD"),
+ PINCTRL_PIN(140, "GMII_MDC_0"),
+ PINCTRL_PIN(141, "GMII_MDIO_0"),
+ PINCTRL_PIN(142, "SLP_DRAMB"),
+ PINCTRL_PIN(143, "GPPC_G_6"),
+ PINCTRL_PIN(144, "GPPC_G_7"),
+ PINCTRL_PIN(145, "ISH_SPI_CSB"),
+ PINCTRL_PIN(146, "ISH_SPI_CLK"),
+ PINCTRL_PIN(147, "ISH_SPI_MISO"),
+ PINCTRL_PIN(148, "ISH_SPI_MOSI"),
+ PINCTRL_PIN(149, "DDP1_CTRLCLK"),
+ PINCTRL_PIN(150, "DDP1_CTRLDATA"),
+ PINCTRL_PIN(151, "DDP2_CTRLCLK"),
+ PINCTRL_PIN(152, "DDP2_CTRLDATA"),
+ PINCTRL_PIN(153, "GSPI2_CLK_LOOPBK"),
+ /* vGPIO */
+ PINCTRL_PIN(154, "CNV_BTEN"),
+ PINCTRL_PIN(155, "CNV_BT_HOST_WAKEB"),
+ PINCTRL_PIN(156, "CNV_BT_IF_SELECT"),
+ PINCTRL_PIN(157, "vCNV_BT_UART_TXD"),
+ PINCTRL_PIN(158, "vCNV_BT_UART_RXD"),
+ PINCTRL_PIN(159, "vCNV_BT_UART_CTS_B"),
+ PINCTRL_PIN(160, "vCNV_BT_UART_RTS_B"),
+ PINCTRL_PIN(161, "vCNV_MFUART1_TXD"),
+ PINCTRL_PIN(162, "vCNV_MFUART1_RXD"),
+ PINCTRL_PIN(163, "vCNV_MFUART1_CTS_B"),
+ PINCTRL_PIN(164, "vCNV_MFUART1_RTS_B"),
+ PINCTRL_PIN(165, "vUART0_TXD"),
+ PINCTRL_PIN(166, "vUART0_RXD"),
+ PINCTRL_PIN(167, "vUART0_CTS_B"),
+ PINCTRL_PIN(168, "vUART0_RTS_B"),
+ PINCTRL_PIN(169, "vISH_UART0_TXD"),
+ PINCTRL_PIN(170, "vISH_UART0_RXD"),
+ PINCTRL_PIN(171, "vISH_UART0_CTS_B"),
+ PINCTRL_PIN(172, "vISH_UART0_RTS_B"),
+ PINCTRL_PIN(173, "vCNV_BT_I2S_BCLK"),
+ PINCTRL_PIN(174, "vCNV_BT_I2S_WS_SYNC"),
+ PINCTRL_PIN(175, "vCNV_BT_I2S_SDO"),
+ PINCTRL_PIN(176, "vCNV_BT_I2S_SDI"),
+ PINCTRL_PIN(177, "vI2S2_SCLK"),
+ PINCTRL_PIN(178, "vI2S2_SFRM"),
+ PINCTRL_PIN(179, "vI2S2_TXD"),
+ PINCTRL_PIN(180, "vI2S2_RXD"),
+ /* GPP_E */
+ PINCTRL_PIN(181, "SATAXPCIE_0"),
+ PINCTRL_PIN(182, "SATAXPCIE_1"),
+ PINCTRL_PIN(183, "SATAXPCIE_2"),
+ PINCTRL_PIN(184, "CPU_GP_0"),
+ PINCTRL_PIN(185, "SATA_DEVSLP_0"),
+ PINCTRL_PIN(186, "SATA_DEVSLP_1"),
+ PINCTRL_PIN(187, "SATA_DEVSLP_2"),
+ PINCTRL_PIN(188, "CPU_GP_1"),
+ PINCTRL_PIN(189, "SATA_LEDB"),
+ PINCTRL_PIN(190, "USB2_OCB_0"),
+ PINCTRL_PIN(191, "USB2_OCB_1"),
+ PINCTRL_PIN(192, "USB2_OCB_2"),
+ PINCTRL_PIN(193, "USB2_OCB_3"),
+ /* GPP_F */
+ PINCTRL_PIN(194, "SATAXPCIE_3"),
+ PINCTRL_PIN(195, "SATAXPCIE_4"),
+ PINCTRL_PIN(196, "SATAXPCIE_5"),
+ PINCTRL_PIN(197, "SATAXPCIE_6"),
+ PINCTRL_PIN(198, "SATAXPCIE_7"),
+ PINCTRL_PIN(199, "SATA_DEVSLP_3"),
+ PINCTRL_PIN(200, "SATA_DEVSLP_4"),
+ PINCTRL_PIN(201, "SATA_DEVSLP_5"),
+ PINCTRL_PIN(202, "SATA_DEVSLP_6"),
+ PINCTRL_PIN(203, "SATA_DEVSLP_7"),
+ PINCTRL_PIN(204, "SATA_SCLOCK"),
+ PINCTRL_PIN(205, "SATA_SLOAD"),
+ PINCTRL_PIN(206, "SATA_SDATAOUT1"),
+ PINCTRL_PIN(207, "SATA_SDATAOUT0"),
+ PINCTRL_PIN(208, "PS_ONB"),
+ PINCTRL_PIN(209, "M2_SKT2_CFG_0"),
+ PINCTRL_PIN(210, "M2_SKT2_CFG_1"),
+ PINCTRL_PIN(211, "M2_SKT2_CFG_2"),
+ PINCTRL_PIN(212, "M2_SKT2_CFG_3"),
+ PINCTRL_PIN(213, "L_VDDEN"),
+ PINCTRL_PIN(214, "L_BKLTEN"),
+ PINCTRL_PIN(215, "L_BKLTCTL"),
+ PINCTRL_PIN(216, "VNN_CTRL"),
+ PINCTRL_PIN(217, "GPP_F_23"),
+ /* GPP_H */
+ PINCTRL_PIN(218, "SRCCLKREQB_6"),
+ PINCTRL_PIN(219, "SRCCLKREQB_7"),
+ PINCTRL_PIN(220, "SRCCLKREQB_8"),
+ PINCTRL_PIN(221, "SRCCLKREQB_9"),
+ PINCTRL_PIN(222, "SRCCLKREQB_10"),
+ PINCTRL_PIN(223, "SRCCLKREQB_11"),
+ PINCTRL_PIN(224, "SRCCLKREQB_12"),
+ PINCTRL_PIN(225, "SRCCLKREQB_13"),
+ PINCTRL_PIN(226, "SRCCLKREQB_14"),
+ PINCTRL_PIN(227, "SRCCLKREQB_15"),
+ PINCTRL_PIN(228, "SML2CLK"),
+ PINCTRL_PIN(229, "SML2DATA"),
+ PINCTRL_PIN(230, "SML2ALERTB"),
+ PINCTRL_PIN(231, "SML3CLK"),
+ PINCTRL_PIN(232, "SML3DATA"),
+ PINCTRL_PIN(233, "SML3ALERTB"),
+ PINCTRL_PIN(234, "SML4CLK"),
+ PINCTRL_PIN(235, "SML4DATA"),
+ PINCTRL_PIN(236, "SML4ALERTB"),
+ PINCTRL_PIN(237, "ISH_I2C0_SDA"),
+ PINCTRL_PIN(238, "ISH_I2C0_SCL"),
+ PINCTRL_PIN(239, "ISH_I2C1_SDA"),
+ PINCTRL_PIN(240, "ISH_I2C1_SCL"),
+ PINCTRL_PIN(241, "TIME_SYNC_0"),
+ /* GPP_J */
+ PINCTRL_PIN(242, "CNV_PA_BLANKING"),
+ PINCTRL_PIN(243, "CPU_C10_GATEB"),
+ PINCTRL_PIN(244, "CNV_BRI_DT"),
+ PINCTRL_PIN(245, "CNV_BRI_RSP"),
+ PINCTRL_PIN(246, "CNV_RGI_DT"),
+ PINCTRL_PIN(247, "CNV_RGI_RSP"),
+ PINCTRL_PIN(248, "CNV_MFUART2_RXD"),
+ PINCTRL_PIN(249, "CNV_MFUART2_TXD"),
+ PINCTRL_PIN(250, "GPP_J_8"),
+ PINCTRL_PIN(251, "GPP_J_9"),
+ /* GPP_K */
+ PINCTRL_PIN(252, "GSXDOUT"),
+ PINCTRL_PIN(253, "GSXSLOAD"),
+ PINCTRL_PIN(254, "GSXDIN"),
+ PINCTRL_PIN(255, "GSXSRESETB"),
+ PINCTRL_PIN(256, "GSXCLK"),
+ PINCTRL_PIN(257, "ADR_COMPLETE"),
+ PINCTRL_PIN(258, "DDSP_HPD_A"),
+ PINCTRL_PIN(259, "DDSP_HPD_B"),
+ PINCTRL_PIN(260, "CORE_VID_0"),
+ PINCTRL_PIN(261, "CORE_VID_1"),
+ PINCTRL_PIN(262, "DDSP_HPD_C"),
+ PINCTRL_PIN(263, "GPP_K_11"),
+ PINCTRL_PIN(264, "SYS_PWROK"),
+ PINCTRL_PIN(265, "SYS_RESETB"),
+ PINCTRL_PIN(266, "MLK_RSTB"),
+ /* GPP_I */
+ PINCTRL_PIN(267, "PMCALERTB"),
+ PINCTRL_PIN(268, "DDSP_HPD_1"),
+ PINCTRL_PIN(269, "DDSP_HPD_2"),
+ PINCTRL_PIN(270, "DDSP_HPD_3"),
+ PINCTRL_PIN(271, "DDSP_HPD_4"),
+ PINCTRL_PIN(272, "DDPB_CTRLCLK"),
+ PINCTRL_PIN(273, "DDPB_CTRLDATA"),
+ PINCTRL_PIN(274, "DDPC_CTRLCLK"),
+ PINCTRL_PIN(275, "DDPC_CTRLDATA"),
+ PINCTRL_PIN(276, "FUSA_DIAGTEST_EN"),
+ PINCTRL_PIN(277, "FUSA_DIAGTEST_MODE"),
+ PINCTRL_PIN(278, "USB2_OCB_4"),
+ PINCTRL_PIN(279, "USB2_OCB_5"),
+ PINCTRL_PIN(280, "USB2_OCB_6"),
+ PINCTRL_PIN(281, "USB2_OCB_7"),
+ /* JTAG */
+ PINCTRL_PIN(282, "JTAG_TDO"),
+ PINCTRL_PIN(283, "JTAGX"),
+ PINCTRL_PIN(284, "PRDYB"),
+ PINCTRL_PIN(285, "PREQB"),
+ PINCTRL_PIN(286, "JTAG_TDI"),
+ PINCTRL_PIN(287, "JTAG_TMS"),
+ PINCTRL_PIN(288, "JTAG_TCK"),
+ PINCTRL_PIN(289, "DBG_PMODE"),
+ PINCTRL_PIN(290, "CPU_TRSTB"),
+};
+
+static const struct intel_padgroup tglh_community0_gpps[] = {
+ TGL_GPP(0, 0, 24, 0), /* GPP_A */
+ TGL_GPP(1, 25, 44, 128), /* GPP_R */
+ TGL_GPP(2, 45, 70, 32), /* GPP_B */
+ TGL_GPP(3, 71, 78, INTEL_GPIO_BASE_NOMAP), /* vGPIO_0 */
+};
+
+static const struct intel_padgroup tglh_community1_gpps[] = {
+ TGL_GPP(0, 79, 104, 96), /* GPP_D */
+ TGL_GPP(1, 105, 128, 64), /* GPP_C */
+ TGL_GPP(2, 129, 136, 160), /* GPP_S */
+ TGL_GPP(3, 137, 153, 192), /* GPP_G */
+ TGL_GPP(4, 154, 180, 224), /* vGPIO */
+};
+
+static const struct intel_padgroup tglh_community3_gpps[] = {
+ TGL_GPP(0, 181, 193, 256), /* GPP_E */
+ TGL_GPP(1, 194, 217, 288), /* GPP_F */
+};
+
+static const struct intel_padgroup tglh_community4_gpps[] = {
+ TGL_GPP(0, 218, 241, 320), /* GPP_H */
+ TGL_GPP(1, 242, 251, 384), /* GPP_J */
+ TGL_GPP(2, 252, 266, 352), /* GPP_K */
+};
+
+static const struct intel_padgroup tglh_community5_gpps[] = {
+ TGL_GPP(0, 267, 281, 416), /* GPP_I */
+ TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
+};
+
+static const struct intel_community tglh_communities[] = {
+ TGL_COMMUNITY(0, 0, 78, tglh_community0_gpps),
+ TGL_COMMUNITY(1, 79, 180, tglh_community1_gpps),
+ TGL_COMMUNITY(2, 181, 217, tglh_community3_gpps),
+ TGL_COMMUNITY(3, 218, 266, tglh_community4_gpps),
+ TGL_COMMUNITY(4, 267, 290, tglh_community5_gpps),
+};
+
+static const struct intel_pinctrl_soc_data tglh_soc_data = {
+ .pins = tglh_pins,
+ .npins = ARRAY_SIZE(tglh_pins),
+ .communities = tglh_communities,
+ .ncommunities = ARRAY_SIZE(tglh_communities),
+};
+
static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
{ "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
+ { "INT34C6", (kernel_ulong_t)&tglh_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
+config PINCTRL_MT6779
+ tristate "Mediatek MT6779 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+ help
+ Say yes here to support pin controller and gpio driver
+ on Mediatek MT6779 SoC.
+ In MTK platform, we support virtual gpio and use it to
+ map specific eint which doesn't have real gpio pin.
+
config PINCTRL_MT6797
bool "Mediatek MT6797 pin control"
depends on OF
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
+obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng <andy.teng@mediatek.com>
+ *
+ */
+
+#include <linux/module.h>
+#include "pinctrl-mtk-mt6779.h"
+#include "pinctrl-paris.h"
+
+/* MT6779 have multiple bases to program pin configuration listed as the below:
+ * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
+ * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
+ * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 1)
+
+static const struct mtk_pin_field_calc mt6779_pin_mode_range[] = {
+ PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
+ PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
+ PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
+ PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
+ PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
+ PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
+ PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
+ PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
+ PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
+ PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
+ PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4),
+ PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4),
+ PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4),
+ PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4),
+ PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4),
+ PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4),
+ PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
+ PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
+ PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
+ PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
+ PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4),
+ PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4),
+ PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4),
+ PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4),
+ PIN_FIELD_BASE(192, 199, 0, 0x0480, 0x10, 0, 4),
+ PIN_FIELD_BASE(200, 202, 0, 0x0490, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_dir_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x0000, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1),
+ PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10, 0, 1),
+ PIN_FIELD_BASE(96, 127, 0, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(128, 159, 0, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(160, 191, 0, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(192, 202, 0, 0x0060, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_di_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x0200, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0210, 0x10, 0, 1),
+ PIN_FIELD_BASE(64, 95, 0, 0x0220, 0x10, 0, 1),
+ PIN_FIELD_BASE(96, 127, 0, 0x0230, 0x10, 0, 1),
+ PIN_FIELD_BASE(128, 159, 0, 0x0240, 0x10, 0, 1),
+ PIN_FIELD_BASE(160, 191, 0, 0x0250, 0x10, 0, 1),
+ PIN_FIELD_BASE(192, 202, 0, 0x0260, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_do_range[] = {
+ PIN_FIELD_BASE(0, 31, 0, 0x0100, 0x10, 0, 1),
+ PIN_FIELD_BASE(32, 63, 0, 0x0110, 0x10, 0, 1),
+ PIN_FIELD_BASE(64, 95, 0, 0x0120, 0x10, 0, 1),
+ PIN_FIELD_BASE(96, 127, 0, 0x0130, 0x10, 0, 1),
+ PIN_FIELD_BASE(128, 159, 0, 0x0140, 0x10, 0, 1),
+ PIN_FIELD_BASE(160, 191, 0, 0x0150, 0x10, 0, 1),
+ PIN_FIELD_BASE(192, 202, 0, 0x0160, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_ies_range[] = {
+ PIN_FIELD_BASE(0, 9, 6, 0x0030, 0x10, 3, 1),
+ PIN_FIELD_BASE(10, 16, 3, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(17, 18, 6, 0x0030, 0x10, 28, 1),
+ PIN_FIELD_BASE(19, 19, 6, 0x0030, 0x10, 27, 1),
+ PIN_FIELD_BASE(20, 20, 6, 0x0030, 0x10, 26, 1),
+ PIN_FIELD_BASE(21, 24, 6, 0x0030, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, 6, 0x0030, 0x10, 30, 1),
+ PIN_FIELD_BASE(26, 26, 6, 0x0030, 0x10, 23, 1),
+ PIN_FIELD_BASE(27, 27, 6, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(28, 29, 6, 0x0030, 0x10, 24, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(32, 32, 6, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(33, 33, 6, 0x0030, 0x10, 17, 1),
+ PIN_FIELD_BASE(34, 34, 6, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(35, 35, 6, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(36, 36, 6, 0x0030, 0x10, 31, 1),
+ PIN_FIELD_BASE(37, 37, 6, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(38, 41, 6, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(42, 43, 6, 0x0030, 0x10, 1, 1),
+ PIN_FIELD_BASE(44, 44, 6, 0x0030, 0x10, 18, 1),
+ PIN_FIELD_BASE(45, 45, 3, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(46, 46, 3, 0x0050, 0x10, 22, 1),
+ PIN_FIELD_BASE(47, 47, 3, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(48, 48, 3, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(49, 49, 3, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(50, 50, 3, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(53, 54, 3, 0x0050, 0x10, 27, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(56, 56, 3, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(57, 57, 3, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(58, 58, 3, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(59, 60, 3, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 20, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(67, 67, 2, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(68, 68, 2, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(69, 69, 2, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(70, 71, 2, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(72, 72, 4, 0x0020, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 4, 0x0020, 0x10, 2, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x0020, 0x10, 1, 1),
+ PIN_FIELD_BASE(75, 75, 4, 0x0020, 0x10, 4, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x0020, 0x10, 12, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x0020, 0x10, 11, 1),
+ PIN_FIELD_BASE(78, 78, 2, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(79, 79, 2, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(80, 81, 2, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(82, 88, 2, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(89, 89, 2, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(90, 90, 2, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(92, 92, 2, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(93, 93, 4, 0x0020, 0x10, 0, 1),
+ PIN_FIELD_BASE(94, 94, 2, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(95, 95, 4, 0x0020, 0x10, 7, 1),
+ PIN_FIELD_BASE(96, 96, 4, 0x0020, 0x10, 5, 1),
+ PIN_FIELD_BASE(97, 97, 4, 0x0020, 0x10, 8, 1),
+ PIN_FIELD_BASE(98, 98, 4, 0x0020, 0x10, 6, 1),
+ PIN_FIELD_BASE(99, 99, 2, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(100, 100, 2, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(101, 101, 2, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(102, 102, 2, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(103, 103, 2, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(104, 104, 2, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(105, 105, 2, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(106, 106, 2, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(107, 108, 2, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(109, 109, 2, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(110, 110, 2, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(111, 111, 2, 0x0060, 0x10, 18, 1),
+ PIN_FIELD_BASE(112, 112, 2, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(113, 113, 2, 0x0060, 0x10, 17, 1),
+ PIN_FIELD_BASE(114, 115, 2, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(116, 117, 2, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(118, 118, 2, 0x0050, 0x10, 31, 1),
+ PIN_FIELD_BASE(119, 119, 2, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(120, 121, 2, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(122, 123, 2, 0x0050, 0x10, 28, 1),
+ PIN_FIELD_BASE(124, 125, 2, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 127, 1, 0x0030, 0x10, 8, 1),
+ PIN_FIELD_BASE(128, 129, 1, 0x0030, 0x10, 17, 1),
+ PIN_FIELD_BASE(130, 130, 1, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(131, 131, 1, 0x0030, 0x10, 19, 1),
+ PIN_FIELD_BASE(132, 132, 1, 0x0030, 0x10, 21, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0030, 0x10, 20, 1),
+ PIN_FIELD_BASE(134, 135, 1, 0x0030, 0x10, 2, 1),
+ PIN_FIELD_BASE(136, 136, 1, 0x0030, 0x10, 7, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(139, 139, 1, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(140, 141, 1, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(142, 142, 1, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(143, 143, 5, 0x0020, 0x10, 15, 1),
+ PIN_FIELD_BASE(144, 144, 5, 0x0020, 0x10, 17, 1),
+ PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 16, 1),
+ PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 12, 1),
+ PIN_FIELD_BASE(147, 155, 5, 0x0020, 0x10, 0, 1),
+ PIN_FIELD_BASE(156, 157, 5, 0x0020, 0x10, 22, 1),
+ PIN_FIELD_BASE(158, 158, 5, 0x0020, 0x10, 21, 1),
+ PIN_FIELD_BASE(159, 159, 5, 0x0020, 0x10, 24, 1),
+ PIN_FIELD_BASE(160, 161, 5, 0x0020, 0x10, 19, 1),
+ PIN_FIELD_BASE(162, 166, 5, 0x0020, 0x10, 25, 1),
+ PIN_FIELD_BASE(167, 168, 7, 0x0010, 0x10, 1, 1),
+ PIN_FIELD_BASE(169, 169, 7, 0x0010, 0x10, 4, 1),
+ PIN_FIELD_BASE(170, 170, 7, 0x0010, 0x10, 6, 1),
+ PIN_FIELD_BASE(171, 171, 7, 0x0010, 0x10, 8, 1),
+ PIN_FIELD_BASE(172, 172, 7, 0x0010, 0x10, 3, 1),
+ PIN_FIELD_BASE(173, 173, 7, 0x0010, 0x10, 7, 1),
+ PIN_FIELD_BASE(174, 175, 7, 0x0010, 0x10, 9, 1),
+ PIN_FIELD_BASE(176, 176, 7, 0x0010, 0x10, 0, 1),
+ PIN_FIELD_BASE(177, 177, 7, 0x0010, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 7, 0x0010, 0x10, 11, 1),
+ PIN_FIELD_BASE(179, 179, 4, 0x0020, 0x10, 13, 1),
+ PIN_FIELD_BASE(180, 180, 4, 0x0020, 0x10, 10, 1),
+ PIN_FIELD_BASE(181, 183, 1, 0x0030, 0x10, 22, 1),
+ PIN_FIELD_BASE(184, 184, 1, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(185, 185, 1, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(186, 186, 1, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(187, 187, 1, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(188, 188, 1, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(189, 189, 5, 0x0020, 0x10, 9, 1),
+ PIN_FIELD_BASE(190, 190, 5, 0x0020, 0x10, 18, 1),
+ PIN_FIELD_BASE(191, 192, 5, 0x0020, 0x10, 13, 1),
+ PIN_FIELD_BASE(193, 194, 5, 0x0020, 0x10, 10, 1),
+ PIN_FIELD_BASE(195, 195, 2, 0x0050, 0x10, 30, 1),
+ PIN_FIELD_BASE(196, 196, 2, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(197, 197, 2, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(198, 199, 4, 0x0020, 0x10, 14, 1),
+ PIN_FIELD_BASE(200, 201, 6, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(202, 202, 4, 0x0020, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_smt_range[] = {
+ PINS_FIELD_BASE(0, 9, 6, 0x00c0, 0x10, 3, 1),
+ PIN_FIELD_BASE(10, 11, 3, 0x00e0, 0x10, 0, 1),
+ PINS_FIELD_BASE(12, 15, 3, 0x00e0, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, 3, 0x00e0, 0x10, 3, 1),
+ PINS_FIELD_BASE(17, 20, 6, 0x00c0, 0x10, 11, 1),
+ PINS_FIELD_BASE(21, 24, 6, 0x00c0, 0x10, 7, 1),
+ PIN_FIELD_BASE(25, 25, 6, 0x00c0, 0x10, 12, 1),
+ PIN_FIELD_BASE(26, 26, 6, 0x00c0, 0x10, 8, 1),
+ PIN_FIELD_BASE(27, 27, 6, 0x00c0, 0x10, 0, 1),
+ PIN_FIELD_BASE(28, 29, 6, 0x00c0, 0x10, 9, 1),
+ PINS_FIELD_BASE(30, 32, 6, 0x00c0, 0x10, 4, 1),
+ PIN_FIELD_BASE(33, 33, 6, 0x00c0, 0x10, 5, 1),
+ PIN_FIELD_BASE(34, 34, 6, 0x00c0, 0x10, 4, 1),
+ PINS_FIELD_BASE(35, 41, 6, 0x00c0, 0x10, 13, 1),
+ PIN_FIELD_BASE(42, 43, 6, 0x00c0, 0x10, 1, 1),
+ PIN_FIELD_BASE(44, 44, 6, 0x00c0, 0x10, 6, 1),
+ PIN_FIELD_BASE(45, 45, 3, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(46, 46, 3, 0x00e0, 0x10, 13, 1),
+ PINS_FIELD_BASE(47, 50, 3, 0x00e0, 0x10, 14, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(53, 54, 3, 0x00e0, 0x10, 15, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(56, 56, 3, 0x00e0, 0x10, 12, 1),
+ PINS_FIELD_BASE(57, 60, 3, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x00e0, 0x10, 11, 1),
+ PINS_FIELD_BASE(63, 66, 3, 0x00e0, 0x10, 9, 1),
+ PINS_FIELD_BASE(67, 69, 2, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(70, 71, 2, 0x00e0, 0x10, 10, 1),
+ PINS_FIELD_BASE(72, 75, 4, 0x0070, 0x10, 1, 1),
+ PINS_FIELD_BASE(76, 77, 4, 0x0070, 0x10, 4, 1),
+ PINS_FIELD_BASE(78, 86, 2, 0x00e0, 0x10, 1, 1),
+ PINS_FIELD_BASE(87, 92, 2, 0x00e0, 0x10, 2, 1),
+ PIN_FIELD_BASE(93, 93, 4, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(94, 94, 2, 0x00e0, 0x10, 2, 1),
+ PINS_FIELD_BASE(95, 98, 4, 0x0070, 0x10, 2, 1),
+ PINS_FIELD_BASE(99, 104, 2, 0x00e0, 0x10, 12, 1),
+ PINS_FIELD_BASE(105, 109, 2, 0x00e0, 0x10, 0, 1),
+ PIN_FIELD_BASE(110, 110, 2, 0x00e0, 0x10, 14, 1),
+ PIN_FIELD_BASE(111, 111, 2, 0x00e0, 0x10, 16, 1),
+ PIN_FIELD_BASE(112, 112, 2, 0x00e0, 0x10, 13, 1),
+ PIN_FIELD_BASE(113, 113, 2, 0x00e0, 0x10, 15, 1),
+ PINS_FIELD_BASE(114, 115, 2, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(116, 117, 2, 0x00e0, 0x10, 5, 1),
+ PINS_FIELD_BASE(118, 119, 2, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(120, 121, 2, 0x00e0, 0x10, 7, 1),
+ PINS_FIELD_BASE(122, 125, 2, 0x00e0, 0x10, 3, 1),
+ PINS_FIELD_BASE(126, 127, 1, 0x00c0, 0x10, 5, 1),
+ PINS_FIELD_BASE(128, 130, 1, 0x00c0, 0x10, 9, 1),
+ PINS_FIELD_BASE(131, 133, 1, 0x00c0, 0x10, 10, 1),
+ PIN_FIELD_BASE(134, 135, 1, 0x00c0, 0x10, 2, 1),
+ PINS_FIELD_BASE(136, 139, 1, 0x00c0, 0x10, 4, 1),
+ PIN_FIELD_BASE(140, 141, 1, 0x00c0, 0x10, 0, 1),
+ PIN_FIELD_BASE(142, 142, 1, 0x00c0, 0x10, 8, 1),
+ PINS_FIELD_BASE(143, 146, 5, 0x0060, 0x10, 1, 1),
+ PINS_FIELD_BASE(147, 155, 5, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(156, 157, 5, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(158, 158, 5, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(159, 159, 5, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(160, 161, 5, 0x0060, 0x10, 3, 1),
+ PINS_FIELD_BASE(162, 166, 5, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(167, 167, 7, 0x0060, 0x10, 1, 1),
+ PINS_FIELD_BASE(168, 174, 7, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(175, 175, 7, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(176, 176, 7, 0x0060, 0x10, 0, 1),
+ PINS_FIELD_BASE(177, 178, 7, 0x0060, 0x10, 2, 1),
+ PINS_FIELD_BASE(179, 180, 4, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(181, 183, 1, 0x00c0, 0x10, 11, 1),
+ PINS_FIELD_BASE(184, 187, 1, 0x00c0, 0x10, 6, 1),
+ PIN_FIELD_BASE(188, 188, 1, 0x00c0, 0x10, 7, 1),
+ PINS_FIELD_BASE(189, 194, 5, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(195, 195, 2, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(196, 196, 2, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(197, 197, 2, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(198, 199, 4, 0x0070, 0x10, 5, 1),
+ PIN_FIELD_BASE(200, 201, 6, 0x00c0, 0x10, 14, 1),
+ PIN_FIELD_BASE(202, 202, 4, 0x0070, 0x10, 3, 1),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_pu_range[] = {
+ PIN_FIELD_BASE(0, 9, 6, 0x0070, 0x10, 3, 1),
+ PIN_FIELD_BASE(16, 16, 3, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(17, 18, 6, 0x0070, 0x10, 28, 1),
+ PIN_FIELD_BASE(19, 19, 6, 0x0070, 0x10, 27, 1),
+ PIN_FIELD_BASE(20, 20, 6, 0x0070, 0x10, 26, 1),
+ PIN_FIELD_BASE(21, 24, 6, 0x0070, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, 6, 0x0070, 0x10, 30, 1),
+ PIN_FIELD_BASE(26, 26, 6, 0x0070, 0x10, 23, 1),
+ PIN_FIELD_BASE(27, 27, 6, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(28, 29, 6, 0x0070, 0x10, 24, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0070, 0x10, 16, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0070, 0x10, 13, 1),
+ PIN_FIELD_BASE(32, 32, 6, 0x0070, 0x10, 15, 1),
+ PIN_FIELD_BASE(33, 33, 6, 0x0070, 0x10, 17, 1),
+ PIN_FIELD_BASE(34, 34, 6, 0x0070, 0x10, 14, 1),
+ PIN_FIELD_BASE(35, 35, 6, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(36, 36, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(37, 37, 6, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 41, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 43, 6, 0x0070, 0x10, 1, 1),
+ PIN_FIELD_BASE(44, 44, 6, 0x0070, 0x10, 18, 1),
+ PIN_FIELD_BASE(45, 45, 3, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(46, 46, 3, 0x0080, 0x10, 12, 1),
+ PIN_FIELD_BASE(47, 47, 3, 0x0080, 0x10, 15, 1),
+ PIN_FIELD_BASE(48, 48, 3, 0x0080, 0x10, 14, 1),
+ PIN_FIELD_BASE(49, 49, 3, 0x0080, 0x10, 16, 1),
+ PIN_FIELD_BASE(50, 50, 3, 0x0080, 0x10, 13, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(53, 54, 3, 0x0080, 0x10, 18, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(56, 56, 3, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0080, 0x10, 8, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(67, 67, 2, 0x00a0, 0x10, 7, 1),
+ PIN_FIELD_BASE(68, 68, 2, 0x00a0, 0x10, 6, 1),
+ PIN_FIELD_BASE(69, 69, 2, 0x00a0, 0x10, 8, 1),
+ PIN_FIELD_BASE(70, 71, 2, 0x00a0, 0x10, 4, 1),
+ PIN_FIELD_BASE(72, 72, 4, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 4, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(75, 75, 4, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(78, 78, 2, 0x0090, 0x10, 18, 1),
+ PIN_FIELD_BASE(79, 79, 2, 0x0090, 0x10, 17, 1),
+ PIN_FIELD_BASE(80, 81, 2, 0x0090, 0x10, 19, 1),
+ PIN_FIELD_BASE(82, 88, 2, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 16, 1),
+ PIN_FIELD_BASE(90, 90, 2, 0x0090, 0x10, 15, 1),
+ PIN_FIELD_BASE(91, 91, 2, 0x0090, 0x10, 14, 1),
+ PIN_FIELD_BASE(92, 92, 2, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(93, 93, 4, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(94, 94, 2, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(95, 95, 4, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(96, 96, 4, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(97, 97, 4, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(98, 98, 4, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(99, 99, 2, 0x00a0, 0x10, 9, 1),
+ PIN_FIELD_BASE(100, 100, 2, 0x00a0, 0x10, 12, 1),
+ PIN_FIELD_BASE(101, 101, 2, 0x00a0, 0x10, 10, 1),
+ PIN_FIELD_BASE(102, 102, 2, 0x00a0, 0x10, 13, 1),
+ PIN_FIELD_BASE(103, 103, 2, 0x00a0, 0x10, 11, 1),
+ PIN_FIELD_BASE(104, 104, 2, 0x00a0, 0x10, 14, 1),
+ PIN_FIELD_BASE(105, 105, 2, 0x0090, 0x10, 10, 1),
+ PIN_FIELD_BASE(106, 106, 2, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(107, 108, 2, 0x0090, 0x10, 12, 1),
+ PIN_FIELD_BASE(109, 109, 2, 0x0090, 0x10, 11, 1),
+ PIN_FIELD_BASE(110, 110, 2, 0x00a0, 0x10, 16, 1),
+ PIN_FIELD_BASE(111, 111, 2, 0x00a0, 0x10, 18, 1),
+ PIN_FIELD_BASE(112, 112, 2, 0x00a0, 0x10, 15, 1),
+ PIN_FIELD_BASE(113, 113, 2, 0x00a0, 0x10, 17, 1),
+ PIN_FIELD_BASE(114, 115, 2, 0x0090, 0x10, 26, 1),
+ PIN_FIELD_BASE(116, 117, 2, 0x0090, 0x10, 21, 1),
+ PIN_FIELD_BASE(118, 118, 2, 0x0090, 0x10, 31, 1),
+ PIN_FIELD_BASE(119, 119, 2, 0x00a0, 0x10, 0, 1),
+ PIN_FIELD_BASE(120, 121, 2, 0x0090, 0x10, 23, 1),
+ PIN_FIELD_BASE(122, 123, 2, 0x0090, 0x10, 28, 1),
+ PIN_FIELD_BASE(124, 125, 2, 0x00a0, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 127, 1, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(140, 141, 1, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(142, 142, 1, 0x0070, 0x10, 9, 1),
+ PIN_FIELD_BASE(143, 143, 5, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(144, 144, 5, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(145, 145, 5, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(146, 146, 5, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(147, 155, 5, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(156, 157, 5, 0x0040, 0x10, 22, 1),
+ PIN_FIELD_BASE(158, 158, 5, 0x0040, 0x10, 21, 1),
+ PIN_FIELD_BASE(159, 159, 5, 0x0040, 0x10, 24, 1),
+ PIN_FIELD_BASE(160, 161, 5, 0x0040, 0x10, 19, 1),
+ PIN_FIELD_BASE(162, 166, 5, 0x0040, 0x10, 25, 1),
+ PIN_FIELD_BASE(179, 179, 4, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(180, 180, 4, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(181, 183, 1, 0x0070, 0x10, 10, 1),
+ PIN_FIELD_BASE(184, 184, 1, 0x0070, 0x10, 6, 1),
+ PIN_FIELD_BASE(185, 185, 1, 0x0070, 0x10, 5, 1),
+ PIN_FIELD_BASE(186, 186, 1, 0x0070, 0x10, 7, 1),
+ PIN_FIELD_BASE(187, 187, 1, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(188, 188, 1, 0x0070, 0x10, 8, 1),
+ PIN_FIELD_BASE(189, 189, 5, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(190, 190, 5, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(191, 192, 5, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(193, 194, 5, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(195, 195, 2, 0x0090, 0x10, 30, 1),
+ PIN_FIELD_BASE(196, 196, 2, 0x0090, 0x10, 25, 1),
+ PIN_FIELD_BASE(197, 197, 2, 0x00a0, 0x10, 3, 1),
+ PIN_FIELD_BASE(198, 199, 4, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(200, 201, 6, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(202, 202, 4, 0x0040, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_pd_range[] = {
+ PIN_FIELD_BASE(0, 9, 6, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(16, 16, 3, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(17, 18, 6, 0x0050, 0x10, 28, 1),
+ PIN_FIELD_BASE(19, 19, 6, 0x0050, 0x10, 27, 1),
+ PIN_FIELD_BASE(20, 20, 6, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(21, 24, 6, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(25, 25, 6, 0x0050, 0x10, 30, 1),
+ PIN_FIELD_BASE(26, 26, 6, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(27, 27, 6, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(28, 29, 6, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(32, 32, 6, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(33, 33, 6, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(34, 34, 6, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(35, 35, 6, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(36, 36, 6, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(37, 37, 6, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 41, 6, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(42, 43, 6, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(44, 44, 6, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(45, 45, 3, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(46, 46, 3, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(47, 47, 3, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(48, 48, 3, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(49, 49, 3, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(50, 50, 3, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(51, 51, 3, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(53, 54, 3, 0x0060, 0x10, 18, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(56, 56, 3, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(67, 67, 2, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(68, 68, 2, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(69, 69, 2, 0x0080, 0x10, 8, 1),
+ PIN_FIELD_BASE(70, 71, 2, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(72, 72, 4, 0x0030, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 4, 0x0030, 0x10, 2, 1),
+ PIN_FIELD_BASE(74, 74, 4, 0x0030, 0x10, 1, 1),
+ PIN_FIELD_BASE(75, 75, 4, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(76, 76, 4, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(77, 77, 4, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(78, 78, 2, 0x0070, 0x10, 18, 1),
+ PIN_FIELD_BASE(79, 79, 2, 0x0070, 0x10, 17, 1),
+ PIN_FIELD_BASE(80, 81, 2, 0x0070, 0x10, 19, 1),
+ PIN_FIELD_BASE(82, 88, 2, 0x0070, 0x10, 1, 1),
+ PIN_FIELD_BASE(89, 89, 2, 0x0070, 0x10, 16, 1),
+ PIN_FIELD_BASE(90, 90, 2, 0x0070, 0x10, 15, 1),
+ PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 14, 1),
+ PIN_FIELD_BASE(92, 92, 2, 0x0070, 0x10, 8, 1),
+ PIN_FIELD_BASE(93, 93, 4, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(94, 94, 2, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(95, 95, 4, 0x0030, 0x10, 7, 1),
+ PIN_FIELD_BASE(96, 96, 4, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(97, 97, 4, 0x0030, 0x10, 8, 1),
+ PIN_FIELD_BASE(98, 98, 4, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(99, 99, 2, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(100, 100, 2, 0x0080, 0x10, 12, 1),
+ PIN_FIELD_BASE(101, 101, 2, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(102, 102, 2, 0x0080, 0x10, 13, 1),
+ PIN_FIELD_BASE(103, 103, 2, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(104, 104, 2, 0x0080, 0x10, 14, 1),
+ PIN_FIELD_BASE(105, 105, 2, 0x0070, 0x10, 10, 1),
+ PIN_FIELD_BASE(106, 106, 2, 0x0070, 0x10, 9, 1),
+ PIN_FIELD_BASE(107, 108, 2, 0x0070, 0x10, 12, 1),
+ PIN_FIELD_BASE(109, 109, 2, 0x0070, 0x10, 11, 1),
+ PIN_FIELD_BASE(110, 110, 2, 0x0080, 0x10, 16, 1),
+ PIN_FIELD_BASE(111, 111, 2, 0x0080, 0x10, 18, 1),
+ PIN_FIELD_BASE(112, 112, 2, 0x0080, 0x10, 15, 1),
+ PIN_FIELD_BASE(113, 113, 2, 0x0080, 0x10, 17, 1),
+ PIN_FIELD_BASE(114, 115, 2, 0x0070, 0x10, 26, 1),
+ PIN_FIELD_BASE(116, 117, 2, 0x0070, 0x10, 21, 1),
+ PIN_FIELD_BASE(118, 118, 2, 0x0070, 0x10, 31, 1),
+ PIN_FIELD_BASE(119, 119, 2, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(120, 121, 2, 0x0070, 0x10, 23, 1),
+ PIN_FIELD_BASE(122, 123, 2, 0x0070, 0x10, 28, 1),
+ PIN_FIELD_BASE(124, 125, 2, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 127, 1, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(140, 141, 1, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(142, 142, 1, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(143, 143, 5, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(144, 144, 5, 0x0030, 0x10, 17, 1),
+ PIN_FIELD_BASE(145, 145, 5, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(146, 146, 5, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(147, 155, 5, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(156, 157, 5, 0x0030, 0x10, 22, 1),
+ PIN_FIELD_BASE(158, 158, 5, 0x0030, 0x10, 21, 1),
+ PIN_FIELD_BASE(159, 159, 5, 0x0030, 0x10, 24, 1),
+ PIN_FIELD_BASE(160, 161, 5, 0x0030, 0x10, 19, 1),
+ PIN_FIELD_BASE(162, 166, 5, 0x0030, 0x10, 25, 1),
+ PIN_FIELD_BASE(179, 179, 4, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(180, 180, 4, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(181, 183, 1, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(184, 184, 1, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(185, 185, 1, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(186, 186, 1, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(187, 187, 1, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(188, 188, 1, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(189, 189, 5, 0x0030, 0x10, 9, 1),
+ PIN_FIELD_BASE(190, 190, 5, 0x0030, 0x10, 18, 1),
+ PIN_FIELD_BASE(191, 192, 5, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(193, 194, 5, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(195, 195, 2, 0x0070, 0x10, 30, 1),
+ PIN_FIELD_BASE(196, 196, 2, 0x0070, 0x10, 25, 1),
+ PIN_FIELD_BASE(197, 197, 2, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(198, 199, 4, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(200, 201, 6, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(202, 202, 4, 0x0030, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_drv_range[] = {
+ PINS_FIELD_BASE(0, 9, 6, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(10, 16, 3, 0x0000, 0x10, 0, 3),
+ PINS_FIELD_BASE(17, 19, 6, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(20, 20, 6, 0x0010, 0x10, 6, 3),
+ PINS_FIELD_BASE(21, 24, 6, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(25, 25, 6, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(26, 26, 6, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(27, 27, 6, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(28, 28, 6, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(29, 29, 6, 0x0010, 0x10, 0, 3),
+ PINS_FIELD_BASE(30, 32, 6, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(33, 33, 6, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(34, 34, 6, 0x0000, 0x10, 12, 3),
+ PINS_FIELD_BASE(35, 41, 6, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(42, 43, 6, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(44, 44, 6, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(45, 45, 3, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(46, 46, 3, 0x0020, 0x10, 0, 3),
+ PINS_FIELD_BASE(47, 49, 3, 0x0020, 0x10, 3, 3),
+ PIN_FIELD_BASE(50, 50, 3, 0x0020, 0x10, 6, 3),
+ PIN_FIELD_BASE(51, 51, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 21, 3),
+ PINS_FIELD_BASE(53, 54, 3, 0x0020, 0x10, 9, 3),
+ PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(56, 56, 3, 0x0010, 0x10, 27, 3),
+ PIN_FIELD_BASE(57, 57, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(58, 58, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(59, 60, 3, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(61, 61, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(62, 62, 3, 0x0010, 0x10, 24, 3),
+ PINS_FIELD_BASE(63, 65, 3, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(66, 66, 3, 0x0010, 0x10, 18, 3),
+ PINS_FIELD_BASE(67, 69, 2, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(70, 71, 2, 0x0010, 0x10, 0, 3),
+ PINS_FIELD_BASE(72, 75, 4, 0x0000, 0x10, 0, 3),
+ PINS_FIELD_BASE(76, 77, 4, 0x0000, 0x10, 15, 3),
+ PINS_FIELD_BASE(78, 86, 2, 0x0000, 0x10, 3, 3),
+ PINS_FIELD_BASE(87, 92, 2, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(93, 93, 4, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(94, 94, 2, 0x0000, 0x10, 6, 3),
+ PINS_FIELD_BASE(95, 96, 4, 0x0000, 0x10, 6, 3),
+ PINS_FIELD_BASE(97, 98, 4, 0x0000, 0x10, 9, 3),
+ PINS_FIELD_BASE(99, 100, 2, 0x0010, 0x10, 6, 3),
+ PINS_FIELD_BASE(101, 102, 2, 0x0010, 0x10, 9, 3),
+ PINS_FIELD_BASE(103, 104, 2, 0x0010, 0x10, 12, 3),
+ PINS_FIELD_BASE(105, 109, 2, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(110, 110, 2, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(111, 111, 2, 0x0010, 0x10, 24, 3),
+ PIN_FIELD_BASE(112, 112, 2, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(113, 113, 2, 0x0010, 0x10, 21, 3),
+ PINS_FIELD_BASE(114, 115, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(116, 117, 2, 0x0000, 0x10, 15, 3),
+ PINS_FIELD_BASE(118, 119, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(120, 121, 2, 0x0000, 0x10, 21, 3),
+ PINS_FIELD_BASE(122, 125, 2, 0x0000, 0x10, 9, 3),
+ PINS_FIELD_BASE(126, 127, 1, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(128, 128, 1, 0x0000, 0x10, 29, 2),
+ PIN_FIELD_BASE(129, 129, 1, 0x0010, 0x10, 0, 2),
+ PIN_FIELD_BASE(130, 130, 1, 0x0000, 0x10, 27, 2),
+ PIN_FIELD_BASE(131, 131, 1, 0x0010, 0x10, 2, 2),
+ PIN_FIELD_BASE(132, 132, 1, 0x0010, 0x10, 6, 2),
+ PIN_FIELD_BASE(133, 133, 1, 0x0010, 0x10, 4, 2),
+ PIN_FIELD_BASE(134, 135, 1, 0x0000, 0x10, 3, 3),
+ PINS_FIELD_BASE(136, 139, 1, 0x0000, 0x10, 9, 3),
+ PINS_FIELD_BASE(140, 141, 1, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(142, 142, 1, 0x0000, 0x10, 24, 3),
+ PINS_FIELD_BASE(143, 146, 5, 0x0000, 0x10, 3, 3),
+ PINS_FIELD_BASE(147, 155, 5, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(156, 157, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(158, 158, 5, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(159, 159, 5, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(160, 161, 5, 0x0000, 0x10, 9, 3),
+ PINS_FIELD_BASE(162, 166, 5, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(167, 167, 7, 0x0000, 0x10, 3, 3),
+ PINS_FIELD_BASE(168, 174, 7, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(175, 175, 7, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(176, 176, 7, 0x0000, 0x10, 0, 3),
+ PINS_FIELD_BASE(177, 178, 7, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(179, 180, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(181, 183, 1, 0x0010, 0x10, 8, 3),
+ PINS_FIELD_BASE(184, 186, 1, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(187, 188, 1, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(189, 189, 5, 0x0000, 0x10, 6, 3),
+ PINS_FIELD_BASE(190, 194, 5, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(195, 195, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(196, 196, 2, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(197, 197, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(198, 199, 4, 0x0000, 0x10, 21, 3),
+ PINS_FIELD_BASE(200, 201, 6, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(202, 202, 4, 0x0000, 0x10, 12, 3),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_pupd_range[] = {
+ PIN_FIELD_BASE(10, 15, 3, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(57, 57, 3, 0x0070, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, 3, 0x0070, 0x10, 8, 1),
+ PIN_FIELD_BASE(59, 60, 3, 0x0070, 0x10, 6, 1),
+ PIN_FIELD_BASE(128, 129, 1, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(130, 130, 1, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(131, 131, 1, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(132, 132, 1, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(134, 135, 1, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(136, 136, 1, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(139, 139, 1, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(167, 168, 7, 0x0020, 0x10, 1, 1),
+ PIN_FIELD_BASE(169, 169, 7, 0x0020, 0x10, 4, 1),
+ PIN_FIELD_BASE(170, 170, 7, 0x0020, 0x10, 6, 1),
+ PIN_FIELD_BASE(171, 171, 7, 0x0020, 0x10, 8, 1),
+ PIN_FIELD_BASE(172, 172, 7, 0x0020, 0x10, 3, 1),
+ PIN_FIELD_BASE(173, 173, 7, 0x0020, 0x10, 7, 1),
+ PIN_FIELD_BASE(174, 175, 7, 0x0020, 0x10, 9, 1),
+ PIN_FIELD_BASE(176, 176, 7, 0x0020, 0x10, 0, 1),
+ PIN_FIELD_BASE(177, 177, 7, 0x0020, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 7, 0x0020, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_r0_range[] = {
+ PIN_FIELD_BASE(10, 15, 3, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(57, 57, 3, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, 3, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(59, 60, 3, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(128, 129, 1, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(130, 130, 1, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(131, 131, 1, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(132, 132, 1, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(134, 135, 1, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(136, 136, 1, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(139, 139, 1, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(167, 168, 7, 0x0030, 0x10, 1, 1),
+ PIN_FIELD_BASE(169, 169, 7, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(170, 170, 7, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(171, 171, 7, 0x0030, 0x10, 8, 1),
+ PIN_FIELD_BASE(172, 172, 7, 0x0030, 0x10, 3, 1),
+ PIN_FIELD_BASE(173, 173, 7, 0x0030, 0x10, 7, 1),
+ PIN_FIELD_BASE(174, 175, 7, 0x0030, 0x10, 9, 1),
+ PIN_FIELD_BASE(176, 176, 7, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(177, 177, 7, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 7, 0x0030, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt6779_pin_r1_range[] = {
+ PIN_FIELD_BASE(10, 15, 3, 0x00a0, 0x10, 0, 1),
+ PIN_FIELD_BASE(57, 57, 3, 0x00a0, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 8, 1),
+ PIN_FIELD_BASE(59, 60, 3, 0x00a0, 0x10, 6, 1),
+ PIN_FIELD_BASE(128, 129, 1, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(130, 130, 1, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(131, 131, 1, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(132, 132, 1, 0x0090, 0x10, 11, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0090, 0x10, 10, 1),
+ PIN_FIELD_BASE(134, 135, 1, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(136, 136, 1, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(139, 139, 1, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(167, 168, 7, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(169, 169, 7, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(170, 170, 7, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(171, 171, 7, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(172, 172, 7, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(173, 173, 7, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(174, 175, 7, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(176, 176, 7, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(177, 177, 7, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 7, 0x0040, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_reg_calc mt6779_reg_cals[PINCTRL_PIN_REG_MAX] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6779_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6779_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6779_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6779_pin_do_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6779_pin_smt_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6779_pin_ies_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6779_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6779_pin_pd_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6779_pin_drv_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6779_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6779_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6779_pin_r1_range),
+};
+
+static const char * const mt6779_pinctrl_register_base_names[] = {
+ "gpio", "iocfg_rm", "iocfg_br", "iocfg_lm", "iocfg_lb",
+ "iocfg_rt", "iocfg_lt", "iocfg_tl",
+};
+
+static const struct mtk_eint_hw mt6779_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num = 195,
+ .db_cnt = 13,
+};
+
+static const struct mtk_pin_soc mt6779_data = {
+ .reg_cal = mt6779_reg_cals,
+ .pins = mtk_pins_mt6779,
+ .npins = ARRAY_SIZE(mtk_pins_mt6779),
+ .ngrps = ARRAY_SIZE(mtk_pins_mt6779),
+ .eint_hw = &mt6779_eint_hw,
+ .gpio_m = 0,
+ .ies_present = true,
+ .base_names = mt6779_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt6779_pinctrl_register_base_names),
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_raw,
+ .drive_get = mtk_pinconf_drive_get_raw,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
+};
+
+static const struct of_device_id mt6779_pinctrl_of_match[] = {
+ { .compatible = "mediatek,mt6779-pinctrl", },
+ { }
+};
+
+static int mt6779_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_paris_pinctrl_probe(pdev, &mt6779_data);
+}
+
+static struct platform_driver mt6779_pinctrl_driver = {
+ .driver = {
+ .name = "mt6779-pinctrl",
+ .of_match_table = mt6779_pinctrl_of_match,
+ },
+ .probe = mt6779_pinctrl_probe,
+};
+
+static int __init mt6779_pinctrl_init(void)
+{
+ return platform_driver_register(&mt6779_pinctrl_driver);
+}
+arch_initcall(mt6779_pinctrl_init);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("MediaTek MT6779 Pinctrl Driver");
return EINT_NA;
}
+/*
+ * Virtual GPIO only used inside SOC and not being exported to outside SOC.
+ * Some modules use virtual GPIO as eint (e.g. pmif or usb).
+ * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
+ * and we can set GPIO as eint.
+ * But some modules use specific eint which doesn't have real GPIO pin.
+ * So we use virtual GPIO to map it.
+ */
+
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
+{
+ const struct mtk_pin_desc *desc;
+ bool virt_gpio = false;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
+
+ if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
+ virt_gpio = true;
+
+ return virt_gpio;
+}
+EXPORT_SYMBOL_GPL(mtk_is_virt_gpio);
+
static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
if (err)
return err;
+ if (mtk_is_virt_gpio(hw, gpio_n))
+ return 0;
+
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
DRV_GRP_MAX,
};
-static const char * const mtk_default_register_base_names[] = {
+static const char * const mtk_default_register_base_names[] __maybe_unused = {
"base",
};
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n);
#endif /* __PINCTRL_MTK_COMMON_V2_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng <andy.teng@mediatek.com>
+ *
+ */
+
+#ifndef __PINCTRL_MTK_MT6779_H
+#define __PINCTRL_MTK_MT6779_H
+
+#include "pinctrl-paris.h"
+
+static const struct mtk_pin_desc mtk_pins_mt6779[] = {
+ MTK_PIN(
+ 0, "GPIO0",
+ MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "SPI6_MI"),
+ MTK_FUNCTION(2, "I2S5_LRCK"),
+ MTK_FUNCTION(3, "TDM_LRCK_2ND"),
+ MTK_FUNCTION(4, "PCM1_SYNC"),
+ MTK_FUNCTION(5, "SCL_6306"),
+ MTK_FUNCTION(6, "TP_GPIO0_AO"),
+ MTK_FUNCTION(7, "PTA_RXD")
+ ),
+ MTK_PIN(
+ 1, "GPIO1",
+ MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "SPI6_CSB"),
+ MTK_FUNCTION(2, "I2S5_DO"),
+ MTK_FUNCTION(3, "TDM_DATA0_2ND"),
+ MTK_FUNCTION(4, "PCM1_DO0"),
+ MTK_FUNCTION(5, "SDA_6306"),
+ MTK_FUNCTION(6, "TP_GPIO1_AO"),
+ MTK_FUNCTION(7, "PTA_TXD")
+ ),
+ MTK_PIN(
+ 2, "GPIO2",
+ MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "SPI6_MO"),
+ MTK_FUNCTION(2, "I2S5_BCK"),
+ MTK_FUNCTION(3, "TDM_BCK_2ND"),
+ MTK_FUNCTION(4, "PCM1_CLK"),
+ MTK_FUNCTION(5, "MD_INT1_C2K_UIM0_HOT_PLUG"),
+ MTK_FUNCTION(6, "TP_GPIO2_AO")
+ ),
+ MTK_PIN(
+ 3, "GPIO3",
+ MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "SPI6_CLK"),
+ MTK_FUNCTION(2, "I2S5_MCK"),
+ MTK_FUNCTION(3, "TDM_MCK_2ND"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "MD_INT2_C2K_UIM1_HOT_PLUG"),
+ MTK_FUNCTION(6, "TP_GPIO3_AO")
+ ),
+ MTK_PIN(
+ 4, "GPIO4",
+ MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "SPI7_MI"),
+ MTK_FUNCTION(2, "I2S0_MCK"),
+ MTK_FUNCTION(3, "TDM_DATA1_2ND"),
+ MTK_FUNCTION(4, "PCM1_DO1"),
+ MTK_FUNCTION(5, "DMIC1_CLK"),
+ MTK_FUNCTION(6, "TP_GPIO4_AO"),
+ MTK_FUNCTION(7, "SCL8")
+ ),
+ MTK_PIN(
+ 5, "GPIO5",
+ MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "SPI7_CSB"),
+ MTK_FUNCTION(2, "I2S0_BCK"),
+ MTK_FUNCTION(3, "TDM_DATA2_2ND"),
+ MTK_FUNCTION(4, "PCM1_DO2"),
+ MTK_FUNCTION(5, "DMIC1_DAT"),
+ MTK_FUNCTION(6, "TP_GPIO5_AO"),
+ MTK_FUNCTION(7, "SDA8")
+ ),
+ MTK_PIN(
+ 6, "GPIO6",
+ MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "SPI7_MO"),
+ MTK_FUNCTION(2, "I2S0_LRCK"),
+ MTK_FUNCTION(3, "TDM_DATA3_2ND"),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "DMIC_CLK"),
+ MTK_FUNCTION(6, "TP_GPIO6_AO"),
+ MTK_FUNCTION(7, "SCL9")
+ ),
+ MTK_PIN(
+ 7, "GPIO7",
+ MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "SPI7_CLK"),
+ MTK_FUNCTION(2, "I2S0_DI"),
+ MTK_FUNCTION(3, "SRCLKENAI1"),
+ MTK_FUNCTION(4, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(5, "DMIC_DAT"),
+ MTK_FUNCTION(6, "TP_GPIO7_AO"),
+ MTK_FUNCTION(7, "SDA9")
+ ),
+ MTK_PIN(
+ 8, "GPIO8",
+ MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "PWM_0"),
+ MTK_FUNCTION(2, "I2S2_DI2"),
+ MTK_FUNCTION(3, "SRCLKENAI0"),
+ MTK_FUNCTION(4, "URXD1"),
+ MTK_FUNCTION(5, "I2S0_MCK"),
+ MTK_FUNCTION(6, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(7, "IDDIG")
+ ),
+ MTK_PIN(
+ 9, "GPIO9",
+ MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "PWM_3"),
+ MTK_FUNCTION(2, "MD_INT0"),
+ MTK_FUNCTION(3, "SRCLKENAI1"),
+ MTK_FUNCTION(4, "UTXD1"),
+ MTK_FUNCTION(5, "I2S0_BCK"),
+ MTK_FUNCTION(6, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(7, "USB_DRVVBUS")
+ ),
+ MTK_PIN(
+ 10, "GPIO10",
+ MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "MSDC1_CLK_A"),
+ MTK_FUNCTION(2, "TP_URXD1_AO"),
+ MTK_FUNCTION(3, "I2S1_LRCK"),
+ MTK_FUNCTION(4, "UCTS0"),
+ MTK_FUNCTION(5, "DMIC1_CLK"),
+ MTK_FUNCTION(6, "KPCOL2"),
+ MTK_FUNCTION(7, "SCL8")
+ ),
+ MTK_PIN(
+ 11, "GPIO11",
+ MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "MSDC1_CMD_A"),
+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(4, "URTS0"),
+ MTK_FUNCTION(5, "DMIC1_DAT"),
+ MTK_FUNCTION(6, "KPROW2"),
+ MTK_FUNCTION(7, "SDA8")
+ ),
+ MTK_PIN(
+ 12, "GPIO12",
+ MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "MSDC1_DAT3_A"),
+ MTK_FUNCTION(2, "TP_URXD2_AO"),
+ MTK_FUNCTION(3, "I2S1_MCK"),
+ MTK_FUNCTION(4, "UCTS1"),
+ MTK_FUNCTION(5, "DMIC_CLK"),
+ MTK_FUNCTION(6, "ANT_SEL9"),
+ MTK_FUNCTION(7, "SCL9")
+ ),
+ MTK_PIN(
+ 13, "GPIO13",
+ MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "MSDC1_DAT0_A"),
+ MTK_FUNCTION(2, "TP_UTXD2_AO"),
+ MTK_FUNCTION(3, "I2S1_BCK"),
+ MTK_FUNCTION(4, "URTS1"),
+ MTK_FUNCTION(5, "DMIC_DAT"),
+ MTK_FUNCTION(6, "ANT_SEL10"),
+ MTK_FUNCTION(7, "SDA9")
+ ),
+ MTK_PIN(
+ 14, "GPIO14",
+ MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "MSDC1_DAT2_A"),
+ MTK_FUNCTION(2, "PWM_3"),
+ MTK_FUNCTION(3, "IDDIG"),
+ MTK_FUNCTION(4, "MD_INT0"),
+ MTK_FUNCTION(5, "PTA_RXD"),
+ MTK_FUNCTION(6, "ANT_SEL11")
+ ),
+ MTK_PIN(
+ 15, "GPIO15",
+ MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "MSDC1_DAT1_A"),
+ MTK_FUNCTION(2, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(3, "USB_DRVVBUS"),
+ MTK_FUNCTION(4, "MD_INT1_C2K_UIM0_HOT_PLUG"),
+ MTK_FUNCTION(5, "PTA_TXD"),
+ MTK_FUNCTION(6, "ANT_SEL12")
+ ),
+ MTK_PIN(
+ 16, "GPIO16",
+ MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "SRCLKENAI0"),
+ MTK_FUNCTION(2, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(3, "MFG_EJTAG_TRSTN"),
+ MTK_FUNCTION(4, "MD_INT2_C2K_UIM1_HOT_PLUG"),
+ MTK_FUNCTION(5, "CONN_TCXOENA_REQ"),
+ MTK_FUNCTION(6, "PWM_2"),
+ MTK_FUNCTION(7, "JTRSTN_SEL1")
+ ),
+ MTK_PIN(
+ 17, "GPIO17",
+ MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "SPI0_A_MI"),
+ MTK_FUNCTION(2, "SCP_SPI0_MI"),
+ MTK_FUNCTION(3, "MFG_EJTAG_TDO"),
+ MTK_FUNCTION(4, "DPI_HSYNC"),
+ MTK_FUNCTION(5, "MFG_DFD_JTAG_TDO"),
+ MTK_FUNCTION(6, "DFD_TDO"),
+ MTK_FUNCTION(7, "JTDO_SEL1")
+ ),
+ MTK_PIN(
+ 18, "GPIO18",
+ MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "SPI0_A_MO"),
+ MTK_FUNCTION(2, "SCP_SPI0_MO"),
+ MTK_FUNCTION(3, "MFG_EJTAG_TDI"),
+ MTK_FUNCTION(4, "DPI_VSYNC"),
+ MTK_FUNCTION(5, "MFG_DFD_JTAG_TDI"),
+ MTK_FUNCTION(6, "DFD_TDI"),
+ MTK_FUNCTION(7, "JTDI_SEL1")
+ ),
+ MTK_PIN(
+ 19, "GPIO19",
+ MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "SPI0_A_CSB"),
+ MTK_FUNCTION(2, "SCP_SPI0_CS"),
+ MTK_FUNCTION(3, "MFG_EJTAG_TMS"),
+ MTK_FUNCTION(4, "DPI_DE"),
+ MTK_FUNCTION(5, "MFG_DFD_JTAG_TMS"),
+ MTK_FUNCTION(6, "DFD_TMS"),
+ MTK_FUNCTION(7, "JTMS_SEL1")
+ ),
+ MTK_PIN(
+ 20, "GPIO20",
+ MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "SPI0_A_CLK"),
+ MTK_FUNCTION(2, "SCP_SPI0_CK"),
+ MTK_FUNCTION(3, "MFG_EJTAG_TCK"),
+ MTK_FUNCTION(4, "DPI_CK"),
+ MTK_FUNCTION(5, "MFG_DFD_JTAG_TCK"),
+ MTK_FUNCTION(6, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "JTCK_SEL1")
+ ),
+ MTK_PIN(
+ 21, "GPIO21",
+ MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "PWM_0"),
+ MTK_FUNCTION(2, "CMFLASH0"),
+ MTK_FUNCTION(3, "CMVREF2"),
+ MTK_FUNCTION(4, "CLKM0"),
+ MTK_FUNCTION(5, "ANT_SEL9"),
+ MTK_FUNCTION(6, "CONN_TCXOENA_REQ"),
+ MTK_FUNCTION(7, "DBG_MON_A27")
+ ),
+ MTK_PIN(
+ 22, "GPIO22",
+ MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "PWM_1"),
+ MTK_FUNCTION(2, "CMFLASH1"),
+ MTK_FUNCTION(3, "CMVREF3"),
+ MTK_FUNCTION(4, "CLKM1"),
+ MTK_FUNCTION(5, "ANT_SEL10"),
+ MTK_FUNCTION(7, "DBG_MON_A28")
+ ),
+ MTK_PIN(
+ 23, "GPIO23",
+ MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "PWM_2"),
+ MTK_FUNCTION(2, "CMFLASH2"),
+ MTK_FUNCTION(3, "CMVREF0"),
+ MTK_FUNCTION(4, "CLKM2"),
+ MTK_FUNCTION(5, "ANT_SEL11"),
+ MTK_FUNCTION(7, "DBG_MON_A29")
+ ),
+ MTK_PIN(
+ 24, "GPIO24",
+ MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "PWM_0"),
+ MTK_FUNCTION(2, "CMFLASH3"),
+ MTK_FUNCTION(3, "CMVREF1"),
+ MTK_FUNCTION(4, "CLKM3"),
+ MTK_FUNCTION(5, "ANT_SEL12"),
+ MTK_FUNCTION(7, "DBG_MON_A30")
+ ),
+ MTK_PIN(
+ 25, "GPIO25",
+ MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "SRCLKENAI0"),
+ MTK_FUNCTION(2, "UCTS0"),
+ MTK_FUNCTION(3, "SCL8"),
+ MTK_FUNCTION(4, "CMVREF4"),
+ MTK_FUNCTION(5, "I2S0_LRCK"),
+ MTK_FUNCTION(6, "CONN_TCXOENA_REQ"),
+ MTK_FUNCTION(7, "DBG_MON_A31")
+ ),
+ MTK_PIN(
+ 26, "GPIO26",
+ MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "PWM_0"),
+ MTK_FUNCTION(2, "URTS0"),
+ MTK_FUNCTION(3, "SDA8"),
+ MTK_FUNCTION(4, "CLKM0"),
+ MTK_FUNCTION(5, "I2S0_DI"),
+ MTK_FUNCTION(6, "AGPS_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A32")
+ ),
+ MTK_PIN(
+ 27, "GPIO27",
+ MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "AP_GOOD")
+ ),
+ MTK_PIN(
+ 28, "GPIO28",
+ MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "SCL5")
+ ),
+ MTK_PIN(
+ 29, "GPIO29",
+ MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "SDA5")
+ ),
+ MTK_PIN(
+ 30, "GPIO30",
+ MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "I2S1_MCK"),
+ MTK_FUNCTION(2, "I2S3_MCK"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(4, "DPI_D0"),
+ MTK_FUNCTION(5, "SPI4_MI"),
+ MTK_FUNCTION(6, "CONN_MCU_DBGI_N")
+ ),
+ MTK_PIN(
+ 31, "GPIO31",
+ MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "I2S1_BCK"),
+ MTK_FUNCTION(2, "I2S3_BCK"),
+ MTK_FUNCTION(3, "I2S2_BCK"),
+ MTK_FUNCTION(4, "DPI_D1"),
+ MTK_FUNCTION(5, "SPI4_CSB"),
+ MTK_FUNCTION(6, "CONN_MCU_TDO")
+ ),
+ MTK_PIN(
+ 32, "GPIO32",
+ MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "I2S1_LRCK"),
+ MTK_FUNCTION(2, "I2S3_LRCK"),
+ MTK_FUNCTION(3, "I2S2_LRCK"),
+ MTK_FUNCTION(4, "DPI_D2"),
+ MTK_FUNCTION(5, "SPI4_MO"),
+ MTK_FUNCTION(6, "CONN_MCU_TDI")
+ ),
+ MTK_PIN(
+ 33, "GPIO33",
+ MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "I2S2_DI"),
+ MTK_FUNCTION(2, "I2S0_DI"),
+ MTK_FUNCTION(3, "I2S5_DO"),
+ MTK_FUNCTION(4, "DPI_D3"),
+ MTK_FUNCTION(5, "SPI4_CLK"),
+ MTK_FUNCTION(6, "CONN_MCU_TMS")
+ ),
+ MTK_PIN(
+ 34, "GPIO34",
+ MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "I2S1_DO"),
+ MTK_FUNCTION(2, "I2S3_DO"),
+ MTK_FUNCTION(3, "I2S2_DI2"),
+ MTK_FUNCTION(4, "DPI_D4"),
+ MTK_FUNCTION(5, "AGPS_SYNC"),
+ MTK_FUNCTION(6, "CONN_MCU_TCK")
+ ),
+ MTK_PIN(
+ 35, "GPIO35",
+ MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "TDM_LRCK"),
+ MTK_FUNCTION(2, "I2S1_LRCK"),
+ MTK_FUNCTION(3, "I2S5_LRCK"),
+ MTK_FUNCTION(4, "DPI_D5"),
+ MTK_FUNCTION(5, "SPI5_A_MO"),
+ MTK_FUNCTION(6, "IO_JTAG_TDI"),
+ MTK_FUNCTION(7, "PWM_2")
+ ),
+ MTK_PIN(
+ 36, "GPIO36",
+ MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "TDM_BCK"),
+ MTK_FUNCTION(2, "I2S1_BCK"),
+ MTK_FUNCTION(3, "I2S5_BCK"),
+ MTK_FUNCTION(4, "DPI_D6"),
+ MTK_FUNCTION(5, "SPI5_A_CSB"),
+ MTK_FUNCTION(6, "IO_JTAG_TRSTN"),
+ MTK_FUNCTION(7, "SRCLKENAI1")
+ ),
+ MTK_PIN(
+ 37, "GPIO37",
+ MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "TDM_MCK"),
+ MTK_FUNCTION(2, "I2S1_MCK"),
+ MTK_FUNCTION(3, "I2S5_MCK"),
+ MTK_FUNCTION(4, "DPI_D7"),
+ MTK_FUNCTION(5, "SPI5_A_MI"),
+ MTK_FUNCTION(6, "IO_JTAG_TCK"),
+ MTK_FUNCTION(7, "SRCLKENAI0")
+ ),
+ MTK_PIN(
+ 38, "GPIO38",
+ MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "TDM_DATA0"),
+ MTK_FUNCTION(2, "I2S2_DI"),
+ MTK_FUNCTION(3, "I2S5_DO"),
+ MTK_FUNCTION(4, "DPI_D8"),
+ MTK_FUNCTION(5, "SPI5_A_CLK"),
+ MTK_FUNCTION(6, "IO_JTAG_TDO"),
+ MTK_FUNCTION(7, "CONN_TCXOENA_REQ")
+ ),
+ MTK_PIN(
+ 39, "GPIO39",
+ MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "TDM_DATA1"),
+ MTK_FUNCTION(2, "I2S1_DO"),
+ MTK_FUNCTION(3, "I2S2_DI2"),
+ MTK_FUNCTION(4, "DPI_D9"),
+ MTK_FUNCTION(5, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(6, "IO_JTAG_TMS"),
+ MTK_FUNCTION(7, "IDDIG")
+ ),
+ MTK_PIN(
+ 40, "GPIO40",
+ MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "TDM_DATA2"),
+ MTK_FUNCTION(2, "SCL9"),
+ MTK_FUNCTION(3, "PWM_3"),
+ MTK_FUNCTION(4, "DPI_D10"),
+ MTK_FUNCTION(5, "SRCLKENAI0"),
+ MTK_FUNCTION(6, "DAP_MD32_SWD"),
+ MTK_FUNCTION(7, "USB_DRVVBUS")
+ ),
+ MTK_PIN(
+ 41, "GPIO41",
+ MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "TDM_DATA3"),
+ MTK_FUNCTION(2, "SDA9"),
+ MTK_FUNCTION(3, "PWM_1"),
+ MTK_FUNCTION(4, "DPI_D11"),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(6, "DAP_MD32_SWCK")
+ ),
+ MTK_PIN(
+ 42, "GPIO42",
+ MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "DISP_PWM")
+ ),
+ MTK_PIN(
+ 43, "GPIO43",
+ MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "DSI_TE")
+ ),
+ MTK_PIN(
+ 44, "GPIO44",
+ MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "LCM_RST")
+ ),
+ MTK_PIN(
+ 45, "GPIO45",
+ MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "SCL6"),
+ MTK_FUNCTION(2, "SCP_SCL0"),
+ MTK_FUNCTION(3, "SCP_SCL1"),
+ MTK_FUNCTION(4, "SCL_6306")
+ ),
+ MTK_PIN(
+ 46, "GPIO46",
+ MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "SDA6"),
+ MTK_FUNCTION(2, "SCP_SDA0"),
+ MTK_FUNCTION(3, "SCP_SDA1"),
+ MTK_FUNCTION(4, "SDA_6306")
+ ),
+ MTK_PIN(
+ 47, "GPIO47",
+ MTK_EINT_FUNCTION(0, 47),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "SPI1_A_MI"),
+ MTK_FUNCTION(2, "SCP_SPI1_A_MI"),
+ MTK_FUNCTION(3, "KPCOL2"),
+ MTK_FUNCTION(4, "MD_URXD0"),
+ MTK_FUNCTION(5, "CONN_UART0_RXD"),
+ MTK_FUNCTION(6, "SSPM_URXD_AO"),
+ MTK_FUNCTION(7, "DBG_MON_B32")
+ ),
+ MTK_PIN(
+ 48, "GPIO48",
+ MTK_EINT_FUNCTION(0, 48),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "SPI1_A_CSB"),
+ MTK_FUNCTION(2, "SCP_SPI1_A_CS"),
+ MTK_FUNCTION(3, "KPROW2"),
+ MTK_FUNCTION(4, "MD_UTXD0"),
+ MTK_FUNCTION(5, "CONN_UART0_TXD"),
+ MTK_FUNCTION(6, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(7, "DBG_MON_B31")
+ ),
+ MTK_PIN(
+ 49, "GPIO49",
+ MTK_EINT_FUNCTION(0, 49),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "SPI1_A_MO"),
+ MTK_FUNCTION(2, "SCP_SPI1_A_MO"),
+ MTK_FUNCTION(3, "UCTS0"),
+ MTK_FUNCTION(4, "MD_URXD1"),
+ MTK_FUNCTION(5, "PWM_1"),
+ MTK_FUNCTION(6, "TP_URXD2_AO"),
+ MTK_FUNCTION(7, "DBG_MON_B30")
+ ),
+ MTK_PIN(
+ 50, "GPIO50",
+ MTK_EINT_FUNCTION(0, 50),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "SPI1_A_CLK"),
+ MTK_FUNCTION(2, "SCP_SPI1_A_CK"),
+ MTK_FUNCTION(3, "URTS0"),
+ MTK_FUNCTION(4, "MD_UTXD1"),
+ MTK_FUNCTION(5, "WIFI_TXD"),
+ MTK_FUNCTION(6, "TP_UTXD2_AO"),
+ MTK_FUNCTION(7, "DBG_MON_B29")
+ ),
+ MTK_PIN(
+ 51, "GPIO51",
+ MTK_EINT_FUNCTION(0, 51),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(
+ 52, "GPIO52",
+ MTK_EINT_FUNCTION(0, 52),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(
+ 53, "GPIO53",
+ MTK_EINT_FUNCTION(0, 53),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0"),
+ MTK_FUNCTION(3, "MD_URXD0"),
+ MTK_FUNCTION(4, "MD_URXD1"),
+ MTK_FUNCTION(5, "SSPM_URXD_AO"),
+ MTK_FUNCTION(7, "CONN_UART0_RXD")
+ ),
+ MTK_PIN(
+ 54, "GPIO54",
+ MTK_EINT_FUNCTION(0, 54),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0"),
+ MTK_FUNCTION(3, "MD_UTXD0"),
+ MTK_FUNCTION(4, "MD_UTXD1"),
+ MTK_FUNCTION(5, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(6, "WIFI_TXD"),
+ MTK_FUNCTION(7, "CONN_UART0_TXD")
+ ),
+ MTK_PIN(
+ 55, "GPIO55",
+ MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SCL3"),
+ MTK_FUNCTION(2, "SCP_SCL0"),
+ MTK_FUNCTION(3, "SCP_SCL1"),
+ MTK_FUNCTION(4, "SCL_6306")
+ ),
+ MTK_PIN(
+ 56, "GPIO56",
+ MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "SDA3"),
+ MTK_FUNCTION(2, "SCP_SDA0"),
+ MTK_FUNCTION(3, "SCP_SDA1"),
+ MTK_FUNCTION(4, "SDA_6306")
+ ),
+ MTK_PIN(
+ 57, "GPIO57",
+ MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "KPROW1"),
+ MTK_FUNCTION(2, "PWM_1"),
+ MTK_FUNCTION(3, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(4, "CLKM1"),
+ MTK_FUNCTION(5, "IDDIG"),
+ MTK_FUNCTION(6, "CONN_TCXOENA_REQ"),
+ MTK_FUNCTION(7, "MBISTREADEN_TRIGGER")
+ ),
+ MTK_PIN(
+ 58, "GPIO58",
+ MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "KPROW0"),
+ MTK_FUNCTION(7, "DBG_MON_B28")
+ ),
+ MTK_PIN(
+ 59, "GPIO59",
+ MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "KPCOL0"),
+ MTK_FUNCTION(7, "DBG_MON_B27")
+ ),
+ MTK_PIN(
+ 60, "GPIO60",
+ MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "KPCOL1"),
+ MTK_FUNCTION(2, "PWM_2"),
+ MTK_FUNCTION(3, "UCTS1"),
+ MTK_FUNCTION(4, "CLKM2"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER")
+ ),
+ MTK_PIN(
+ 61, "GPIO61",
+ MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "SCL1"),
+ MTK_FUNCTION(2, "SCP_SCL0"),
+ MTK_FUNCTION(3, "SCP_SCL1")
+ ),
+ MTK_PIN(
+ 62, "GPIO62",
+ MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "SDA1"),
+ MTK_FUNCTION(2, "SCP_SDA0"),
+ MTK_FUNCTION(3, "SCP_SDA1")
+ ),
+ MTK_PIN(
+ 63, "GPIO63",
+ MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "SPI2_MI"),
+ MTK_FUNCTION(2, "SCP_SPI2_MI"),
+ MTK_FUNCTION(3, "KPCOL2"),
+ MTK_FUNCTION(4, "MRG_DI"),
+ MTK_FUNCTION(5, "MD_URXD0"),
+ MTK_FUNCTION(6, "CONN_UART0_RXD"),
+ MTK_FUNCTION(7, "DBG_MON_B26")
+ ),
+ MTK_PIN(
+ 64, "GPIO64",
+ MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "SPI2_CSB"),
+ MTK_FUNCTION(2, "SCP_SPI2_CS"),
+ MTK_FUNCTION(3, "KPROW2"),
+ MTK_FUNCTION(4, "MRG_SYNC"),
+ MTK_FUNCTION(5, "MD_UTXD0"),
+ MTK_FUNCTION(6, "CONN_UART0_TXD"),
+ MTK_FUNCTION(7, "DBG_MON_B25")
+ ),
+ MTK_PIN(
+ 65, "GPIO65",
+ MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "SPI2_MO"),
+ MTK_FUNCTION(2, "SCP_SPI2_MO"),
+ MTK_FUNCTION(3, "SCP_SDA1"),
+ MTK_FUNCTION(4, "MRG_DO"),
+ MTK_FUNCTION(5, "MD_URXD1"),
+ MTK_FUNCTION(6, "PWM_3")
+ ),
+ MTK_PIN(
+ 66, "GPIO66",
+ MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "SPI2_CLK"),
+ MTK_FUNCTION(2, "SCP_SPI2_CK"),
+ MTK_FUNCTION(3, "SCP_SCL1"),
+ MTK_FUNCTION(4, "MRG_CLK"),
+ MTK_FUNCTION(5, "MD_UTXD1"),
+ MTK_FUNCTION(6, "WIFI_TXD")
+ ),
+ MTK_PIN(
+ 67, "GPIO67",
+ MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "I2S3_LRCK"),
+ MTK_FUNCTION(2, "I2S1_LRCK"),
+ MTK_FUNCTION(3, "URXD1"),
+ MTK_FUNCTION(4, "PCM0_SYNC"),
+ MTK_FUNCTION(5, "I2S5_LRCK"),
+ MTK_FUNCTION(6, "ANT_SEL9"),
+ MTK_FUNCTION(7, "DBG_MON_B10")
+ ),
+ MTK_PIN(
+ 68, "GPIO68",
+ MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "I2S3_DO"),
+ MTK_FUNCTION(2, "I2S1_DO"),
+ MTK_FUNCTION(3, "UTXD1"),
+ MTK_FUNCTION(4, "PCM0_DO"),
+ MTK_FUNCTION(5, "I2S5_DO"),
+ MTK_FUNCTION(6, "ANT_SEL10"),
+ MTK_FUNCTION(7, "DBG_MON_B9")
+ ),
+ MTK_PIN(
+ 69, "GPIO69",
+ MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "I2S3_MCK"),
+ MTK_FUNCTION(2, "I2S1_MCK"),
+ MTK_FUNCTION(3, "URTS1"),
+ MTK_FUNCTION(4, "AGPS_SYNC"),
+ MTK_FUNCTION(5, "I2S5_MCK"),
+ MTK_FUNCTION(6, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(7, "DBG_MON_B8")
+ ),
+ MTK_PIN(
+ 70, "GPIO70",
+ MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "I2S2_DI"),
+ MTK_FUNCTION(3, "KPCOL2"),
+ MTK_FUNCTION(4, "PCM0_DI"),
+ MTK_FUNCTION(5, "I2S2_DI2"),
+ MTK_FUNCTION(6, "ANT_SEL11"),
+ MTK_FUNCTION(7, "DBG_MON_B7")
+ ),
+ MTK_PIN(
+ 71, "GPIO71",
+ MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "I2S3_BCK"),
+ MTK_FUNCTION(2, "I2S1_BCK"),
+ MTK_FUNCTION(3, "KPROW2"),
+ MTK_FUNCTION(4, "PCM0_CLK"),
+ MTK_FUNCTION(5, "I2S5_BCK"),
+ MTK_FUNCTION(6, "ANT_SEL12"),
+ MTK_FUNCTION(7, "DBG_MON_B6")
+ ),
+ MTK_PIN(
+ 72, "GPIO72",
+ MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "BPI_BUS19_OLAT0"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS19_OLAT0")
+ ),
+ MTK_PIN(
+ 73, "GPIO73",
+ MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "BPI_BUS18_PA_VM1"),
+ MTK_FUNCTION(2, "CONN_MIPI5_SCLK"),
+ MTK_FUNCTION(3, "MIPI5_SCLK")
+ ),
+ MTK_PIN(
+ 74, "GPIO74",
+ MTK_EINT_FUNCTION(0, 74),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "BPI_BUS17_PA_VM0"),
+ MTK_FUNCTION(2, "CONN_MIPI5_SDATA"),
+ MTK_FUNCTION(3, "MIPI5_SDATA")
+ ),
+ MTK_PIN(
+ 75, "GPIO75",
+ MTK_EINT_FUNCTION(0, 75),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "BPI_BUS20_OLAT1"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS20_OLAT1"),
+ MTK_FUNCTION(3, "RFIC0_BSI_D2")
+ ),
+ MTK_PIN(
+ 76, "GPIO76",
+ MTK_EINT_FUNCTION(0, 76),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D1")
+ ),
+ MTK_PIN(
+ 77, "GPIO77",
+ MTK_EINT_FUNCTION(0, 77),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D0")
+ ),
+ MTK_PIN(
+ 78, "GPIO78",
+ MTK_EINT_FUNCTION(0, 78),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "BPI_BUS7"),
+ MTK_FUNCTION(7, "DBG_MON_B24")
+ ),
+ MTK_PIN(
+ 79, "GPIO79",
+ MTK_EINT_FUNCTION(0, 79),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "BPI_BUS6"),
+ MTK_FUNCTION(7, "DBG_MON_B23")
+ ),
+ MTK_PIN(
+ 80, "GPIO80",
+ MTK_EINT_FUNCTION(0, 80),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "BPI_BUS8"),
+ MTK_FUNCTION(7, "DBG_MON_B22")
+ ),
+ MTK_PIN(
+ 81, "GPIO81",
+ MTK_EINT_FUNCTION(0, 81),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "BPI_BUS9"),
+ MTK_FUNCTION(7, "DBG_MON_B21")
+ ),
+ MTK_PIN(
+ 82, "GPIO82",
+ MTK_EINT_FUNCTION(0, 82),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "BPI_BUS10"),
+ MTK_FUNCTION(7, "DBG_MON_B20")
+ ),
+ MTK_PIN(
+ 83, "GPIO83",
+ MTK_EINT_FUNCTION(0, 83),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "BPI_BUS11"),
+ MTK_FUNCTION(7, "DBG_MON_B19")
+ ),
+ MTK_PIN(
+ 84, "GPIO84",
+ MTK_EINT_FUNCTION(0, 84),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "BPI_BUS12"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS12")
+ ),
+ MTK_PIN(
+ 85, "GPIO85",
+ MTK_EINT_FUNCTION(0, 85),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "BPI_BUS13"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS13")
+ ),
+ MTK_PIN(
+ 86, "GPIO86",
+ MTK_EINT_FUNCTION(0, 86),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "BPI_BUS14"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS14")
+ ),
+ MTK_PIN(
+ 87, "GPIO87",
+ MTK_EINT_FUNCTION(0, 87),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "BPI_BUS15"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS15")
+ ),
+ MTK_PIN(
+ 88, "GPIO88",
+ MTK_EINT_FUNCTION(0, 88),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "BPI_BUS16"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS16")
+ ),
+ MTK_PIN(
+ 89, "GPIO89",
+ MTK_EINT_FUNCTION(0, 89),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "BPI_BUS5"),
+ MTK_FUNCTION(7, "DBG_MON_B18")
+ ),
+ MTK_PIN(
+ 90, "GPIO90",
+ MTK_EINT_FUNCTION(0, 90),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "BPI_BUS4"),
+ MTK_FUNCTION(7, "DBG_MON_B17")
+ ),
+ MTK_PIN(
+ 91, "GPIO91",
+ MTK_EINT_FUNCTION(0, 91),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "BPI_BUS3")
+ ),
+ MTK_PIN(
+ 92, "GPIO92",
+ MTK_EINT_FUNCTION(0, 92),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "BPI_BUS2"),
+ MTK_FUNCTION(7, "DBG_MON_B16")
+ ),
+ MTK_PIN(
+ 93, "GPIO93",
+ MTK_EINT_FUNCTION(0, 93),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "BPI_BUS1")
+ ),
+ MTK_PIN(
+ 94, "GPIO94",
+ MTK_EINT_FUNCTION(0, 94),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "BPI_BUS0"),
+ MTK_FUNCTION(7, "DBG_MON_B15")
+ ),
+ MTK_PIN(
+ 95, "GPIO95",
+ MTK_EINT_FUNCTION(0, 95),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "MIPI0_SDATA")
+ ),
+ MTK_PIN(
+ 96, "GPIO96",
+ MTK_EINT_FUNCTION(0, 96),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "MIPI0_SCLK")
+ ),
+ MTK_PIN(
+ 97, "GPIO97",
+ MTK_EINT_FUNCTION(0, 97),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "MIPI1_SDATA")
+ ),
+ MTK_PIN(
+ 98, "GPIO98",
+ MTK_EINT_FUNCTION(0, 98),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "MIPI1_SCLK")
+ ),
+ MTK_PIN(
+ 99, "GPIO99",
+ MTK_EINT_FUNCTION(0, 99),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "MIPI2_SCLK"),
+ MTK_FUNCTION(7, "DBG_MON_B14")
+ ),
+ MTK_PIN(
+ 100, "GPIO100",
+ MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "MIPI2_SDATA"),
+ MTK_FUNCTION(7, "DBG_MON_B13")
+ ),
+ MTK_PIN(
+ 101, "GPIO101",
+ MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "MIPI3_SCLK"),
+ MTK_FUNCTION(7, "DBG_MON_B12")
+ ),
+ MTK_PIN(
+ 102, "GPIO102",
+ MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "MIPI3_SDATA"),
+ MTK_FUNCTION(7, "DBG_MON_B11")
+ ),
+ MTK_PIN(
+ 103, "GPIO103",
+ MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "MIPI4_SCLK"),
+ MTK_FUNCTION(2, "CONN_MIPI4_SCLK")
+ ),
+ MTK_PIN(
+ 104, "GPIO104",
+ MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "MIPI4_SDATA"),
+ MTK_FUNCTION(2, "CONN_MIPI4_SDATA")
+ ),
+ MTK_PIN(
+ 105, "GPIO105",
+ MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "BPI_BUS22_OLAT3"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS22_OLAT3")
+ ),
+ MTK_PIN(
+ 106, "GPIO106",
+ MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "BPI_BUS21_OLAT2"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS21_OLAT2")
+ ),
+ MTK_PIN(
+ 107, "GPIO107",
+ MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "BPI_BUS24_ANT1"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS24_ANT1")
+ ),
+ MTK_PIN(
+ 108, "GPIO108",
+ MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "BPI_BUS25_ANT2"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS25_ANT2")
+ ),
+ MTK_PIN(
+ 109, "GPIO109",
+ MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "BPI_BUS23_ANT0"),
+ MTK_FUNCTION(2, "CONN_BPI_BUS23_ANT0")
+ ),
+ MTK_PIN(
+ 110, "GPIO110",
+ MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "SCL4")
+ ),
+ MTK_PIN(
+ 111, "GPIO111",
+ MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "SDA4")
+ ),
+ MTK_PIN(
+ 112, "GPIO112",
+ MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "SCL2")
+ ),
+ MTK_PIN(
+ 113, "GPIO113",
+ MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "SDA2")
+ ),
+ MTK_PIN(
+ 114, "GPIO114",
+ MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "CLKM0"),
+ MTK_FUNCTION(2, "SPI3_MI"),
+ MTK_FUNCTION(7, "DBG_MON_B5")
+ ),
+ MTK_PIN(
+ 115, "GPIO115",
+ MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "CLKM1"),
+ MTK_FUNCTION(2, "SPI3_CSB"),
+ MTK_FUNCTION(7, "DBG_MON_B4")
+ ),
+ MTK_PIN(
+ 116, "GPIO116",
+ MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "CMMCLK0"),
+ MTK_FUNCTION(7, "DBG_MON_B3")
+ ),
+ MTK_PIN(
+ 117, "GPIO117",
+ MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "CMMCLK1"),
+ MTK_FUNCTION(2, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(7, "DBG_MON_B2")
+ ),
+ MTK_PIN(
+ 118, "GPIO118",
+ MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "CLKM2"),
+ MTK_FUNCTION(2, "SPI3_MO"),
+ MTK_FUNCTION(7, "DBG_MON_B1")
+ ),
+ MTK_PIN(
+ 119, "GPIO119",
+ MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "CLKM3"),
+ MTK_FUNCTION(2, "SPI3_CLK"),
+ MTK_FUNCTION(7, "DBG_MON_B0")
+ ),
+ MTK_PIN(
+ 120, "GPIO120",
+ MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "CMMCLK2"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(6, "ANT_SEL12"),
+ MTK_FUNCTION(7, "TP_UCTS2_AO")
+ ),
+ MTK_PIN(
+ 121, "GPIO121",
+ MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "CMMCLK3"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(3, "DVFSRC_EXT_REQ"),
+ MTK_FUNCTION(6, "ANT_SEL11"),
+ MTK_FUNCTION(7, "TP_URTS2_AO")
+ ),
+ MTK_PIN(
+ 122, "GPIO122",
+ MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "CMVREF1"),
+ MTK_FUNCTION(2, "PCM0_SYNC"),
+ MTK_FUNCTION(3, "SRCLKENAI1"),
+ MTK_FUNCTION(4, "AGPS_SYNC"),
+ MTK_FUNCTION(5, "PWM_1"),
+ MTK_FUNCTION(6, "ANT_SEL9"),
+ MTK_FUNCTION(7, "TP_UCTS1_AO")
+ ),
+ MTK_PIN(
+ 123, "GPIO123",
+ MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(2, "PCM0_DI"),
+ MTK_FUNCTION(3, "ADSP_JTAG_TRSTN"),
+ MTK_FUNCTION(4, "VPU_UDI_NTRST"),
+ MTK_FUNCTION(5, "SPM_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TRSTN")
+ ),
+ MTK_PIN(
+ 124, "GPIO124",
+ MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "CMVREF2"),
+ MTK_FUNCTION(2, "PCM0_CLK"),
+ MTK_FUNCTION(3, "MD_INT0"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "PWM_2"),
+ MTK_FUNCTION(6, "ANT_SEL10"),
+ MTK_FUNCTION(7, "TP_URTS1_AO")
+ ),
+ MTK_PIN(
+ 125, "GPIO125",
+ MTK_EINT_FUNCTION(0, 125),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "CMVREF3"),
+ MTK_FUNCTION(2, "PCM0_DO"),
+ MTK_FUNCTION(3, "ADSP_JTAG_TMS"),
+ MTK_FUNCTION(4, "VPU_UDI_TMS"),
+ MTK_FUNCTION(5, "SPM_JTAG_TMS"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TMS")
+ ),
+ MTK_PIN(
+ 126, "GPIO126",
+ MTK_EINT_FUNCTION(0, 126),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "CMVREF4"),
+ MTK_FUNCTION(2, "CMFLASH0"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC")
+ ),
+ MTK_PIN(
+ 127, "GPIO127",
+ MTK_EINT_FUNCTION(0, 127),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "CMVREF0"),
+ MTK_FUNCTION(2, "CMFLASH1"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC")
+ ),
+ MTK_PIN(
+ 128, "GPIO128",
+ MTK_EINT_FUNCTION(0, 128),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "MD1_SIM1_SIO"),
+ MTK_FUNCTION(2, "MD1_SIM2_SIO"),
+ MTK_FUNCTION(3, "CCU_JTAG_TRST"),
+ MTK_FUNCTION(4, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "LVTS_FOUT"),
+ MTK_FUNCTION(7, "DBG_MON_A3")
+ ),
+ MTK_PIN(
+ 129, "GPIO129",
+ MTK_EINT_FUNCTION(0, 129),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "MD1_SIM1_SRST"),
+ MTK_FUNCTION(2, "MD1_SIM2_SRST"),
+ MTK_FUNCTION(3, "CCU_JTAG_TCK"),
+ MTK_FUNCTION(4, "CONN_DSP_JCK"),
+ MTK_FUNCTION(5, "SCP_JTAG_TCK"),
+ MTK_FUNCTION(6, "LVTS_SDO"),
+ MTK_FUNCTION(7, "DBG_MON_A4")
+ ),
+ MTK_PIN(
+ 130, "GPIO130",
+ MTK_EINT_FUNCTION(0, 130),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "MD1_SIM1_SCLK"),
+ MTK_FUNCTION(2, "MD1_SIM2_SCLK"),
+ MTK_FUNCTION(6, "LVTS_26M"),
+ MTK_FUNCTION(7, "DBG_MON_A5")
+ ),
+ MTK_PIN(
+ 131, "GPIO131",
+ MTK_EINT_FUNCTION(0, 131),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "MD1_SIM2_SCLK"),
+ MTK_FUNCTION(2, "MD1_SIM1_SCLK"),
+ MTK_FUNCTION(3, "CCU_JTAG_TDI"),
+ MTK_FUNCTION(4, "CONN_DSP_JDI"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDI"),
+ MTK_FUNCTION(6, "LVTS_SCK"),
+ MTK_FUNCTION(7, "DBG_MON_A0")
+ ),
+ MTK_PIN(
+ 132, "GPIO132",
+ MTK_EINT_FUNCTION(0, 132),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "MD1_SIM2_SRST"),
+ MTK_FUNCTION(2, "MD1_SIM1_SRST"),
+ MTK_FUNCTION(3, "CCU_JTAG_TMS"),
+ MTK_FUNCTION(4, "CONN_DSP_JMS"),
+ MTK_FUNCTION(5, "SCP_JTAG_TMS"),
+ MTK_FUNCTION(6, "LVTS_SDI"),
+ MTK_FUNCTION(7, "DBG_MON_A1")
+ ),
+ MTK_PIN(
+ 133, "GPIO133",
+ MTK_EINT_FUNCTION(0, 133),
+ DRV_GRP0,
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "MD1_SIM2_SIO"),
+ MTK_FUNCTION(2, "MD1_SIM1_SIO"),
+ MTK_FUNCTION(3, "CCU_JTAG_TDO"),
+ MTK_FUNCTION(4, "CONN_DSP_JDO"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDO"),
+ MTK_FUNCTION(6, "LVTS_SCF"),
+ MTK_FUNCTION(7, "DBG_MON_A2")
+ ),
+ MTK_PIN(
+ 134, "GPIO134",
+ MTK_EINT_FUNCTION(0, 134),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "PCM1_CLK"),
+ MTK_FUNCTION(3, "SPI5_B_MI"),
+ MTK_FUNCTION(4, "UDI_TCK"),
+ MTK_FUNCTION(5, "CONN_DSP_JCK"),
+ MTK_FUNCTION(6, "IPU_JTAG_TCK"),
+ MTK_FUNCTION(7, "JTCK_SEL3")
+ ),
+ MTK_PIN(
+ 135, "GPIO135",
+ MTK_EINT_FUNCTION(0, 135),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "PCM1_SYNC"),
+ MTK_FUNCTION(3, "SPI5_B_CSB"),
+ MTK_FUNCTION(4, "UDI_TMS"),
+ MTK_FUNCTION(5, "CONN_DSP_JMS"),
+ MTK_FUNCTION(6, "IPU_JTAG_TMS"),
+ MTK_FUNCTION(7, "JTMS_SEL3")
+ ),
+ MTK_PIN(
+ 136, "GPIO136",
+ MTK_EINT_FUNCTION(0, 136),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(2, "PCM1_DI"),
+ MTK_FUNCTION(3, "SPI5_B_MO"),
+ MTK_FUNCTION(4, "CONN_TCXOENA_REQ"),
+ MTK_FUNCTION(5, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC")
+ ),
+ MTK_PIN(
+ 137, "GPIO137",
+ MTK_EINT_FUNCTION(0, 137),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "PCM1_DO0"),
+ MTK_FUNCTION(3, "SPI5_B_CLK"),
+ MTK_FUNCTION(4, "UDI_TDI"),
+ MTK_FUNCTION(5, "CONN_DSP_JDI"),
+ MTK_FUNCTION(6, "IPU_JTAG_TDI"),
+ MTK_FUNCTION(7, "JTDI_SEL3")
+ ),
+ MTK_PIN(
+ 138, "GPIO138",
+ MTK_EINT_FUNCTION(0, 138),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "PCM1_DO2"),
+ MTK_FUNCTION(3, "ANT_SEL11"),
+ MTK_FUNCTION(4, "UDI_NTRST"),
+ MTK_FUNCTION(5, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(6, "IPU_JTAG_TRST"),
+ MTK_FUNCTION(7, "JTRSTN_SEL3")
+ ),
+ MTK_PIN(
+ 139, "GPIO139",
+ MTK_EINT_FUNCTION(0, 139),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "PCM1_DO1"),
+ MTK_FUNCTION(3, "ANT_SEL12"),
+ MTK_FUNCTION(4, "UDI_TDO"),
+ MTK_FUNCTION(5, "CONN_DSP_JDO"),
+ MTK_FUNCTION(6, "IPU_JTAG_TDO"),
+ MTK_FUNCTION(7, "JTDO_SEL3")
+ ),
+ MTK_PIN(
+ 140, "GPIO140",
+ MTK_EINT_FUNCTION(0, 140),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"),
+ MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"),
+ MTK_FUNCTION(3, "ADSP_URXD0"),
+ MTK_FUNCTION(4, "SCL_6306"),
+ MTK_FUNCTION(5, "PTA_RXD"),
+ MTK_FUNCTION(6, "SSPM_URXD_AO")
+ ),
+ MTK_PIN(
+ 141, "GPIO141",
+ MTK_EINT_FUNCTION(0, 141),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"),
+ MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"),
+ MTK_FUNCTION(3, "ADSP_UTXD0"),
+ MTK_FUNCTION(4, "SDA_6306"),
+ MTK_FUNCTION(5, "PTA_TXD"),
+ MTK_FUNCTION(6, "SSPM_UTXD_AO")
+ ),
+ MTK_PIN(
+ 142, "GPIO142",
+ MTK_EINT_FUNCTION(0, 142),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "SCP_VREQ_VAO"),
+ MTK_FUNCTION(2, "DVFSRC_EXT_REQ")
+ ),
+ MTK_PIN(
+ 143, "GPIO143",
+ MTK_EINT_FUNCTION(0, 143),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI2"),
+ MTK_FUNCTION(7, "DBG_MON_A9")
+ ),
+ MTK_PIN(
+ 144, "GPIO144",
+ MTK_EINT_FUNCTION(0, 144),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "AUD_NLE_MOSI1"),
+ MTK_FUNCTION(2, "AUD_CLK_MISO"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(5, "UDI_TCK"),
+ MTK_FUNCTION(6, "UFS_UNIPRO_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A10")
+ ),
+ MTK_PIN(
+ 145, "GPIO145",
+ MTK_EINT_FUNCTION(0, 145),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "AUD_NLE_MOSI0"),
+ MTK_FUNCTION(2, "AUD_SYNC_MISO"),
+ MTK_FUNCTION(3, "I2S2_BCK"),
+ MTK_FUNCTION(5, "UDI_TMS"),
+ MTK_FUNCTION(7, "DBG_MON_A11")
+ ),
+ MTK_PIN(
+ 146, "GPIO146",
+ MTK_EINT_FUNCTION(0, 146),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO2"),
+ MTK_FUNCTION(3, "I2S2_DI2"),
+ MTK_FUNCTION(5, "UDI_TDO"),
+ MTK_FUNCTION(7, "DBG_MON_A14")
+ ),
+ MTK_PIN(
+ 147, "GPIO147",
+ MTK_EINT_FUNCTION(0, 147),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "ANT_SEL0"),
+ MTK_FUNCTION(2, "PWM_3")
+ ),
+ MTK_PIN(
+ 148, "GPIO148",
+ MTK_EINT_FUNCTION(0, 148),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "ANT_SEL1"),
+ MTK_FUNCTION(2, "SPI0_B_MI"),
+ MTK_FUNCTION(3, "SSPM_URXD_AO"),
+ MTK_FUNCTION(5, "TP_UCTS2_AO"),
+ MTK_FUNCTION(6, "CLKM0")
+ ),
+ MTK_PIN(
+ 149, "GPIO149",
+ MTK_EINT_FUNCTION(0, 149),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "ANT_SEL2"),
+ MTK_FUNCTION(2, "SPI0_B_CSB"),
+ MTK_FUNCTION(3, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(5, "TP_URTS2_AO"),
+ MTK_FUNCTION(6, "CONN_TCXOENA_REQ")
+ ),
+ MTK_PIN(
+ 150, "GPIO150",
+ MTK_EINT_FUNCTION(0, 150),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, "ANT_SEL3"),
+ MTK_FUNCTION(2, "SPI0_B_MO"),
+ MTK_FUNCTION(3, "UCTS1"),
+ MTK_FUNCTION(5, "TP_UCTS1_AO"),
+ MTK_FUNCTION(6, "IDDIG"),
+ MTK_FUNCTION(7, "SCL9")
+ ),
+ MTK_PIN(
+ 151, "GPIO151",
+ MTK_EINT_FUNCTION(0, 151),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "ANT_SEL4"),
+ MTK_FUNCTION(2, "SPI0_B_CLK"),
+ MTK_FUNCTION(3, "URTS1"),
+ MTK_FUNCTION(5, "TP_URTS1_AO"),
+ MTK_FUNCTION(6, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "SDA9")
+ ),
+ MTK_PIN(
+ 152, "GPIO152",
+ MTK_EINT_FUNCTION(0, 152),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, "ANT_SEL5"),
+ MTK_FUNCTION(2, "SPI1_B_MI"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(5, "TP_URXD1_AO"),
+ MTK_FUNCTION(6, "SCP_SPI1_B_MI"),
+ MTK_FUNCTION(7, "SCL8")
+ ),
+ MTK_PIN(
+ 153, "GPIO153",
+ MTK_EINT_FUNCTION(0, 153),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "ANT_SEL6"),
+ MTK_FUNCTION(2, "SPI1_B_CSB"),
+ MTK_FUNCTION(3, "SRCLKENAI0"),
+ MTK_FUNCTION(4, "PWM_0"),
+ MTK_FUNCTION(5, "TP_UTXD1_AO"),
+ MTK_FUNCTION(6, "SCP_SPI1_B_CS"),
+ MTK_FUNCTION(7, "SDA8")
+ ),
+ MTK_PIN(
+ 154, "GPIO154",
+ MTK_EINT_FUNCTION(0, 154),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "ANT_SEL7"),
+ MTK_FUNCTION(2, "SPI1_B_MO"),
+ MTK_FUNCTION(3, "SRCLKENAI1"),
+ MTK_FUNCTION(5, "TP_URXD2_AO"),
+ MTK_FUNCTION(6, "SCP_SPI1_B_MO")
+ ),
+ MTK_PIN(
+ 155, "GPIO155",
+ MTK_EINT_FUNCTION(0, 155),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "ANT_SEL8"),
+ MTK_FUNCTION(2, "SPI1_B_CLK"),
+ MTK_FUNCTION(3, "MD_INT0"),
+ MTK_FUNCTION(5, "TP_UTXD2_AO"),
+ MTK_FUNCTION(6, "SCP_SPI1_B_CK"),
+ MTK_FUNCTION(7, "DBG_MON_A15")
+ ),
+ MTK_PIN(
+ 156, "GPIO156",
+ MTK_EINT_FUNCTION(0, 156),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "CONN_TOP_CLK"),
+ MTK_FUNCTION(2, "AUXIF_CLK0"),
+ MTK_FUNCTION(7, "DBG_MON_A16")
+ ),
+ MTK_PIN(
+ 157, "GPIO157",
+ MTK_EINT_FUNCTION(0, 157),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "CONN_TOP_DATA"),
+ MTK_FUNCTION(2, "AUXIF_ST0"),
+ MTK_FUNCTION(7, "DBG_MON_A17")
+ ),
+ MTK_PIN(
+ 158, "GPIO158",
+ MTK_EINT_FUNCTION(0, 158),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "CONN_HRST_B"),
+ MTK_FUNCTION(7, "DBG_MON_A18")
+ ),
+ MTK_PIN(
+ 159, "GPIO159",
+ MTK_EINT_FUNCTION(0, 159),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "CONN_WB_PTA"),
+ MTK_FUNCTION(7, "DBG_MON_A19")
+ ),
+ MTK_PIN(
+ 160, "GPIO160",
+ MTK_EINT_FUNCTION(0, 160),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "CONN_BT_CLK"),
+ MTK_FUNCTION(2, "AUXIF_CLK1"),
+ MTK_FUNCTION(7, "DBG_MON_A20")
+ ),
+ MTK_PIN(
+ 161, "GPIO161",
+ MTK_EINT_FUNCTION(0, 161),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "CONN_BT_DATA"),
+ MTK_FUNCTION(2, "AUXIF_ST1"),
+ MTK_FUNCTION(7, "DBG_MON_A21")
+ ),
+ MTK_PIN(
+ 162, "GPIO162",
+ MTK_EINT_FUNCTION(0, 162),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL0"),
+ MTK_FUNCTION(7, "DBG_MON_A22")
+ ),
+ MTK_PIN(
+ 163, "GPIO163",
+ MTK_EINT_FUNCTION(0, 163),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL1"),
+ MTK_FUNCTION(2, "UFS_MPHY_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_A23")
+ ),
+ MTK_PIN(
+ 164, "GPIO164",
+ MTK_EINT_FUNCTION(0, 164),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL2"),
+ MTK_FUNCTION(2, "UFS_MPHY_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A24")
+ ),
+ MTK_PIN(
+ 165, "GPIO165",
+ MTK_EINT_FUNCTION(0, 165),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL3"),
+ MTK_FUNCTION(2, "UFS_UNIPRO_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A25")
+ ),
+ MTK_PIN(
+ 166, "GPIO166",
+ MTK_EINT_FUNCTION(0, 166),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL4"),
+ MTK_FUNCTION(2, "UFS_UNIPRO_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_A26")
+ ),
+ MTK_PIN(
+ 167, "GPIO167",
+ MTK_EINT_FUNCTION(0, 167),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "MSDC0_CMD")
+ ),
+ MTK_PIN(
+ 168, "GPIO168",
+ MTK_EINT_FUNCTION(0, 168),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "MSDC0_DAT0")
+ ),
+ MTK_PIN(
+ 169, "GPIO169",
+ MTK_EINT_FUNCTION(0, 169),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "MSDC0_DAT2")
+ ),
+ MTK_PIN(
+ 170, "GPIO170",
+ MTK_EINT_FUNCTION(0, 170),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "MSDC0_DAT4")
+ ),
+ MTK_PIN(
+ 171, "GPIO171",
+ MTK_EINT_FUNCTION(0, 171),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "MSDC0_DAT6")
+ ),
+ MTK_PIN(
+ 172, "GPIO172",
+ MTK_EINT_FUNCTION(0, 172),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "MSDC0_DAT1")
+ ),
+ MTK_PIN(
+ 173, "GPIO173",
+ MTK_EINT_FUNCTION(0, 173),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "MSDC0_DAT5")
+ ),
+ MTK_PIN(
+ 174, "GPIO174",
+ MTK_EINT_FUNCTION(0, 174),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "MSDC0_DAT7")
+ ),
+ MTK_PIN(
+ 175, "GPIO175",
+ MTK_EINT_FUNCTION(0, 175),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "MSDC0_DSL"),
+ MTK_FUNCTION(2, "ANT_SEL9")
+ ),
+ MTK_PIN(
+ 176, "GPIO176",
+ MTK_EINT_FUNCTION(0, 176),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION(2, "ANT_SEL10")
+ ),
+ MTK_PIN(
+ 177, "GPIO177",
+ MTK_EINT_FUNCTION(0, 177),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "MSDC0_DAT3")
+ ),
+ MTK_PIN(
+ 178, "GPIO178",
+ MTK_EINT_FUNCTION(0, 178),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "MSDC0_RSTB")
+ ),
+ MTK_PIN(
+ 179, "GPIO179",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "RFIC0_BSI_EN")
+ ),
+ MTK_PIN(
+ 180, "GPIO180",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "RFIC0_BSI_CK")
+ ),
+ MTK_PIN(
+ 181, "GPIO181",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "SRCLKENA0")
+ ),
+ MTK_PIN(
+ 182, "GPIO182",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "SRCLKENA1")
+ ),
+ MTK_PIN(
+ 183, "GPIO183",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ 184, "GPIO184",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MO")
+ ),
+ MTK_PIN(
+ 185, "GPIO185",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
+ ),
+ MTK_PIN(
+ 186, "GPIO186",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MI")
+ ),
+ MTK_PIN(
+ 187, "GPIO187",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CK")
+ ),
+ MTK_PIN(
+ 188, "GPIO188",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ 189, "GPIO189",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(1, "AUD_CLK_MOSI"),
+ MTK_FUNCTION(3, "I2S1_MCK"),
+ MTK_FUNCTION(6, "UFS_UNIPRO_SCL")
+ ),
+ MTK_PIN(
+ 190, "GPIO190",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "AUD_SYNC_MOSI"),
+ MTK_FUNCTION(3, "I2S1_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_A6")
+ ),
+ MTK_PIN(
+ 191, "GPIO191",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI0"),
+ MTK_FUNCTION(3, "I2S1_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_A7")
+ ),
+ MTK_PIN(
+ 192, "GPIO192",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI1"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(6, "UFS_MPHY_SDA"),
+ MTK_FUNCTION(7, "DBG_MON_A8")
+ ),
+ MTK_PIN(
+ 193, "GPIO193",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO0"),
+ MTK_FUNCTION(2, "VOW_DAT_MISO"),
+ MTK_FUNCTION(3, "I2S2_LRCK"),
+ MTK_FUNCTION(5, "UDI_TDI"),
+ MTK_FUNCTION(7, "DBG_MON_A12")
+ ),
+ MTK_PIN(
+ 194, "GPIO194",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO1"),
+ MTK_FUNCTION(2, "VOW_CLK_MISO"),
+ MTK_FUNCTION(3, "I2S2_DI"),
+ MTK_FUNCTION(5, "UDI_NTRST"),
+ MTK_FUNCTION(6, "UFS_MPHY_SCL"),
+ MTK_FUNCTION(7, "DBG_MON_A13")
+ ),
+ MTK_PIN(
+ 195, "GPIO195",
+ MTK_EINT_FUNCTION(0, 179),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(3, "ADSP_JTAG_TCK"),
+ MTK_FUNCTION(4, "VPU_UDI_TCK"),
+ MTK_FUNCTION(5, "SPM_JTAG_TCK"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TCK")
+ ),
+ MTK_PIN(
+ 196, "GPIO196",
+ MTK_EINT_FUNCTION(0, 180),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "CMMCLK4"),
+ MTK_FUNCTION(3, "ADSP_JTAG_TDI"),
+ MTK_FUNCTION(4, "VPU_UDI_TDI"),
+ MTK_FUNCTION(5, "SPM_JTAG_TDI"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TDI")
+ ),
+ MTK_PIN(
+ 197, "GPIO197",
+ MTK_EINT_FUNCTION(0, 181),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(3, "ADSP_JTAG_TDO"),
+ MTK_FUNCTION(4, "VPU_UDI_TDO"),
+ MTK_FUNCTION(5, "SPM_JTAG_TDO"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TDO")
+ ),
+ MTK_PIN(
+ 198, "GPIO198",
+ MTK_EINT_FUNCTION(0, 182),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO198"),
+ MTK_FUNCTION(1, "SCL7")
+ ),
+ MTK_PIN(
+ 199, "GPIO199",
+ MTK_EINT_FUNCTION(0, 183),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "SDA7")
+ ),
+ MTK_PIN(
+ 200, "GPIO200",
+ MTK_EINT_FUNCTION(0, 184),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "ADSP_URXD0"),
+ MTK_FUNCTION(3, "TP_URXD1_AO"),
+ MTK_FUNCTION(4, "SSPM_URXD_AO"),
+ MTK_FUNCTION(5, "TP_URXD2_AO"),
+ MTK_FUNCTION(6, "MBISTREADEN_TRIGGER")
+ ),
+ MTK_PIN(
+ 201, "GPIO201",
+ MTK_EINT_FUNCTION(0, 185),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "ADSP_UTXD0"),
+ MTK_FUNCTION(3, "TP_UTXD1_AO"),
+ MTK_FUNCTION(4, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(5, "TP_UTXD2_AO"),
+ MTK_FUNCTION(6, "MBISTWRITEEN_TRIGGER")
+ ),
+ MTK_PIN(
+ 202, "GPIO202",
+ MTK_EINT_FUNCTION(0, 186),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO202"),
+ MTK_FUNCTION(1, "PWM_3"),
+ MTK_FUNCTION(2, "CLKM3")
+ ),
+ MTK_PIN(
+ 203, "GPIO203",
+ MTK_EINT_FUNCTION(0, 187),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 204, "GPIO204",
+ MTK_EINT_FUNCTION(0, 188),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 205, "GPIO205",
+ MTK_EINT_FUNCTION(0, 189),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 206, "GPIO206",
+ MTK_EINT_FUNCTION(0, 190),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 207, "GPIO207",
+ MTK_EINT_FUNCTION(0, 191),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 208, "GPIO208",
+ MTK_EINT_FUNCTION(0, 193),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+ MTK_PIN(
+ 209, "GPIO209",
+ MTK_EINT_FUNCTION(0, 194),
+ DRV_GRP4,
+ MTK_FUNCTION(0, NULL)
+ ),
+};
+
+#endif /* __PINCTRL-MTK-MT6779_H */
if (gpio >= hw->soc->npins)
return -EINVAL;
+ /*
+ * "Virtual" GPIOs are always and only used for interrupts
+ * Since they are only used for interrupts, they are always inputs
+ */
+ if (mtk_is_virt_gpio(hw, gpio))
+ return 1;
+
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
"i2c3_sck_x", "i2c3_sda_x", "i2c3_sck_f", "i2c3_sda_f",
};
-static const char * const i2c_slave_groups[] = {
- "i2c_slave_sda_a", "i2c_slave_sck_a",
- "i2c_slave_sda_f", "i2c_slave_sck_f",
-};
-
static const char * const spi_a_groups[] = {
"spi_a_mosi_x2", "spi_a_ss0_x3", "spi_a_sclk_x4", "spi_a_miso_x5",
"spi_a_mosi_x7", "spi_a_miso_x8", "spi_a_ss0_x9", "spi_a_sclk_x10",
#include "../pinctrl-utils.h"
#include "pinctrl-meson.h"
+static const unsigned int meson_bit_strides[] = {
+ 1, 1, 1, 1, 1, 2, 1
+};
+
/**
* meson_get_bank() - find the bank containing a given pin
*
{
struct meson_reg_desc *desc = &bank->regs[reg_type];
- *reg = desc->reg * 4;
- *bit = desc->bit + pin - bank->first;
+ *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type];
+ *reg = (desc->reg + (*bit / 32)) * 4;
+ *bit &= 0x1f;
}
static int meson_get_groups_count(struct pinctrl_dev *pcdev)
return ret;
meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit);
- bit = bit << 1;
if (drive_strength_ua <= 500) {
ds_val = MESON_PINCONF_DRV_500UA;
return ret;
meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit);
- bit = bit << 1;
ret = regmap_read(pc->reg_ds, reg, &val);
if (ret)
* The pins of a pinmux groups are composed of one or two groups of contiguous
* pins.
* @name: Name of the pin group, used to lookup the group.
- * @start_pins: Index of the first pin of the main range of pins belonging to
+ * @start_pin: Index of the first pin of the main range of pins belonging to
* the group
* @npins: Number of pins included in the first range
* @reg_mask: Bit mask matching the group in the selection register
- * @extra_pins: Index of the first pin of the optional second range of pins
+ * @val: Value to write to the registers for a given function
+ * @extra_pin: Index of the first pin of the optional second range of pins
* belonging to the group
- * @npins: Number of pins included in the second optional range
+ * @extra_npins:Number of pins included in the second optional range
* @funcs: A list of pinmux functions that can be selected for this group.
* @pins: List of the pins included in the group
*/
* pinconf_generic_parse_dt_config()
* parse the config properties into generic pinconfig values.
* @np: node containing the pinconfig properties
+ * @pctldev: pincontrol device
* @configs: array with nconfigs entries containing the generic pinconf values
* must be freed when no longer necessary.
- * @nconfigs: umber of configurations
+ * @nconfigs: number of configurations
*/
int pinconf_generic_parse_dt_config(struct device_node *np,
struct pinctrl_dev *pctldev,
{
int ret = 0;
u32 pin_reg, pin_reg_irq_en, mask;
- unsigned long flags, irq_flags;
+ unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
- /* Ignore the settings coming from the client and
- * read the values from the ACPI tables
- * while setting the trigger type
- */
-
- irq_flags = irq_get_trigger_type(d->irq);
- if (irq_flags != IRQ_TYPE_NONE)
- type = irq_flags;
-
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
int irq_base;
struct resource *res;
struct amd_gpio *gpio_dev;
+ struct gpio_irq_chip *girq;
gpio_dev = devm_kzalloc(&pdev->dev,
sizeof(struct amd_gpio), GFP_KERNEL);
return PTR_ERR(gpio_dev->pctrl);
}
+ girq = &gpio_dev->gc.irq;
+ girq->chip = &amd_gpio_irqchip;
+ /* This will let us handle the parent IRQ in the driver */
+ girq->parent_handler = NULL;
+ girq->num_parents = 0;
+ girq->parents = NULL;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_simple_irq;
+
ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
if (ret)
return ret;
goto out2;
}
- ret = gpiochip_irqchip_add(&gpio_dev->gc,
- &amd_gpio_irqchip,
- 0,
- handle_simple_irq,
- IRQ_TYPE_NONE);
- if (ret) {
- dev_err(&pdev->dev, "could not add irqchip\n");
- ret = -ENODEV;
- goto out2;
- }
-
ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
if (ret)
return 0;
}
+#ifdef CONFIG_ACPI
static const struct acpi_device_id amd_gpio_acpi_match[] = {
{ "AMD0030", 0 },
{ "AMDI0030", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
+#endif
static struct platform_driver amd_gpio_driver = {
.driver = {
* @irq_domain: irq domain for the gpio controller.
* @irqs: table containing the hw irq number of the bank. The index of the
* table is the bank id.
+ * @pm_wakeup_sources: bitmap of wakeup sources (lines)
+ * @pm_suspend_backup: backup/restore register values on suspend/resume
* @dev: device entry for the Atmel PIO controller.
* @node: node of the Atmel PIO controller.
*/
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
-/**
+/*
* These defines will translated the dt binding settings to our internal
* settings. They are not necessarily the same value as the register setting.
* The actual drive strength current of low, medium and high must be looked up
* @set_pulldown: enable/disable pulldown
* @get_schmitt_trig: get schmitt trigger status
* @disable_schmitt_trig: disable schmitt trigger
+ * @get_drivestrength: get driver strength
+ * @set_drivestrength: set driver strength
+ * @get_slewrate: get slew rate
+ * @set_slewrate: set slew rate
* @irq_type: return irq type
*/
struct at91_pinctrl_mux_ops {
/**
* struct bm1880_pinctrl - driver data
* @base: Pinctrl base address
- * @pctrl: Pinctrl device
+ * @pctrldev: Pinctrl device
* @groups: Pingroups
* @ngroups: Number of @groups
* @funcs: Pinmux functions
* @nfuncs: Number of @funcs
- * @pconf: Pinconf data
+ * @pinconf: Pinconf data
*/
struct bm1880_pinctrl {
void __iomem *base;
static int jz4740_nand_cs2_pins[] = { 0x3a, };
static int jz4740_nand_cs3_pins[] = { 0x3b, };
static int jz4740_nand_cs4_pins[] = { 0x3c, };
+static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
static int jz4740_pwm_pwm0_pins[] = { 0x77, };
static int jz4740_pwm_pwm1_pins[] = { 0x78, };
static int jz4740_pwm_pwm2_pins[] = { 0x79, };
static int jz4740_nand_cs2_funcs[] = { 0, };
static int jz4740_nand_cs3_funcs[] = { 0, };
static int jz4740_nand_cs4_funcs[] = { 0, };
+static int jz4740_nand_fre_fwe_funcs[] = { 0, 0, };
static int jz4740_pwm_pwm0_funcs[] = { 0, };
static int jz4740_pwm_pwm1_funcs[] = { 0, };
static int jz4740_pwm_pwm2_funcs[] = { 0, };
INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
+ INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe),
INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
};
static const char *jz4740_nand_groups[] = {
- "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
+ "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
};
static const char *jz4740_pwm0_groups[] = { "pwm0", };
static const char *jz4740_pwm1_groups[] = { "pwm1", };
*/
high = ingenic_gpio_get_value(jzgc, irq);
if (high)
- irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING);
+ irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
else
- irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
+ irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
}
if (jzgc->jzpc->info->version >= ID_JZ4760)
*/
bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
- type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
+ type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
}
irq_set_type(jzgc, irqd->hwirq, type);
unsigned int pin = gc->base + offset;
if (jzpc->info->version >= ID_JZ4760) {
- if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1))
+ if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_INT) ||
+ ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
{ .compatible = "ingenic,jz4740-gpio", },
+ { .compatible = "ingenic,jz4725b-gpio", },
{ .compatible = "ingenic,jz4760-gpio", },
{ .compatible = "ingenic,jz4770-gpio", },
{ .compatible = "ingenic,jz4780-gpio", },
*arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
switch (*arg) {
case 3: *arg += 5;
- /* fall through */
+ fallthrough;
case 2: *arg += 5;
- /* fall through */
+ fallthrough;
case 1: *arg += 3;
- /* fall through */
+ fallthrough;
case 0: *arg += 4;
}
break;
switch (param_val) {
case 20: param_val -= 5;
- /* fall through */
+ fallthrough;
case 14: param_val -= 5;
- /* fall through */
+ fallthrough;
case 8: param_val -= 3;
- /* fall through */
+ fallthrough;
case 4: param_val -= 4;
break;
default:
return 0;
}
-static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp)
-{
- struct gpio_chip *chip = &mcp->chip;
- int err;
-
- err = gpiochip_irqchip_add_nested(chip,
- &mcp->irq_chip,
- 0,
- handle_simple_irq,
- IRQ_TYPE_NONE);
- if (err) {
- dev_err(chip->parent,
- "could not connect irqchip to gpiochip: %d\n", err);
- return err;
- }
-
- gpiochip_set_nested_irqchip(chip,
- &mcp->irq_chip,
- mcp->irq);
-
- return 0;
-}
-
/*----------------------------------------------------------------------*/
int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
if (ret < 0)
goto fail;
- ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
- if (ret < 0)
- goto fail;
-
mcp->irq_controller =
device_property_read_bool(dev, "interrupt-controller");
if (mcp->irq && mcp->irq_controller) {
}
if (mcp->irq && mcp->irq_controller) {
- ret = mcp23s08_irqchip_setup(mcp);
- if (ret)
- goto fail;
+ struct gpio_irq_chip *girq = &mcp->chip.irq;
+
+ girq->chip = &mcp->irq_chip;
+ /* This will let us handle the parent IRQ in the driver */
+ girq->parent_handler = NULL;
+ girq->num_parents = 0;
+ girq->parents = NULL;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_simple_irq;
+ girq->threaded = true;
}
+ ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
+ if (ret < 0)
+ goto fail;
+
mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
mcp->pinctrl_desc.npins = mcp->chip.ngpio;
#include "pinconf.h"
#include "pinmux.h"
+#define ocelot_clrsetbits(addr, clear, set) \
+ writel((readl(addr) & ~(clear)) | (set), (addr))
+
+/* PINCONFIG bits (sparx5 only) */
+enum {
+ PINCONF_BIAS,
+ PINCONF_SCHMITT,
+ PINCONF_DRIVE_STRENGTH,
+};
+
+#define BIAS_PD_BIT BIT(4)
+#define BIAS_PU_BIT BIT(3)
+#define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT)
+#define SCHMITT_BIT BIT(2)
+#define DRIVE_BITS GENMASK(1, 0)
+
+/* GPIO standard registers */
#define OCELOT_GPIO_OUT_SET 0x0
#define OCELOT_GPIO_OUT_CLR 0x4
#define OCELOT_GPIO_OUT 0x8
enum {
FUNC_NONE,
FUNC_GPIO,
+ FUNC_IRQ0,
FUNC_IRQ0_IN,
FUNC_IRQ0_OUT,
+ FUNC_IRQ1,
FUNC_IRQ1_IN,
FUNC_IRQ1_OUT,
+ FUNC_EXT_IRQ,
FUNC_MIIM,
+ FUNC_PHY_LED,
FUNC_PCI_WAKE,
+ FUNC_MD,
FUNC_PTP0,
FUNC_PTP1,
FUNC_PTP2,
FUNC_SG1,
FUNC_SG2,
FUNC_SI,
+ FUNC_SI2,
FUNC_TACHO,
FUNC_TWI,
FUNC_TWI2,
+ FUNC_TWI3,
FUNC_TWI_SCL_M,
FUNC_UART,
FUNC_UART2,
+ FUNC_UART3,
+ FUNC_PLL_STAT,
+ FUNC_EMMC,
+ FUNC_REF_CLK,
+ FUNC_RCVRD_CLK,
FUNC_MAX
};
static const char *const ocelot_function_names[] = {
[FUNC_NONE] = "none",
[FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0] = "irq0",
[FUNC_IRQ0_IN] = "irq0_in",
[FUNC_IRQ0_OUT] = "irq0_out",
+ [FUNC_IRQ1] = "irq1",
[FUNC_IRQ1_IN] = "irq1_in",
[FUNC_IRQ1_OUT] = "irq1_out",
+ [FUNC_EXT_IRQ] = "ext_irq",
[FUNC_MIIM] = "miim",
+ [FUNC_PHY_LED] = "phy_led",
[FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_MD] = "md",
[FUNC_PTP0] = "ptp0",
[FUNC_PTP1] = "ptp1",
[FUNC_PTP2] = "ptp2",
[FUNC_SG1] = "sg1",
[FUNC_SG2] = "sg2",
[FUNC_SI] = "si",
+ [FUNC_SI2] = "si2",
[FUNC_TACHO] = "tacho",
[FUNC_TWI] = "twi",
[FUNC_TWI2] = "twi2",
+ [FUNC_TWI3] = "twi3",
[FUNC_TWI_SCL_M] = "twi_scl_m",
[FUNC_UART] = "uart",
[FUNC_UART2] = "uart2",
+ [FUNC_UART3] = "uart3",
+ [FUNC_PLL_STAT] = "pll_stat",
+ [FUNC_EMMC] = "emmc",
+ [FUNC_REF_CLK] = "ref_clk",
+ [FUNC_RCVRD_CLK] = "rcvrd_clk",
};
struct ocelot_pmx_func {
struct pinctrl_dev *pctl;
struct gpio_chip gpio_chip;
struct regmap *map;
+ void __iomem *pincfg;
struct pinctrl_desc *desc;
struct ocelot_pmx_func func[FUNC_MAX];
u8 stride;
JAGUAR2_PIN(63),
};
+#define SPARX5_P(p, f0, f1, f2) \
+static struct ocelot_pin_caps sparx5_pin_##p = { \
+ .pin = p, \
+ .functions = { \
+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
+ }, \
+}
+
+SPARX5_P(0, SG0, PLL_STAT, NONE);
+SPARX5_P(1, SG0, NONE, NONE);
+SPARX5_P(2, SG0, NONE, NONE);
+SPARX5_P(3, SG0, NONE, NONE);
+SPARX5_P(4, SG1, NONE, NONE);
+SPARX5_P(5, SG1, NONE, NONE);
+SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
+SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
+SPARX5_P(8, PTP0, NONE, SFP);
+SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
+SPARX5_P(10, UART, NONE, NONE);
+SPARX5_P(11, UART, NONE, NONE);
+SPARX5_P(12, SG1, NONE, NONE);
+SPARX5_P(13, SG1, NONE, NONE);
+SPARX5_P(14, TWI, TWI_SCL_M, NONE);
+SPARX5_P(15, TWI, NONE, NONE);
+SPARX5_P(16, SI, TWI_SCL_M, SFP);
+SPARX5_P(17, SI, TWI_SCL_M, SFP);
+SPARX5_P(18, SI, TWI_SCL_M, SFP);
+SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
+SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
+SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
+SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
+SPARX5_P(23, PWM, UART3, TWI_SCL_M);
+SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
+SPARX5_P(25, PTP3, SI, TWI_SCL_M);
+SPARX5_P(26, UART2, SI, TWI_SCL_M);
+SPARX5_P(27, UART2, SI, TWI_SCL_M);
+SPARX5_P(28, TWI2, SI, SFP);
+SPARX5_P(29, TWI2, SI, SFP);
+SPARX5_P(30, SG2, SI, PWM);
+SPARX5_P(31, SG2, SI, TWI_SCL_M);
+SPARX5_P(32, SG2, SI, TWI_SCL_M);
+SPARX5_P(33, SG2, SI, SFP);
+SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
+SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
+SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
+SPARX5_P(37, SFP, NONE, EMMC);
+SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
+SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(44, SI, SFP, EMMC);
+SPARX5_P(45, SI, SFP, EMMC);
+SPARX5_P(46, NONE, SFP, EMMC);
+SPARX5_P(47, NONE, SFP, EMMC);
+SPARX5_P(48, TWI3, SI, SFP);
+SPARX5_P(49, TWI3, NONE, SFP);
+SPARX5_P(50, SFP, NONE, TWI_SCL_M);
+SPARX5_P(51, SFP, SI, TWI_SCL_M);
+SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
+SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
+SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
+SPARX5_P(55, SFP, PTP3, PCI_WAKE);
+SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
+SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
+SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
+SPARX5_P(59, MIIM, SFP, NONE);
+SPARX5_P(60, RECO_CLK, NONE, NONE);
+SPARX5_P(61, RECO_CLK, NONE, NONE);
+SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
+SPARX5_P(63, RECO_CLK, NONE, NONE);
+
+#define SPARX5_PIN(n) { \
+ .number = n, \
+ .name = "GPIO_"#n, \
+ .drv_data = &sparx5_pin_##n \
+}
+
+static const struct pinctrl_pin_desc sparx5_pins[] = {
+ SPARX5_PIN(0),
+ SPARX5_PIN(1),
+ SPARX5_PIN(2),
+ SPARX5_PIN(3),
+ SPARX5_PIN(4),
+ SPARX5_PIN(5),
+ SPARX5_PIN(6),
+ SPARX5_PIN(7),
+ SPARX5_PIN(8),
+ SPARX5_PIN(9),
+ SPARX5_PIN(10),
+ SPARX5_PIN(11),
+ SPARX5_PIN(12),
+ SPARX5_PIN(13),
+ SPARX5_PIN(14),
+ SPARX5_PIN(15),
+ SPARX5_PIN(16),
+ SPARX5_PIN(17),
+ SPARX5_PIN(18),
+ SPARX5_PIN(19),
+ SPARX5_PIN(20),
+ SPARX5_PIN(21),
+ SPARX5_PIN(22),
+ SPARX5_PIN(23),
+ SPARX5_PIN(24),
+ SPARX5_PIN(25),
+ SPARX5_PIN(26),
+ SPARX5_PIN(27),
+ SPARX5_PIN(28),
+ SPARX5_PIN(29),
+ SPARX5_PIN(30),
+ SPARX5_PIN(31),
+ SPARX5_PIN(32),
+ SPARX5_PIN(33),
+ SPARX5_PIN(34),
+ SPARX5_PIN(35),
+ SPARX5_PIN(36),
+ SPARX5_PIN(37),
+ SPARX5_PIN(38),
+ SPARX5_PIN(39),
+ SPARX5_PIN(40),
+ SPARX5_PIN(41),
+ SPARX5_PIN(42),
+ SPARX5_PIN(43),
+ SPARX5_PIN(44),
+ SPARX5_PIN(45),
+ SPARX5_PIN(46),
+ SPARX5_PIN(47),
+ SPARX5_PIN(48),
+ SPARX5_PIN(49),
+ SPARX5_PIN(50),
+ SPARX5_PIN(51),
+ SPARX5_PIN(52),
+ SPARX5_PIN(53),
+ SPARX5_PIN(54),
+ SPARX5_PIN(55),
+ SPARX5_PIN(56),
+ SPARX5_PIN(57),
+ SPARX5_PIN(58),
+ SPARX5_PIN(59),
+ SPARX5_PIN(60),
+ SPARX5_PIN(61),
+ SPARX5_PIN(62),
+ SPARX5_PIN(63),
+};
+
static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(ocelot_function_names);
* ALT[1]
* This is racy because both registers can't be updated at the same time
* but it doesn't matter much for now.
+ * Note: ALT0/ALT1 are organized specially for 64 gpio targets
*/
regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
BIT(p), f << p);
return 0;
}
+static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
+ unsigned int pin,
+ unsigned int reg,
+ int *val)
+{
+ int ret = -EOPNOTSUPP;
+
+ if (info->pincfg) {
+ u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
+
+ ret = 0;
+ switch (reg) {
+ case PINCONF_BIAS:
+ *val = regcfg & BIAS_BITS;
+ break;
+
+ case PINCONF_SCHMITT:
+ *val = regcfg & SCHMITT_BIT;
+ break;
+
+ case PINCONF_DRIVE_STRENGTH:
+ *val = regcfg & DRIVE_BITS;
+ break;
+
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+ }
+ return ret;
+}
+
+static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
+ unsigned int pin,
+ unsigned int reg,
+ int val)
+{
+ int ret = -EOPNOTSUPP;
+
+ if (info->pincfg) {
+ void __iomem *regaddr = info->pincfg + (pin * sizeof(u32));
+
+ ret = 0;
+ switch (reg) {
+ case PINCONF_BIAS:
+ ocelot_clrsetbits(regaddr, BIAS_BITS, val);
+ break;
+
+ case PINCONF_SCHMITT:
+ ocelot_clrsetbits(regaddr, SCHMITT_BIT, val);
+ break;
+
+ case PINCONF_DRIVE_STRENGTH:
+ if (val <= 3)
+ ocelot_clrsetbits(regaddr, DRIVE_BITS, val);
+ else
+ ret = -EINVAL;
+ break;
+
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+ }
+ return ret;
+}
+
+static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+ u32 param = pinconf_to_config_param(*config);
+ int val, err;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
+ if (err)
+ return err;
+ if (param == PIN_CONFIG_BIAS_DISABLE)
+ val = (val == 0 ? true : false);
+ else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
+ val = (val & BIAS_PD_BIT ? true : false);
+ else /* PIN_CONFIG_BIAS_PULL_UP */
+ val = (val & BIAS_PU_BIT ? true : false);
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
+ if (err)
+ return err;
+
+ val = (val & SCHMITT_BIT ? true : false);
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
+ &val);
+ if (err)
+ return err;
+ break;
+
+ case PIN_CONFIG_OUTPUT:
+ err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
+ &val);
+ if (err)
+ return err;
+ val = !!(val & BIT(pin % 32));
+ break;
+
+ case PIN_CONFIG_INPUT_ENABLE:
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
+ &val);
+ if (err)
+ return err;
+ val = val & BIT(pin % 32);
+ if (param == PIN_CONFIG_OUTPUT_ENABLE)
+ val = !!val;
+ else
+ val = !val;
+ break;
+
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, val);
+
+ return 0;
+}
+
+static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+ u32 param, arg, p;
+ int cfg, err = 0;
+
+ for (cfg = 0; cfg < num_configs; cfg++) {
+ param = pinconf_to_config_param(configs[cfg]);
+ arg = pinconf_to_config_argument(configs[cfg]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
+ (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
+ BIAS_PD_BIT;
+
+ err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
+ if (err)
+ goto err;
+
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ arg = arg ? SCHMITT_BIT : 0;
+ err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
+ arg);
+ if (err)
+ goto err;
+
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ err = ocelot_hw_set_value(info, pin,
+ PINCONF_DRIVE_STRENGTH,
+ arg);
+ if (err)
+ goto err;
+
+ break;
+
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ case PIN_CONFIG_INPUT_ENABLE:
+ case PIN_CONFIG_OUTPUT:
+ p = pin % 32;
+ if (arg)
+ regmap_write(info->map,
+ REG(OCELOT_GPIO_OUT_SET, info,
+ pin),
+ BIT(p));
+ else
+ regmap_write(info->map,
+ REG(OCELOT_GPIO_OUT_CLR, info,
+ pin),
+ BIT(p));
+ regmap_update_bits(info->map,
+ REG(OCELOT_GPIO_OE, info, pin),
+ BIT(p),
+ param == PIN_CONFIG_INPUT_ENABLE ?
+ 0 : BIT(p));
+ break;
+
+ default:
+ err = -EOPNOTSUPP;
+ }
+ }
+err:
+ return err;
+}
+
+static const struct pinconf_ops ocelot_confops = {
+ .is_generic = true,
+ .pin_config_get = ocelot_pinconf_get,
+ .pin_config_set = ocelot_pinconf_set,
+ .pin_config_config_dbg_show = pinconf_generic_dump_config,
+};
+
static const struct pinctrl_ops ocelot_pctl_ops = {
.get_groups_count = ocelot_pctl_get_groups_count,
.get_group_name = ocelot_pctl_get_group_name,
.owner = THIS_MODULE,
};
+static struct pinctrl_desc sparx5_desc = {
+ .name = "sparx5-pinctrl",
+ .pins = sparx5_pins,
+ .npins = ARRAY_SIZE(sparx5_pins),
+ .pctlops = &ocelot_pctl_ops,
+ .pmxops = &ocelot_pmx_ops,
+ .confops = &ocelot_confops,
+ .owner = THIS_MODULE,
+};
+
static int ocelot_create_group_func_map(struct device *dev,
struct ocelot_pinctrl *info)
{
}
for (i = 0; i < npins; i++)
- info->func[f].groups[i] = info->desc->pins[pins[i]].name;
+ info->func[f].groups[i] =
+ info->desc->pins[pins[i]].name;
}
kfree(pins);
static const struct of_device_id ocelot_pinctrl_of_match[] = {
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
+ { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
{},
};
struct device *dev = &pdev->dev;
struct ocelot_pinctrl *info;
void __iomem *base;
+ struct resource *res;
int ret;
struct regmap_config regmap_config = {
.reg_bits = 32,
}
info->stride = 1 + (info->desc->npins - 1) / 32;
+
regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
info->map = devm_regmap_init_mmio(dev, base, ®map_config);
dev_set_drvdata(dev, info->map);
info->dev = dev;
+ /* Pinconf registers */
+ if (info->desc->confops) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n");
+ else
+ info->pincfg = base;
+ }
+
ret = ocelot_pinctrl_register(pdev, info);
if (ret)
return ret;
if (ret)
return ret;
+ dev_info(dev, "driver registered\n");
+
return 0;
}
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2012 Linaro Ltd
- * http://www.linaro.org
+ * https://www.linaro.org
*
* and pinctrl-at91:
* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
RK3399,
};
-/**
+/*
* Encode variants of iomux registers into a type variable
*/
#define IOMUX_GPIO_ONLY BIT(0)
#define IOMUX_WIDTH_2BIT BIT(5)
/**
+ * struct rockchip_iomux
* @type: iomux variant using IOMUX_* constants
* @offset: if initialized to -1 it will be autocalculated, by specifying
* an initial offset value the relevant source offset can be reset
int offset;
};
-/**
+/*
* enum type index corresponding to rockchip_perpin_drv_list arrays index.
*/
enum rockchip_pin_drv_type {
DRV_TYPE_MAX
};
-/**
+/*
* enum type index corresponding to rockchip_pull_list arrays index.
*/
enum rockchip_pin_pull_type {
};
/**
+ * struct rockchip_drv
* @drv_type: drive strength variant using rockchip_perpin_drv_type
* @offset: if initialized to -1 it will be autocalculated, by specifying
* an initial offset value the relevant source offset can be reset
};
/**
+ * struct rockchip_pin_bank
* @reg_base: register base of the gpio bank
- * @reg_pull: optional separate register for additional pull settings
+ * @regmap_pull: optional separate register for additional pull settings
* @clk: clock of the gpio bank
* @irq: interrupt of the gpio bank
* @saved_masks: Saved content of GPIO_INTEN at suspend time.
* @gpio_chip: gpiolib chip
* @grange: gpio range
* @slock: spinlock for the gpio bank
+ * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
+ * @recalced_mask: bit mask to indicate a need to recalulate the mask
* @route_mask: bits describing the routing pins of per bank
*/
struct rockchip_pin_bank {
* @bank_num: bank number.
* @pin: index at register or used to calc index.
* @func: the min pin.
+ * @route_location: the mux route location (same, pmu, grf).
* @route_offset: the max pin.
* @route_val: the register offset.
*/
u32 route_val;
};
-/**
- */
struct rockchip_pin_ctrl {
struct rockchip_pin_bank *pin_banks;
u32 nr_banks;
* @name: name of the pin group, used to lookup the group.
* @pins: the pins included in this group.
* @npins: number of pins included in this group.
- * @func: the mux function number to be programmed when selected.
- * @configs: the config values to be set for each pin
- * @nconfigs: number of configs for each pin
+ * @data: local pin configuration
*/
struct rockchip_pin_group {
const char *name;
* struct rockchip_pmx_func: represent a pin function.
* @name: name of the pin function, used to lookup the function.
* @groups: one or more names of pin groups that provide this function.
- * @num_groups: number of groups included in @groups.
+ * @ngroups: number of groups included in @groups.
*/
struct rockchip_pmx_func {
const char *name;
* RZ/A1 pinmux flags
*/
-/**
+/*
* rza1_bidir_pin - describe a single pin that needs bidir flag applied.
*/
struct rza1_bidir_pin {
u8 func: 4;
};
-/**
+/*
* rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
* Each struct rza1_bidir_entry describes a port.
*/
const struct rza1_bidir_pin *pins;
};
-/**
+/*
* rza1_swio_pin - describe a single pin that needs swio flag applied.
*/
struct rza1_swio_pin {
u16 input: 1;
};
-/**
+/*
* rza1_swio_entry - describe a list of pins that needs swio flag applied
*/
struct rza1_swio_entry {
const struct rza1_swio_pin *pins;
};
-/**
+/*
* rza1_pinmux_conf - group together bidir and swio pinmux flag tables
*/
struct rza1_pinmux_conf {
* RZ/A1 types
*/
/**
- * rza1_mux_conf - describes a pin multiplexing operation
+ * struct rza1_mux_conf - describes a pin multiplexing operation
*
* @id: the pin identifier from 0 to RZA1_NPINS
* @port: the port where pin sits on
};
/**
- * rza1_port - describes a pin port
+ * struct rza1_port - describes a pin port
*
* This is mostly useful to lock register writes per-bank and not globally.
*
};
/**
- * rza1_pinctrl - RZ pincontroller device
+ * struct rza1_pinctrl - RZ pincontroller device
*
* @dev: parent device structure
* @mutex: protect [pinctrl|pinmux]_generic functions
* @base: logical address base
- * @nports: number of pin controller ports
+ * @nport: number of pin controller ports
* @ports: pin controller banks
* @pins: pin array for pinctrl core
* @desc: pincontroller desc for pinctrl core
return -ENOENT;
}
-/**
+/*
* rza1_pinmux_get_flags() - return pinmux flags associated to a pin
*/
static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
* RZ/A1 SoC operations
*/
-/**
+/*
* rza1_set_bit() - un-locked set/clear a single bit in pin configuration
* registers
*/
/**
* rza1_pin_mux_single() - configure pin multiplexing on a single pin
*
- * @pinctrl: RZ/A1 pin controller device
+ * @rza1_pctl: RZ/A1 pin controller device
* @mux_conf: pin multiplexing descriptor
*/
static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
* struct pcs_func_vals - mux function register offset and value pair
* @reg: register virtual address
* @val: register value
+ * @mask: mask
*/
struct pcs_func_vals {
void __iomem *reg;
* @nvals: number of entries in vals array
* @pgnames: array of pingroup names the function uses
* @npgnames: number of pingroup names the function uses
+ * @conf: array of pin configurations
+ * @nconfs: number of pin configurations available
* @node: list node
*/
struct pcs_function {
case PIN_CONFIG_BIAS_PULL_UP:
if (arg)
pcs_pinconf_clear_bias(pctldev, pin);
- /* fall through */
+ fallthrough;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
data &= ~func->conf[i].mask;
if (arg)
* pcs_add_pin() - add a pin to the static per controller pin array
* @pcs: pcs driver instance
* @offset: register offset from base
+ * @pin_pos: unused
*/
static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
unsigned pin_pos)
/* If pinconf isn't supported, don't parse properties in below. */
if (!PCS_HAS_PINCONF)
- return 0;
+ return -ENOTSUPP;
/* cacluate how much properties are supported in current node */
for (i = 0; i < ARRAY_SIZE(prop2); i++) {
nconfs++;
}
if (!nconfs)
- return 0;
+ return -ENOTSUPP;
func->conf = devm_kcalloc(pcs->dev,
nconfs, sizeof(struct pcs_conf_vals),
/**
* pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
- * @pctldev: pin controller device
* @pcs: pinctrl driver instance
* @np: device node of the mux entry
* @map: map entry
break;
}
- /* Index plus one value cell */
offset = pinctrl_spec.args[0];
vals[found].reg = pcs->base + offset;
- vals[found].val = pinctrl_spec.args[1];
+
+ switch (pinctrl_spec.args_count) {
+ case 2:
+ vals[found].val = pinctrl_spec.args[1];
+ break;
+ case 3:
+ vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
+ break;
+ }
dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
pinctrl_spec.np, offset, pinctrl_spec.args[1]);
if (PCS_HAS_PINCONF && function) {
res = pcs_parse_pinconf(pcs, np, function, map);
- if (res)
+ if (res == 0)
+ *num_maps = 2;
+ else if (res == -ENOTSUPP)
+ *num_maps = 1;
+ else
goto free_pingroups;
- *num_maps = 2;
} else {
*num_maps = 1;
}
}
return ret;
}
+
/**
+ * struct pcs_interrupt
* @reg: virtual address of interrupt register
* @hwirq: hardware irq number
* @irq: virtual irq number
/**
* pcs_irq_set() - enables or disables an interrupt
+ * @pcs_soc: SoC specific settings
+ * @irq: interrupt
+ * @enable: enable or disable the interrupt
*
* Note that this currently assumes one interrupt per pinctrl
* register that is typically used for wake-up events.
/**
* pcs_irq_handle() - common interrupt handler
- * @pcs_irq: interrupt data
+ * @pcs_soc: SoC specific settings
*
* Note that this currently assumes we have one interrupt bit per
* mux register. This interrupt is typically used for wake-up events.
/**
* pcs_irq_handle() - handler for the dedicated chained interrupt case
- * @irq: interrupt
* @desc: interrupt descriptor
*
* Use this if you have a separate interrupt for each
struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
struct device_node *np = pdev->dev.of_node;
struct stmfx_pinctrl *pctl;
+ struct gpio_irq_chip *girq;
int irq, ret;
pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
pctl->gpio_chip.can_sleep = true;
pctl->gpio_chip.of_node = np;
- ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
- if (ret) {
- dev_err(pctl->dev, "gpio_chip registration failed\n");
- return ret;
- }
-
- ret = stmfx_pinctrl_gpio_function_enable(pctl);
- if (ret)
- return ret;
-
pctl->irq_chip.name = dev_name(pctl->dev);
pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask;
pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask;
pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources;
pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources;
- ret = gpiochip_irqchip_add_nested(&pctl->gpio_chip, &pctl->irq_chip,
- 0, handle_bad_irq, IRQ_TYPE_NONE);
+ girq = &pctl->gpio_chip.irq;
+ girq->chip = &pctl->irq_chip;
+ /* This will let us handle the parent IRQ in the driver */
+ girq->parent_handler = NULL;
+ girq->num_parents = 0;
+ girq->parents = NULL;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+ girq->threaded = true;
+
+ ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
if (ret) {
- dev_err(pctl->dev, "cannot add irqchip to gpiochip\n");
+ dev_err(pctl->dev, "gpio_chip registration failed\n");
return ret;
}
+ ret = stmfx_pinctrl_gpio_function_enable(pctl);
+ if (ret)
+ return ret;
+
ret = devm_request_threaded_irq(pctl->dev, irq, NULL,
stmfx_pinctrl_irq_thread_fn,
IRQF_ONESHOT,
return ret;
}
- gpiochip_set_nested_irqchip(&pctl->gpio_chip, &pctl->irq_chip, irq);
-
dev_info(pctl->dev,
"%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask));
if (pctl->data->model != SX150X_789)
pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
- ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
- if (ret)
- return ret;
-
- ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
- 0, 0, pctl->data->npins);
- if (ret)
- return ret;
-
/* Add Interrupt support if an irq is specified */
if (client->irq > 0) {
+ struct gpio_irq_chip *girq;
+
pctl->irq_chip.irq_mask = sx150x_irq_mask;
pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
/*
* Because sx150x_irq_threaded_fn invokes all of the
- * nested interrrupt handlers via handle_nested_irq,
- * any "handler" passed to gpiochip_irqchip_add()
+ * nested interrupt handlers via handle_nested_irq,
+ * any "handler" assigned to struct gpio_irq_chip
* below is going to be ignored, so the choice of the
* function does not matter that much.
*
* plus it will be instantly noticeable if it is ever
* called (should not happen)
*/
- ret = gpiochip_irqchip_add_nested(&pctl->gpio,
- &pctl->irq_chip, 0,
- handle_bad_irq, IRQ_TYPE_NONE);
- if (ret) {
- dev_err(dev, "could not connect irqchip to gpiochip\n");
- return ret;
- }
+ girq = &pctl->gpio.irq;
+ girq->chip = &pctl->irq_chip;
+ /* This will let us handle the parent IRQ in the driver */
+ girq->parent_handler = NULL;
+ girq->num_parents = 0;
+ girq->parents = NULL;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+ girq->threaded = true;
ret = devm_request_threaded_irq(dev, client->irq, NULL,
sx150x_irq_thread_fn,
pctl->irq_chip.name, pctl);
if (ret < 0)
return ret;
-
- gpiochip_set_nested_irqchip(&pctl->gpio,
- &pctl->irq_chip,
- client->irq);
}
+ ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
+ if (ret)
+ return ret;
+
+ ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
+ 0, 0, pctl->data->npins);
+ if (ret)
+ return ret;
+
return 0;
}
* pinmux_can_be_used_for_gpio() - check if a specific pin
* is either muxed to a different function or used as gpio.
*
+ * @pctldev: the associated pin controller device
* @pin: the pin number in the global pin space
*
* Controllers not defined as strict will always return true,
/**
* pin_request() - request a single pin to be muxed in, typically for GPIO
+ * @pctldev: the associated pin controller device
* @pin: the pin number in the global pin space
* @owner: a representation of the owner of this pin; typically the device
* name that controls its mux function, or the requested GPIO name
* @pctldev: pin controller device affected
* @pin: the pin to mux in for GPIO
* @range: the applicable GPIO range
+ * @gpio: number of requested GPIO
*/
int pinmux_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
/**
* pinmux_generic_get_function() - returns a function based on the number
* @pctldev: pin controller device
- * @group_selector: function number
+ * @selector: function number
*/
struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev,
unsigned int selector)
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
+ .od_bit = 12, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
* @dev: device handle.
* @pctrl: pinctrl handle.
* @chip: gpiochip handle.
+ * @desc: pin controller descriptor
* @restart_nb: restart notifier block.
+ * @irq_chip: irq chip information
* @irq: parent irq for the TLMM irq_chip.
+ * @intr_target_use_scm: route irq to application cpu using scm calls
* @lock: Spinlock to protect register resources as well
* as msm_pinctrl data structures.
* @enabled_irqs: Bitmap of currently enabled irqs.
* @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
* detection.
* @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
- * @soc; Reference to soc_data of platform specific data.
+ * @soc: Reference to soc_data of platform specific data.
* @regs: Base addresses for the TLMM tiles.
+ * @phys_base: Physical base address
*/
struct msm_pinctrl {
struct device *dev;
*bit = g->pull_bit;
*mask = 3;
break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ *bit = g->od_bit;
+ *mask = 1;
+ break;
case PIN_CONFIG_DRIVE_STRENGTH:
*bit = g->drv_bit;
*mask = 7;
if (!arg)
return -EINVAL;
break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ /* Pin is not open-drain */
+ if (!arg)
+ return -EINVAL;
+ arg = 1;
+ break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = msm_regval_to_drive(arg);
break;
else
arg = MSM_PULL_UP;
break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ arg = 1;
+ break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* Check for invalid values */
if (arg > 16 || arg < 2 || (arg % 2) != 0)
* @mux_bit: Offset in @ctl_reg for the pinmux function selection.
* @pull_bit: Offset in @ctl_reg for the bias configuration.
* @drv_bit: Offset in @ctl_reg for the drive strength configuration.
+ * @od_bit: Offset in @ctl_reg for controlling open drain.
* @oe_bit: Offset in @ctl_reg for controlling output enable.
* @in_bit: Offset in @io_reg for the input bit value.
* @out_bit: Offset in @io_reg for the output bit value.
unsigned pull_bit:5;
unsigned drv_bit:5;
+ unsigned od_bit:5;
unsigned oe_bit:5;
unsigned in_bit:5;
unsigned out_bit:5;
static const char * const modem_tsync_groups[] = {
"gpio93",
};
-static const char * const nav_tsync_groups[] = {
- "gpio93",
-};
static const char * const ssbi_wtr1_groups[] = {
"gpio79", "gpio94",
};
switch (subtype) {
case PMIC_GPIO_SUBTYPE_GPIO_4CH:
pad->have_buffer = true;
- /* Fall through */
+ fallthrough;
case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
pad->num_sources = 4;
break;
case PMIC_GPIO_SUBTYPE_GPIO_8CH:
pad->have_buffer = true;
- /* Fall through */
+ fallthrough;
case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
pad->num_sources = 8;
break;
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
+ /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
+ { .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
+ /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
+ { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
/* pm8150b has 12 GPIOs with holes on 3, r and 7 */
return -EINVAL;
}
pin->pull_up_strength = arg;
- /* FALLTHROUGH */
+ fallthrough;
case PIN_CONFIG_BIAS_PULL_UP:
pin->bias = pin->pull_up_strength;
banks |= BIT(2);
u32 eint_con;
u32 eint_mask;
u32 eint_pend;
- u32 eint_wake_mask_value;
+ u32 *eint_wake_mask_value;
u32 eint_wake_mask_reg;
void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata,
struct exynos_irq_chip *irq_chip);
/*
* irq_chip for gpio interrupts.
*/
-static struct exynos_irq_chip exynos_gpio_irq_chip = {
+static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = {
.chip = {
.name = "exynos_gpio_irq_chip",
.irq_unmask = exynos_irq_unmask,
* exynos_eint_gpio_init() - setup handling of external gpio interrupts.
* @d: driver data of samsung pinctrl driver.
*/
-int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
+__init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
{
struct samsung_pin_bank *bank;
struct device *dev = d->dev;
for (i = 0; i < d->nr_banks; ++i, ++bank) {
if (bank->eint_type != EINT_TYPE_GPIO)
continue;
+
+ bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,
+ sizeof(*bank->irq_chip), GFP_KERNEL);
+ if (!bank->irq_chip) {
+ ret = -ENOMEM;
+ goto err_domains;
+ }
+ bank->irq_chip->chip.name = bank->name;
+
bank->irq_domain = irq_domain_add_linear(bank->of_node,
bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
goto err_domains;
}
- bank->irq_chip = &exynos_gpio_irq_chip;
}
return 0;
pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
if (!on)
- our_chip->eint_wake_mask_value |= bit;
+ *our_chip->eint_wake_mask_value |= bit;
else
- our_chip->eint_wake_mask_value &= ~bit;
+ *our_chip->eint_wake_mask_value &= ~bit;
return 0;
}
pmu_regs = drvdata->retention_ctrl->priv;
dev_info(drvdata->dev,
"Setting external wakeup interrupt mask: 0x%x\n",
- irq_chip->eint_wake_mask_value);
+ *irq_chip->eint_wake_mask_value);
regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg,
- irq_chip->eint_wake_mask_value);
+ *irq_chip->eint_wake_mask_value);
}
static void
clk_base = (void __iomem *) drvdata->retention_ctrl->priv;
- __raw_writel(irq_chip->eint_wake_mask_value,
+ __raw_writel(*irq_chip->eint_wake_mask_value,
clk_base + irq_chip->eint_wake_mask_reg);
}
+static u32 eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED;
/*
* irq_chip for wakeup interrupts
*/
.eint_con = EXYNOS_WKUP_ECON_OFFSET,
.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
- .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED,
+ .eint_wake_mask_value = &eint_wake_mask_value,
/* Only differences with exynos4210_wkup_irq_chip: */
.eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK,
.set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask,
.eint_con = EXYNOS_WKUP_ECON_OFFSET,
.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
- .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED,
+ .eint_wake_mask_value = &eint_wake_mask_value,
.eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK,
.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
};
.eint_con = EXYNOS7_WKUP_ECON_OFFSET,
.eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
.eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
- .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED,
+ .eint_wake_mask_value = &eint_wake_mask_value,
.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
};
* exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
* @d: driver data of samsung pinctrl driver.
*/
-int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
+__init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
{
struct device *dev = d->dev;
struct device_node *wkup_np = NULL;
struct samsung_pin_bank *bank;
struct exynos_weint_data *weint_data;
struct exynos_muxed_weint_data *muxed_data;
- struct exynos_irq_chip *irq_chip;
+ const struct exynos_irq_chip *irq_chip;
unsigned int muxed_banks = 0;
unsigned int i;
int idx, irq;
match = of_match_node(exynos_wkup_irq_ids, np);
if (match) {
- irq_chip = kmemdup(match->data,
- sizeof(*irq_chip), GFP_KERNEL);
- if (!irq_chip) {
- of_node_put(np);
- return -ENOMEM;
- }
+ irq_chip = match->data;
wkup_np = np;
break;
}
if (bank->eint_type != EINT_TYPE_WKUP)
continue;
+ bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
+ GFP_KERNEL);
+ if (!bank->irq_chip) {
+ of_node_put(wkup_np);
+ return -ENOMEM;
+ }
+ bank->irq_chip->chip.name = bank->name;
+
bank->irq_domain = irq_domain_add_linear(bank->of_node,
bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
return -ENXIO;
}
- bank->irq_chip = irq_chip;
-
if (!of_find_property(bank->of_node, "interrupts", NULL)) {
bank->eint_type = EINT_TYPE_WKUP_MUX;
++muxed_banks;
irq_chip = bank->irq_chip;
irq_chip->set_eint_wakeup_mask(drvdata,
irq_chip);
- } else if (bank->irq_chip != irq_chip) {
- dev_warn(drvdata->dev,
- "More than one external wakeup interrupt chip configured (bank: %s). This is not supported by hardware nor by driver.\n",
- bank->name);
}
}
}
}
/**
- * struct s3c24xx_eint_data: EINT common data
+ * struct s3c24xx_eint_data - EINT common data
* @drvdata: pin controller driver data
* @domains: IRQ domains of particular EINT interrupts
* @parents: mapped parent irqs in the main interrupt controller
};
/**
- * struct s3c24xx_eint_domain_data: per irq-domain data
+ * struct s3c24xx_eint_domain_data - per irq-domain data
* @bank: pin bank related to the domain
* @eint_data: common data
- * eint0_3_parent_only: live eints 0-3 only in the main intc
+ * @eint0_3_parent_only: live eints 0-3 only in the main intc
*/
struct s3c24xx_eint_domain_data {
struct samsung_pin_bank *bank;
}
/**
- * struct s3c64xx_eint0_data: EINT0 common data
+ * struct s3c64xx_eint0_data - EINT0 common data
* @drvdata: pin controller driver data
* @domains: IRQ domains of particular EINT0 interrupts
* @pins: pin offsets inside of banks of particular EINT0 interrupts
};
/**
- * struct s3c64xx_eint0_domain_data: EINT0 per-domain data
+ * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
* @bank: pin bank related to the domain
* @eints: EINT0 interrupts related to the domain
*/
};
/**
- * struct s3c64xx_eint_gpio_data: GPIO EINT data
+ * struct s3c64xx_eint_gpio_data - GPIO EINT data
* @drvdata: pin controller driver data
* @domains: array of domains related to EINT interrupt groups
*/
return 0;
}
-/**
+/*
* samsung_pinctrl_suspend - save pinctrl state for suspend
*
* Save data for all banks handled by this device.
return 0;
}
-/**
+/*
* samsung_pinctrl_resume - restore pinctrl state from suspend
*
* Restore one of the banks that was saved during suspend.
select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1
select PINCTRL_PFC_R8A774B1 if ARCH_R8A774B1
select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0
+ select PINCTRL_PFC_R8A774E1 if ARCH_R8A774E1
select PINCTRL_PFC_R8A7778 if ARCH_R8A7778
select PINCTRL_PFC_R8A7779 if ARCH_R8A7779
select PINCTRL_PFC_R8A7790 if ARCH_R8A7790
config PINCTRL_PFC_R8A774C0
bool "RZ/G2E pin control support" if COMPILE_TEST
+config PINCTRL_PFC_R8A774E1
+ bool "RZ/G2H pin control support" if COMPILE_TEST
+
config PINCTRL_PFC_R8A7778
bool "R-Car M1A pin control support" if COMPILE_TEST
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o
+obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a77951.o
obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
.data = &r8a774c0_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A774E1
+ {
+ .compatible = "renesas,pfc-r8a774e1",
+ .data = &r8a774e1_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
{
.compatible = "renesas,pfc-r8a7778",
VI5_CLK_MARK,
};
-static const struct sh_pfc_pin_group pinmux_groups[] = {
- SH_PFC_PIN_GROUP(audio_clk_a_a),
- SH_PFC_PIN_GROUP(audio_clk_a_b),
- SH_PFC_PIN_GROUP(audio_clk_a_c),
- SH_PFC_PIN_GROUP(audio_clk_b_a),
- SH_PFC_PIN_GROUP(audio_clk_b_b),
- SH_PFC_PIN_GROUP(audio_clk_c_a),
- SH_PFC_PIN_GROUP(audio_clk_c_b),
- SH_PFC_PIN_GROUP(audio_clkout_a),
- SH_PFC_PIN_GROUP(audio_clkout_b),
- SH_PFC_PIN_GROUP(audio_clkout_c),
- SH_PFC_PIN_GROUP(audio_clkout_d),
- SH_PFC_PIN_GROUP(audio_clkout1_a),
- SH_PFC_PIN_GROUP(audio_clkout1_b),
- SH_PFC_PIN_GROUP(audio_clkout2_a),
- SH_PFC_PIN_GROUP(audio_clkout2_b),
- SH_PFC_PIN_GROUP(audio_clkout3_a),
- SH_PFC_PIN_GROUP(audio_clkout3_b),
- SH_PFC_PIN_GROUP(avb_link),
- SH_PFC_PIN_GROUP(avb_magic),
- SH_PFC_PIN_GROUP(avb_phy_int),
- SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
- SH_PFC_PIN_GROUP(avb_mdio),
- SH_PFC_PIN_GROUP(avb_mii),
- SH_PFC_PIN_GROUP(avb_avtp_pps),
- SH_PFC_PIN_GROUP(avb_avtp_match_a),
- SH_PFC_PIN_GROUP(avb_avtp_capture_a),
- SH_PFC_PIN_GROUP(avb_avtp_match_b),
- SH_PFC_PIN_GROUP(avb_avtp_capture_b),
- SH_PFC_PIN_GROUP(can0_data_a),
- SH_PFC_PIN_GROUP(can0_data_b),
- SH_PFC_PIN_GROUP(can1_data),
- SH_PFC_PIN_GROUP(can_clk),
- SH_PFC_PIN_GROUP(canfd0_data_a),
- SH_PFC_PIN_GROUP(canfd0_data_b),
- SH_PFC_PIN_GROUP(canfd1_data),
- SH_PFC_PIN_GROUP(drif0_ctrl_a),
- SH_PFC_PIN_GROUP(drif0_data0_a),
- SH_PFC_PIN_GROUP(drif0_data1_a),
- SH_PFC_PIN_GROUP(drif0_ctrl_b),
- SH_PFC_PIN_GROUP(drif0_data0_b),
- SH_PFC_PIN_GROUP(drif0_data1_b),
- SH_PFC_PIN_GROUP(drif0_ctrl_c),
- SH_PFC_PIN_GROUP(drif0_data0_c),
- SH_PFC_PIN_GROUP(drif0_data1_c),
- SH_PFC_PIN_GROUP(drif1_ctrl_a),
- SH_PFC_PIN_GROUP(drif1_data0_a),
- SH_PFC_PIN_GROUP(drif1_data1_a),
- SH_PFC_PIN_GROUP(drif1_ctrl_b),
- SH_PFC_PIN_GROUP(drif1_data0_b),
- SH_PFC_PIN_GROUP(drif1_data1_b),
- SH_PFC_PIN_GROUP(drif1_ctrl_c),
- SH_PFC_PIN_GROUP(drif1_data0_c),
- SH_PFC_PIN_GROUP(drif1_data1_c),
- SH_PFC_PIN_GROUP(drif2_ctrl_a),
- SH_PFC_PIN_GROUP(drif2_data0_a),
- SH_PFC_PIN_GROUP(drif2_data1_a),
- SH_PFC_PIN_GROUP(drif2_ctrl_b),
- SH_PFC_PIN_GROUP(drif2_data0_b),
- SH_PFC_PIN_GROUP(drif2_data1_b),
- SH_PFC_PIN_GROUP(drif3_ctrl_a),
- SH_PFC_PIN_GROUP(drif3_data0_a),
- SH_PFC_PIN_GROUP(drif3_data1_a),
- SH_PFC_PIN_GROUP(drif3_ctrl_b),
- SH_PFC_PIN_GROUP(drif3_data0_b),
- SH_PFC_PIN_GROUP(drif3_data1_b),
- SH_PFC_PIN_GROUP(du_rgb666),
- SH_PFC_PIN_GROUP(du_rgb888),
- SH_PFC_PIN_GROUP(du_clk_out_0),
- SH_PFC_PIN_GROUP(du_clk_out_1),
- SH_PFC_PIN_GROUP(du_sync),
- SH_PFC_PIN_GROUP(du_oddf),
- SH_PFC_PIN_GROUP(du_cde),
- SH_PFC_PIN_GROUP(du_disp),
- SH_PFC_PIN_GROUP(hscif0_data),
- SH_PFC_PIN_GROUP(hscif0_clk),
- SH_PFC_PIN_GROUP(hscif0_ctrl),
- SH_PFC_PIN_GROUP(hscif1_data_a),
- SH_PFC_PIN_GROUP(hscif1_clk_a),
- SH_PFC_PIN_GROUP(hscif1_ctrl_a),
- SH_PFC_PIN_GROUP(hscif1_data_b),
- SH_PFC_PIN_GROUP(hscif1_clk_b),
- SH_PFC_PIN_GROUP(hscif1_ctrl_b),
- SH_PFC_PIN_GROUP(hscif2_data_a),
- SH_PFC_PIN_GROUP(hscif2_clk_a),
- SH_PFC_PIN_GROUP(hscif2_ctrl_a),
- SH_PFC_PIN_GROUP(hscif2_data_b),
- SH_PFC_PIN_GROUP(hscif2_clk_b),
- SH_PFC_PIN_GROUP(hscif2_ctrl_b),
- SH_PFC_PIN_GROUP(hscif2_data_c),
- SH_PFC_PIN_GROUP(hscif2_clk_c),
- SH_PFC_PIN_GROUP(hscif2_ctrl_c),
- SH_PFC_PIN_GROUP(hscif3_data_a),
- SH_PFC_PIN_GROUP(hscif3_clk),
- SH_PFC_PIN_GROUP(hscif3_ctrl),
- SH_PFC_PIN_GROUP(hscif3_data_b),
- SH_PFC_PIN_GROUP(hscif3_data_c),
- SH_PFC_PIN_GROUP(hscif3_data_d),
- SH_PFC_PIN_GROUP(hscif4_data_a),
- SH_PFC_PIN_GROUP(hscif4_clk),
- SH_PFC_PIN_GROUP(hscif4_ctrl),
- SH_PFC_PIN_GROUP(hscif4_data_b),
- SH_PFC_PIN_GROUP(i2c0),
- SH_PFC_PIN_GROUP(i2c1_a),
- SH_PFC_PIN_GROUP(i2c1_b),
- SH_PFC_PIN_GROUP(i2c2_a),
- SH_PFC_PIN_GROUP(i2c2_b),
- SH_PFC_PIN_GROUP(i2c3),
- SH_PFC_PIN_GROUP(i2c5),
- SH_PFC_PIN_GROUP(i2c6_a),
- SH_PFC_PIN_GROUP(i2c6_b),
- SH_PFC_PIN_GROUP(i2c6_c),
- SH_PFC_PIN_GROUP(intc_ex_irq0),
- SH_PFC_PIN_GROUP(intc_ex_irq1),
- SH_PFC_PIN_GROUP(intc_ex_irq2),
- SH_PFC_PIN_GROUP(intc_ex_irq3),
- SH_PFC_PIN_GROUP(intc_ex_irq4),
- SH_PFC_PIN_GROUP(intc_ex_irq5),
- SH_PFC_PIN_GROUP(msiof0_clk),
- SH_PFC_PIN_GROUP(msiof0_sync),
- SH_PFC_PIN_GROUP(msiof0_ss1),
- SH_PFC_PIN_GROUP(msiof0_ss2),
- SH_PFC_PIN_GROUP(msiof0_txd),
- SH_PFC_PIN_GROUP(msiof0_rxd),
- SH_PFC_PIN_GROUP(msiof1_clk_a),
- SH_PFC_PIN_GROUP(msiof1_sync_a),
- SH_PFC_PIN_GROUP(msiof1_ss1_a),
- SH_PFC_PIN_GROUP(msiof1_ss2_a),
- SH_PFC_PIN_GROUP(msiof1_txd_a),
- SH_PFC_PIN_GROUP(msiof1_rxd_a),
- SH_PFC_PIN_GROUP(msiof1_clk_b),
- SH_PFC_PIN_GROUP(msiof1_sync_b),
- SH_PFC_PIN_GROUP(msiof1_ss1_b),
- SH_PFC_PIN_GROUP(msiof1_ss2_b),
- SH_PFC_PIN_GROUP(msiof1_txd_b),
- SH_PFC_PIN_GROUP(msiof1_rxd_b),
- SH_PFC_PIN_GROUP(msiof1_clk_c),
- SH_PFC_PIN_GROUP(msiof1_sync_c),
- SH_PFC_PIN_GROUP(msiof1_ss1_c),
- SH_PFC_PIN_GROUP(msiof1_ss2_c),
- SH_PFC_PIN_GROUP(msiof1_txd_c),
- SH_PFC_PIN_GROUP(msiof1_rxd_c),
- SH_PFC_PIN_GROUP(msiof1_clk_d),
- SH_PFC_PIN_GROUP(msiof1_sync_d),
- SH_PFC_PIN_GROUP(msiof1_ss1_d),
- SH_PFC_PIN_GROUP(msiof1_ss2_d),
- SH_PFC_PIN_GROUP(msiof1_txd_d),
- SH_PFC_PIN_GROUP(msiof1_rxd_d),
- SH_PFC_PIN_GROUP(msiof1_clk_e),
- SH_PFC_PIN_GROUP(msiof1_sync_e),
- SH_PFC_PIN_GROUP(msiof1_ss1_e),
- SH_PFC_PIN_GROUP(msiof1_ss2_e),
- SH_PFC_PIN_GROUP(msiof1_txd_e),
- SH_PFC_PIN_GROUP(msiof1_rxd_e),
- SH_PFC_PIN_GROUP(msiof1_clk_f),
- SH_PFC_PIN_GROUP(msiof1_sync_f),
- SH_PFC_PIN_GROUP(msiof1_ss1_f),
- SH_PFC_PIN_GROUP(msiof1_ss2_f),
- SH_PFC_PIN_GROUP(msiof1_txd_f),
- SH_PFC_PIN_GROUP(msiof1_rxd_f),
- SH_PFC_PIN_GROUP(msiof1_clk_g),
- SH_PFC_PIN_GROUP(msiof1_sync_g),
- SH_PFC_PIN_GROUP(msiof1_ss1_g),
- SH_PFC_PIN_GROUP(msiof1_ss2_g),
- SH_PFC_PIN_GROUP(msiof1_txd_g),
- SH_PFC_PIN_GROUP(msiof1_rxd_g),
- SH_PFC_PIN_GROUP(msiof2_clk_a),
- SH_PFC_PIN_GROUP(msiof2_sync_a),
- SH_PFC_PIN_GROUP(msiof2_ss1_a),
- SH_PFC_PIN_GROUP(msiof2_ss2_a),
- SH_PFC_PIN_GROUP(msiof2_txd_a),
- SH_PFC_PIN_GROUP(msiof2_rxd_a),
- SH_PFC_PIN_GROUP(msiof2_clk_b),
- SH_PFC_PIN_GROUP(msiof2_sync_b),
- SH_PFC_PIN_GROUP(msiof2_ss1_b),
- SH_PFC_PIN_GROUP(msiof2_ss2_b),
- SH_PFC_PIN_GROUP(msiof2_txd_b),
- SH_PFC_PIN_GROUP(msiof2_rxd_b),
- SH_PFC_PIN_GROUP(msiof2_clk_c),
- SH_PFC_PIN_GROUP(msiof2_sync_c),
- SH_PFC_PIN_GROUP(msiof2_ss1_c),
- SH_PFC_PIN_GROUP(msiof2_ss2_c),
- SH_PFC_PIN_GROUP(msiof2_txd_c),
- SH_PFC_PIN_GROUP(msiof2_rxd_c),
- SH_PFC_PIN_GROUP(msiof2_clk_d),
- SH_PFC_PIN_GROUP(msiof2_sync_d),
- SH_PFC_PIN_GROUP(msiof2_ss1_d),
- SH_PFC_PIN_GROUP(msiof2_ss2_d),
- SH_PFC_PIN_GROUP(msiof2_txd_d),
- SH_PFC_PIN_GROUP(msiof2_rxd_d),
- SH_PFC_PIN_GROUP(msiof3_clk_a),
- SH_PFC_PIN_GROUP(msiof3_sync_a),
- SH_PFC_PIN_GROUP(msiof3_ss1_a),
- SH_PFC_PIN_GROUP(msiof3_ss2_a),
- SH_PFC_PIN_GROUP(msiof3_txd_a),
- SH_PFC_PIN_GROUP(msiof3_rxd_a),
- SH_PFC_PIN_GROUP(msiof3_clk_b),
- SH_PFC_PIN_GROUP(msiof3_sync_b),
- SH_PFC_PIN_GROUP(msiof3_ss1_b),
- SH_PFC_PIN_GROUP(msiof3_ss2_b),
- SH_PFC_PIN_GROUP(msiof3_txd_b),
- SH_PFC_PIN_GROUP(msiof3_rxd_b),
- SH_PFC_PIN_GROUP(msiof3_clk_c),
- SH_PFC_PIN_GROUP(msiof3_sync_c),
- SH_PFC_PIN_GROUP(msiof3_txd_c),
- SH_PFC_PIN_GROUP(msiof3_rxd_c),
- SH_PFC_PIN_GROUP(msiof3_clk_d),
- SH_PFC_PIN_GROUP(msiof3_sync_d),
- SH_PFC_PIN_GROUP(msiof3_ss1_d),
- SH_PFC_PIN_GROUP(msiof3_txd_d),
- SH_PFC_PIN_GROUP(msiof3_rxd_d),
- SH_PFC_PIN_GROUP(msiof3_clk_e),
- SH_PFC_PIN_GROUP(msiof3_sync_e),
- SH_PFC_PIN_GROUP(msiof3_ss1_e),
- SH_PFC_PIN_GROUP(msiof3_ss2_e),
- SH_PFC_PIN_GROUP(msiof3_txd_e),
- SH_PFC_PIN_GROUP(msiof3_rxd_e),
- SH_PFC_PIN_GROUP(pwm0),
- SH_PFC_PIN_GROUP(pwm1_a),
- SH_PFC_PIN_GROUP(pwm1_b),
- SH_PFC_PIN_GROUP(pwm2_a),
- SH_PFC_PIN_GROUP(pwm2_b),
- SH_PFC_PIN_GROUP(pwm3_a),
- SH_PFC_PIN_GROUP(pwm3_b),
- SH_PFC_PIN_GROUP(pwm4_a),
- SH_PFC_PIN_GROUP(pwm4_b),
- SH_PFC_PIN_GROUP(pwm5_a),
- SH_PFC_PIN_GROUP(pwm5_b),
- SH_PFC_PIN_GROUP(pwm6_a),
- SH_PFC_PIN_GROUP(pwm6_b),
- SH_PFC_PIN_GROUP(sata0_devslp_a),
- SH_PFC_PIN_GROUP(sata0_devslp_b),
- SH_PFC_PIN_GROUP(scif0_data),
- SH_PFC_PIN_GROUP(scif0_clk),
- SH_PFC_PIN_GROUP(scif0_ctrl),
- SH_PFC_PIN_GROUP(scif1_data_a),
- SH_PFC_PIN_GROUP(scif1_clk),
- SH_PFC_PIN_GROUP(scif1_ctrl),
- SH_PFC_PIN_GROUP(scif1_data_b),
- SH_PFC_PIN_GROUP(scif2_data_a),
- SH_PFC_PIN_GROUP(scif2_clk),
- SH_PFC_PIN_GROUP(scif2_data_b),
- SH_PFC_PIN_GROUP(scif3_data_a),
- SH_PFC_PIN_GROUP(scif3_clk),
- SH_PFC_PIN_GROUP(scif3_ctrl),
- SH_PFC_PIN_GROUP(scif3_data_b),
- SH_PFC_PIN_GROUP(scif4_data_a),
- SH_PFC_PIN_GROUP(scif4_clk_a),
- SH_PFC_PIN_GROUP(scif4_ctrl_a),
- SH_PFC_PIN_GROUP(scif4_data_b),
- SH_PFC_PIN_GROUP(scif4_clk_b),
- SH_PFC_PIN_GROUP(scif4_ctrl_b),
- SH_PFC_PIN_GROUP(scif4_data_c),
- SH_PFC_PIN_GROUP(scif4_clk_c),
- SH_PFC_PIN_GROUP(scif4_ctrl_c),
- SH_PFC_PIN_GROUP(scif5_data_a),
- SH_PFC_PIN_GROUP(scif5_clk_a),
- SH_PFC_PIN_GROUP(scif5_data_b),
- SH_PFC_PIN_GROUP(scif5_clk_b),
- SH_PFC_PIN_GROUP(scif_clk_a),
- SH_PFC_PIN_GROUP(scif_clk_b),
- SH_PFC_PIN_GROUP(sdhi0_data1),
- SH_PFC_PIN_GROUP(sdhi0_data4),
- SH_PFC_PIN_GROUP(sdhi0_ctrl),
- SH_PFC_PIN_GROUP(sdhi0_cd),
- SH_PFC_PIN_GROUP(sdhi0_wp),
- SH_PFC_PIN_GROUP(sdhi1_data1),
- SH_PFC_PIN_GROUP(sdhi1_data4),
- SH_PFC_PIN_GROUP(sdhi1_ctrl),
- SH_PFC_PIN_GROUP(sdhi1_cd),
- SH_PFC_PIN_GROUP(sdhi1_wp),
- SH_PFC_PIN_GROUP(sdhi2_data1),
- SH_PFC_PIN_GROUP(sdhi2_data4),
- SH_PFC_PIN_GROUP(sdhi2_data8),
- SH_PFC_PIN_GROUP(sdhi2_ctrl),
- SH_PFC_PIN_GROUP(sdhi2_cd_a),
- SH_PFC_PIN_GROUP(sdhi2_wp_a),
- SH_PFC_PIN_GROUP(sdhi2_cd_b),
- SH_PFC_PIN_GROUP(sdhi2_wp_b),
- SH_PFC_PIN_GROUP(sdhi2_ds),
- SH_PFC_PIN_GROUP(sdhi3_data1),
- SH_PFC_PIN_GROUP(sdhi3_data4),
- SH_PFC_PIN_GROUP(sdhi3_data8),
- SH_PFC_PIN_GROUP(sdhi3_ctrl),
- SH_PFC_PIN_GROUP(sdhi3_cd),
- SH_PFC_PIN_GROUP(sdhi3_wp),
- SH_PFC_PIN_GROUP(sdhi3_ds),
- SH_PFC_PIN_GROUP(ssi0_data),
- SH_PFC_PIN_GROUP(ssi01239_ctrl),
- SH_PFC_PIN_GROUP(ssi1_data_a),
- SH_PFC_PIN_GROUP(ssi1_data_b),
- SH_PFC_PIN_GROUP(ssi1_ctrl_a),
- SH_PFC_PIN_GROUP(ssi1_ctrl_b),
- SH_PFC_PIN_GROUP(ssi2_data_a),
- SH_PFC_PIN_GROUP(ssi2_data_b),
- SH_PFC_PIN_GROUP(ssi2_ctrl_a),
- SH_PFC_PIN_GROUP(ssi2_ctrl_b),
- SH_PFC_PIN_GROUP(ssi3_data),
- SH_PFC_PIN_GROUP(ssi349_ctrl),
- SH_PFC_PIN_GROUP(ssi4_data),
- SH_PFC_PIN_GROUP(ssi4_ctrl),
- SH_PFC_PIN_GROUP(ssi5_data),
- SH_PFC_PIN_GROUP(ssi5_ctrl),
- SH_PFC_PIN_GROUP(ssi6_data),
- SH_PFC_PIN_GROUP(ssi6_ctrl),
- SH_PFC_PIN_GROUP(ssi7_data),
- SH_PFC_PIN_GROUP(ssi78_ctrl),
- SH_PFC_PIN_GROUP(ssi8_data),
- SH_PFC_PIN_GROUP(ssi9_data_a),
- SH_PFC_PIN_GROUP(ssi9_data_b),
- SH_PFC_PIN_GROUP(ssi9_ctrl_a),
- SH_PFC_PIN_GROUP(ssi9_ctrl_b),
- SH_PFC_PIN_GROUP(tmu_tclk1_a),
- SH_PFC_PIN_GROUP(tmu_tclk1_b),
- SH_PFC_PIN_GROUP(tmu_tclk2_a),
- SH_PFC_PIN_GROUP(tmu_tclk2_b),
- SH_PFC_PIN_GROUP(tpu_to0),
- SH_PFC_PIN_GROUP(tpu_to1),
- SH_PFC_PIN_GROUP(tpu_to2),
- SH_PFC_PIN_GROUP(tpu_to3),
- SH_PFC_PIN_GROUP(usb0),
- SH_PFC_PIN_GROUP(usb1),
- SH_PFC_PIN_GROUP(usb2),
- SH_PFC_PIN_GROUP(usb2_ch3),
- SH_PFC_PIN_GROUP(usb30),
- VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
- SH_PFC_PIN_GROUP(vin4_data18_a),
- VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
- VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
- VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
- VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
- SH_PFC_PIN_GROUP(vin4_data18_b),
- VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
- VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
- SH_PFC_PIN_GROUP(vin4_sync),
- SH_PFC_PIN_GROUP(vin4_field),
- SH_PFC_PIN_GROUP(vin4_clkenb),
- SH_PFC_PIN_GROUP(vin4_clk),
- VIN_DATA_PIN_GROUP(vin5_data, 8),
- VIN_DATA_PIN_GROUP(vin5_data, 10),
- VIN_DATA_PIN_GROUP(vin5_data, 12),
- VIN_DATA_PIN_GROUP(vin5_data, 16),
- SH_PFC_PIN_GROUP(vin5_sync),
- SH_PFC_PIN_GROUP(vin5_field),
- SH_PFC_PIN_GROUP(vin5_clkenb),
- SH_PFC_PIN_GROUP(vin5_clk),
+static const struct {
+ struct sh_pfc_pin_group common[320];
+ struct sh_pfc_pin_group automotive[30];
+} pinmux_groups = {
+ .common = {
+ SH_PFC_PIN_GROUP(audio_clk_a_a),
+ SH_PFC_PIN_GROUP(audio_clk_a_b),
+ SH_PFC_PIN_GROUP(audio_clk_a_c),
+ SH_PFC_PIN_GROUP(audio_clk_b_a),
+ SH_PFC_PIN_GROUP(audio_clk_b_b),
+ SH_PFC_PIN_GROUP(audio_clk_c_a),
+ SH_PFC_PIN_GROUP(audio_clk_c_b),
+ SH_PFC_PIN_GROUP(audio_clkout_a),
+ SH_PFC_PIN_GROUP(audio_clkout_b),
+ SH_PFC_PIN_GROUP(audio_clkout_c),
+ SH_PFC_PIN_GROUP(audio_clkout_d),
+ SH_PFC_PIN_GROUP(audio_clkout1_a),
+ SH_PFC_PIN_GROUP(audio_clkout1_b),
+ SH_PFC_PIN_GROUP(audio_clkout2_a),
+ SH_PFC_PIN_GROUP(audio_clkout2_b),
+ SH_PFC_PIN_GROUP(audio_clkout3_a),
+ SH_PFC_PIN_GROUP(audio_clkout3_b),
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_avtp_pps),
+ SH_PFC_PIN_GROUP(avb_avtp_match_a),
+ SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+ SH_PFC_PIN_GROUP(avb_avtp_match_b),
+ SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+ SH_PFC_PIN_GROUP(can0_data_a),
+ SH_PFC_PIN_GROUP(can0_data_b),
+ SH_PFC_PIN_GROUP(can1_data),
+ SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(canfd0_data_a),
+ SH_PFC_PIN_GROUP(canfd0_data_b),
+ SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_clk_out_1),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_oddf),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data_a),
+ SH_PFC_PIN_GROUP(hscif1_clk_a),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_a),
+ SH_PFC_PIN_GROUP(hscif1_data_b),
+ SH_PFC_PIN_GROUP(hscif1_clk_b),
+ SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif2_data_a),
+ SH_PFC_PIN_GROUP(hscif2_clk_a),
+ SH_PFC_PIN_GROUP(hscif2_ctrl_a),
+ SH_PFC_PIN_GROUP(hscif2_data_b),
+ SH_PFC_PIN_GROUP(hscif2_clk_b),
+ SH_PFC_PIN_GROUP(hscif2_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif2_data_c),
+ SH_PFC_PIN_GROUP(hscif2_clk_c),
+ SH_PFC_PIN_GROUP(hscif2_ctrl_c),
+ SH_PFC_PIN_GROUP(hscif3_data_a),
+ SH_PFC_PIN_GROUP(hscif3_clk),
+ SH_PFC_PIN_GROUP(hscif3_ctrl),
+ SH_PFC_PIN_GROUP(hscif3_data_b),
+ SH_PFC_PIN_GROUP(hscif3_data_c),
+ SH_PFC_PIN_GROUP(hscif3_data_d),
+ SH_PFC_PIN_GROUP(hscif4_data_a),
+ SH_PFC_PIN_GROUP(hscif4_clk),
+ SH_PFC_PIN_GROUP(hscif4_ctrl),
+ SH_PFC_PIN_GROUP(hscif4_data_b),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1_a),
+ SH_PFC_PIN_GROUP(i2c1_b),
+ SH_PFC_PIN_GROUP(i2c2_a),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c5),
+ SH_PFC_PIN_GROUP(i2c6_a),
+ SH_PFC_PIN_GROUP(i2c6_b),
+ SH_PFC_PIN_GROUP(i2c6_c),
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_txd),
+ SH_PFC_PIN_GROUP(msiof0_rxd),
+ SH_PFC_PIN_GROUP(msiof1_clk_a),
+ SH_PFC_PIN_GROUP(msiof1_sync_a),
+ SH_PFC_PIN_GROUP(msiof1_ss1_a),
+ SH_PFC_PIN_GROUP(msiof1_ss2_a),
+ SH_PFC_PIN_GROUP(msiof1_txd_a),
+ SH_PFC_PIN_GROUP(msiof1_rxd_a),
+ SH_PFC_PIN_GROUP(msiof1_clk_b),
+ SH_PFC_PIN_GROUP(msiof1_sync_b),
+ SH_PFC_PIN_GROUP(msiof1_ss1_b),
+ SH_PFC_PIN_GROUP(msiof1_ss2_b),
+ SH_PFC_PIN_GROUP(msiof1_txd_b),
+ SH_PFC_PIN_GROUP(msiof1_rxd_b),
+ SH_PFC_PIN_GROUP(msiof1_clk_c),
+ SH_PFC_PIN_GROUP(msiof1_sync_c),
+ SH_PFC_PIN_GROUP(msiof1_ss1_c),
+ SH_PFC_PIN_GROUP(msiof1_ss2_c),
+ SH_PFC_PIN_GROUP(msiof1_txd_c),
+ SH_PFC_PIN_GROUP(msiof1_rxd_c),
+ SH_PFC_PIN_GROUP(msiof1_clk_d),
+ SH_PFC_PIN_GROUP(msiof1_sync_d),
+ SH_PFC_PIN_GROUP(msiof1_ss1_d),
+ SH_PFC_PIN_GROUP(msiof1_ss2_d),
+ SH_PFC_PIN_GROUP(msiof1_txd_d),
+ SH_PFC_PIN_GROUP(msiof1_rxd_d),
+ SH_PFC_PIN_GROUP(msiof1_clk_e),
+ SH_PFC_PIN_GROUP(msiof1_sync_e),
+ SH_PFC_PIN_GROUP(msiof1_ss1_e),
+ SH_PFC_PIN_GROUP(msiof1_ss2_e),
+ SH_PFC_PIN_GROUP(msiof1_txd_e),
+ SH_PFC_PIN_GROUP(msiof1_rxd_e),
+ SH_PFC_PIN_GROUP(msiof1_clk_f),
+ SH_PFC_PIN_GROUP(msiof1_sync_f),
+ SH_PFC_PIN_GROUP(msiof1_ss1_f),
+ SH_PFC_PIN_GROUP(msiof1_ss2_f),
+ SH_PFC_PIN_GROUP(msiof1_txd_f),
+ SH_PFC_PIN_GROUP(msiof1_rxd_f),
+ SH_PFC_PIN_GROUP(msiof1_clk_g),
+ SH_PFC_PIN_GROUP(msiof1_sync_g),
+ SH_PFC_PIN_GROUP(msiof1_ss1_g),
+ SH_PFC_PIN_GROUP(msiof1_ss2_g),
+ SH_PFC_PIN_GROUP(msiof1_txd_g),
+ SH_PFC_PIN_GROUP(msiof1_rxd_g),
+ SH_PFC_PIN_GROUP(msiof2_clk_a),
+ SH_PFC_PIN_GROUP(msiof2_sync_a),
+ SH_PFC_PIN_GROUP(msiof2_ss1_a),
+ SH_PFC_PIN_GROUP(msiof2_ss2_a),
+ SH_PFC_PIN_GROUP(msiof2_txd_a),
+ SH_PFC_PIN_GROUP(msiof2_rxd_a),
+ SH_PFC_PIN_GROUP(msiof2_clk_b),
+ SH_PFC_PIN_GROUP(msiof2_sync_b),
+ SH_PFC_PIN_GROUP(msiof2_ss1_b),
+ SH_PFC_PIN_GROUP(msiof2_ss2_b),
+ SH_PFC_PIN_GROUP(msiof2_txd_b),
+ SH_PFC_PIN_GROUP(msiof2_rxd_b),
+ SH_PFC_PIN_GROUP(msiof2_clk_c),
+ SH_PFC_PIN_GROUP(msiof2_sync_c),
+ SH_PFC_PIN_GROUP(msiof2_ss1_c),
+ SH_PFC_PIN_GROUP(msiof2_ss2_c),
+ SH_PFC_PIN_GROUP(msiof2_txd_c),
+ SH_PFC_PIN_GROUP(msiof2_rxd_c),
+ SH_PFC_PIN_GROUP(msiof2_clk_d),
+ SH_PFC_PIN_GROUP(msiof2_sync_d),
+ SH_PFC_PIN_GROUP(msiof2_ss1_d),
+ SH_PFC_PIN_GROUP(msiof2_ss2_d),
+ SH_PFC_PIN_GROUP(msiof2_txd_d),
+ SH_PFC_PIN_GROUP(msiof2_rxd_d),
+ SH_PFC_PIN_GROUP(msiof3_clk_a),
+ SH_PFC_PIN_GROUP(msiof3_sync_a),
+ SH_PFC_PIN_GROUP(msiof3_ss1_a),
+ SH_PFC_PIN_GROUP(msiof3_ss2_a),
+ SH_PFC_PIN_GROUP(msiof3_txd_a),
+ SH_PFC_PIN_GROUP(msiof3_rxd_a),
+ SH_PFC_PIN_GROUP(msiof3_clk_b),
+ SH_PFC_PIN_GROUP(msiof3_sync_b),
+ SH_PFC_PIN_GROUP(msiof3_ss1_b),
+ SH_PFC_PIN_GROUP(msiof3_ss2_b),
+ SH_PFC_PIN_GROUP(msiof3_txd_b),
+ SH_PFC_PIN_GROUP(msiof3_rxd_b),
+ SH_PFC_PIN_GROUP(msiof3_clk_c),
+ SH_PFC_PIN_GROUP(msiof3_sync_c),
+ SH_PFC_PIN_GROUP(msiof3_txd_c),
+ SH_PFC_PIN_GROUP(msiof3_rxd_c),
+ SH_PFC_PIN_GROUP(msiof3_clk_d),
+ SH_PFC_PIN_GROUP(msiof3_sync_d),
+ SH_PFC_PIN_GROUP(msiof3_ss1_d),
+ SH_PFC_PIN_GROUP(msiof3_txd_d),
+ SH_PFC_PIN_GROUP(msiof3_rxd_d),
+ SH_PFC_PIN_GROUP(msiof3_clk_e),
+ SH_PFC_PIN_GROUP(msiof3_sync_e),
+ SH_PFC_PIN_GROUP(msiof3_ss1_e),
+ SH_PFC_PIN_GROUP(msiof3_ss2_e),
+ SH_PFC_PIN_GROUP(msiof3_txd_e),
+ SH_PFC_PIN_GROUP(msiof3_rxd_e),
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm1_a),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2_a),
+ SH_PFC_PIN_GROUP(pwm2_b),
+ SH_PFC_PIN_GROUP(pwm3_a),
+ SH_PFC_PIN_GROUP(pwm3_b),
+ SH_PFC_PIN_GROUP(pwm4_a),
+ SH_PFC_PIN_GROUP(pwm4_b),
+ SH_PFC_PIN_GROUP(pwm5_a),
+ SH_PFC_PIN_GROUP(pwm5_b),
+ SH_PFC_PIN_GROUP(pwm6_a),
+ SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(sata0_devslp_a),
+ SH_PFC_PIN_GROUP(sata0_devslp_b),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif2_data_a),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scif3_data_a),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif4_data_a),
+ SH_PFC_PIN_GROUP(scif4_clk_a),
+ SH_PFC_PIN_GROUP(scif4_ctrl_a),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_clk_b),
+ SH_PFC_PIN_GROUP(scif4_ctrl_b),
+ SH_PFC_PIN_GROUP(scif4_data_c),
+ SH_PFC_PIN_GROUP(scif4_clk_c),
+ SH_PFC_PIN_GROUP(scif4_ctrl_c),
+ SH_PFC_PIN_GROUP(scif5_data_a),
+ SH_PFC_PIN_GROUP(scif5_clk_a),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scif5_clk_b),
+ SH_PFC_PIN_GROUP(scif_clk_a),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_data8),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd_a),
+ SH_PFC_PIN_GROUP(sdhi2_wp_a),
+ SH_PFC_PIN_GROUP(sdhi2_cd_b),
+ SH_PFC_PIN_GROUP(sdhi2_wp_b),
+ SH_PFC_PIN_GROUP(sdhi2_ds),
+ SH_PFC_PIN_GROUP(sdhi3_data1),
+ SH_PFC_PIN_GROUP(sdhi3_data4),
+ SH_PFC_PIN_GROUP(sdhi3_data8),
+ SH_PFC_PIN_GROUP(sdhi3_ctrl),
+ SH_PFC_PIN_GROUP(sdhi3_cd),
+ SH_PFC_PIN_GROUP(sdhi3_wp),
+ SH_PFC_PIN_GROUP(sdhi3_ds),
+ SH_PFC_PIN_GROUP(ssi0_data),
+ SH_PFC_PIN_GROUP(ssi01239_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data_a),
+ SH_PFC_PIN_GROUP(ssi1_data_b),
+ SH_PFC_PIN_GROUP(ssi1_ctrl_a),
+ SH_PFC_PIN_GROUP(ssi1_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi2_data_a),
+ SH_PFC_PIN_GROUP(ssi2_data_b),
+ SH_PFC_PIN_GROUP(ssi2_ctrl_a),
+ SH_PFC_PIN_GROUP(ssi2_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi3_data),
+ SH_PFC_PIN_GROUP(ssi349_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data),
+ SH_PFC_PIN_GROUP(ssi4_ctrl),
+ SH_PFC_PIN_GROUP(ssi5_data),
+ SH_PFC_PIN_GROUP(ssi5_ctrl),
+ SH_PFC_PIN_GROUP(ssi6_data),
+ SH_PFC_PIN_GROUP(ssi6_ctrl),
+ SH_PFC_PIN_GROUP(ssi7_data),
+ SH_PFC_PIN_GROUP(ssi78_ctrl),
+ SH_PFC_PIN_GROUP(ssi8_data),
+ SH_PFC_PIN_GROUP(ssi9_data_a),
+ SH_PFC_PIN_GROUP(ssi9_data_b),
+ SH_PFC_PIN_GROUP(ssi9_ctrl_a),
+ SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb1),
+ SH_PFC_PIN_GROUP(usb2),
+ SH_PFC_PIN_GROUP(usb2_ch3),
+ SH_PFC_PIN_GROUP(usb30),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
+ SH_PFC_PIN_GROUP(vin4_data18_a),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
+ SH_PFC_PIN_GROUP(vin4_data18_b),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
+ SH_PFC_PIN_GROUP(vin4_sync),
+ SH_PFC_PIN_GROUP(vin4_field),
+ SH_PFC_PIN_GROUP(vin4_clkenb),
+ SH_PFC_PIN_GROUP(vin4_clk),
+ VIN_DATA_PIN_GROUP(vin5_data, 8),
+ VIN_DATA_PIN_GROUP(vin5_data, 10),
+ VIN_DATA_PIN_GROUP(vin5_data, 12),
+ VIN_DATA_PIN_GROUP(vin5_data, 16),
+ SH_PFC_PIN_GROUP(vin5_sync),
+ SH_PFC_PIN_GROUP(vin5_field),
+ SH_PFC_PIN_GROUP(vin5_clkenb),
+ SH_PFC_PIN_GROUP(vin5_clk),
+ },
+ .automotive = {
+ SH_PFC_PIN_GROUP(drif0_ctrl_a),
+ SH_PFC_PIN_GROUP(drif0_data0_a),
+ SH_PFC_PIN_GROUP(drif0_data1_a),
+ SH_PFC_PIN_GROUP(drif0_ctrl_b),
+ SH_PFC_PIN_GROUP(drif0_data0_b),
+ SH_PFC_PIN_GROUP(drif0_data1_b),
+ SH_PFC_PIN_GROUP(drif0_ctrl_c),
+ SH_PFC_PIN_GROUP(drif0_data0_c),
+ SH_PFC_PIN_GROUP(drif0_data1_c),
+ SH_PFC_PIN_GROUP(drif1_ctrl_a),
+ SH_PFC_PIN_GROUP(drif1_data0_a),
+ SH_PFC_PIN_GROUP(drif1_data1_a),
+ SH_PFC_PIN_GROUP(drif1_ctrl_b),
+ SH_PFC_PIN_GROUP(drif1_data0_b),
+ SH_PFC_PIN_GROUP(drif1_data1_b),
+ SH_PFC_PIN_GROUP(drif1_ctrl_c),
+ SH_PFC_PIN_GROUP(drif1_data0_c),
+ SH_PFC_PIN_GROUP(drif1_data1_c),
+ SH_PFC_PIN_GROUP(drif2_ctrl_a),
+ SH_PFC_PIN_GROUP(drif2_data0_a),
+ SH_PFC_PIN_GROUP(drif2_data1_a),
+ SH_PFC_PIN_GROUP(drif2_ctrl_b),
+ SH_PFC_PIN_GROUP(drif2_data0_b),
+ SH_PFC_PIN_GROUP(drif2_data1_b),
+ SH_PFC_PIN_GROUP(drif3_ctrl_a),
+ SH_PFC_PIN_GROUP(drif3_data0_a),
+ SH_PFC_PIN_GROUP(drif3_data1_a),
+ SH_PFC_PIN_GROUP(drif3_ctrl_b),
+ SH_PFC_PIN_GROUP(drif3_data0_b),
+ SH_PFC_PIN_GROUP(drif3_data1_b),
+ }
+
};
static const char * const audio_clk_groups[] = {
"vin5_clk",
};
-static const struct sh_pfc_function pinmux_functions[] = {
- SH_PFC_FUNCTION(audio_clk),
- SH_PFC_FUNCTION(avb),
- SH_PFC_FUNCTION(can0),
- SH_PFC_FUNCTION(can1),
- SH_PFC_FUNCTION(can_clk),
- SH_PFC_FUNCTION(canfd0),
- SH_PFC_FUNCTION(canfd1),
- SH_PFC_FUNCTION(drif0),
- SH_PFC_FUNCTION(drif1),
- SH_PFC_FUNCTION(drif2),
- SH_PFC_FUNCTION(drif3),
- SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(hscif0),
- SH_PFC_FUNCTION(hscif1),
- SH_PFC_FUNCTION(hscif2),
- SH_PFC_FUNCTION(hscif3),
- SH_PFC_FUNCTION(hscif4),
- SH_PFC_FUNCTION(i2c0),
- SH_PFC_FUNCTION(i2c1),
- SH_PFC_FUNCTION(i2c2),
- SH_PFC_FUNCTION(i2c3),
- SH_PFC_FUNCTION(i2c5),
- SH_PFC_FUNCTION(i2c6),
- SH_PFC_FUNCTION(intc_ex),
- SH_PFC_FUNCTION(msiof0),
- SH_PFC_FUNCTION(msiof1),
- SH_PFC_FUNCTION(msiof2),
- SH_PFC_FUNCTION(msiof3),
- SH_PFC_FUNCTION(pwm0),
- SH_PFC_FUNCTION(pwm1),
- SH_PFC_FUNCTION(pwm2),
- SH_PFC_FUNCTION(pwm3),
- SH_PFC_FUNCTION(pwm4),
- SH_PFC_FUNCTION(pwm5),
- SH_PFC_FUNCTION(pwm6),
- SH_PFC_FUNCTION(sata0),
- SH_PFC_FUNCTION(scif0),
- SH_PFC_FUNCTION(scif1),
- SH_PFC_FUNCTION(scif2),
- SH_PFC_FUNCTION(scif3),
- SH_PFC_FUNCTION(scif4),
- SH_PFC_FUNCTION(scif5),
- SH_PFC_FUNCTION(scif_clk),
- SH_PFC_FUNCTION(sdhi0),
- SH_PFC_FUNCTION(sdhi1),
- SH_PFC_FUNCTION(sdhi2),
- SH_PFC_FUNCTION(sdhi3),
- SH_PFC_FUNCTION(ssi),
- SH_PFC_FUNCTION(tmu),
- SH_PFC_FUNCTION(tpu),
- SH_PFC_FUNCTION(usb0),
- SH_PFC_FUNCTION(usb1),
- SH_PFC_FUNCTION(usb2),
- SH_PFC_FUNCTION(usb2_ch3),
- SH_PFC_FUNCTION(usb30),
- SH_PFC_FUNCTION(vin4),
- SH_PFC_FUNCTION(vin5),
+static const struct {
+ struct sh_pfc_function common[53];
+ struct sh_pfc_function automotive[4];
+} pinmux_functions = {
+ .common = {
+ SH_PFC_FUNCTION(audio_clk),
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(can0),
+ SH_PFC_FUNCTION(can1),
+ SH_PFC_FUNCTION(can_clk),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(hscif3),
+ SH_PFC_FUNCTION(hscif4),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c5),
+ SH_PFC_FUNCTION(i2c6),
+ SH_PFC_FUNCTION(intc_ex),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(pwm5),
+ SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(sata0),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(sdhi3),
+ SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(tmu),
+ SH_PFC_FUNCTION(tpu),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(usb2),
+ SH_PFC_FUNCTION(usb2_ch3),
+ SH_PFC_FUNCTION(usb30),
+ SH_PFC_FUNCTION(vin4),
+ SH_PFC_FUNCTION(vin5),
+ },
+ .automotive = {
+ SH_PFC_FUNCTION(drif0),
+ SH_PFC_FUNCTION(drif1),
+ SH_PFC_FUNCTION(drif2),
+ SH_PFC_FUNCTION(drif3),
+ }
+
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
+#endif
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
{ PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
{ PIN_TMS, 4, 2 }, /* TMS */
{ RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
{ RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
{ RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
- { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
- { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
+ { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
+ { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
} },
{ },
};
.set_bias = r8a77951_pinmux_set_bias,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A774E1
+const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
+ .name = "r8a774e1_pfc",
+ .ops = &r8a77951_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common),
+
+ .cfg_regs = pinmux_config_regs,
+ .drive_regs = pinmux_drive_regs,
+ .bias_regs = pinmux_bias_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
const struct sh_pfc_soc_info r8a77951_pinmux_info = {
.name = "r8a77951_pfc",
.ops = &r8a77951_pinmux_ops,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
- .groups = pinmux_groups,
- .nr_groups = ARRAY_SIZE(pinmux_groups),
- .functions = pinmux_functions,
- .nr_functions = ARRAY_SIZE(pinmux_functions),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+ ARRAY_SIZE(pinmux_groups.automotive),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+ ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
+#endif
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
+/* - RPC -------------------------------------------------------------------- */
+static const unsigned int rpc_clk1_pins[] = {
+ /* Octal-SPI flash: C/SCLK */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int rpc_clk1_mux[] = {
+ QSPI0_SPCLK_MARK,
+};
+static const unsigned int rpc_clk2_pins[] = {
+ /* HyperFlash: CK, CK# */
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int rpc_clk2_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
+};
+static const unsigned int rpc_ctrl_pins[] = {
+ /* Octal-SPI flash: S#/CS, DQS */
+ /* HyperFlash: CS#, RDS */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
+};
+static const unsigned int rpc_ctrl_mux[] = {
+ QSPI0_SSL_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int rpc_data_pins[] = {
+ /* DQ[0:7] */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
+ RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+ RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int rpc_data_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+static const unsigned int rpc_reset_pins[] = {
+ /* RPC_RESET# */
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int rpc_reset_mux[] = {
+ RPC_RESET_N_MARK,
+};
+static const unsigned int rpc_int_pins[] = {
+ /* RPC_INT# */
+ RCAR_GP_PIN(5, 14),
+};
+static const unsigned int rpc_int_mux[] = {
+ RPC_INT_N_MARK,
+};
+static const unsigned int rpc_wp_pins[] = {
+ /* RPC_WP# */
+ RCAR_GP_PIN(5, 13),
+};
+static const unsigned int rpc_wp_mux[] = {
+ RPC_WP_N_MARK,
+};
+
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_a_pins[] = {
/* SCIF_CLK */
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
+ SH_PFC_PIN_GROUP(rpc_clk1),
+ SH_PFC_PIN_GROUP(rpc_clk2),
+ SH_PFC_PIN_GROUP(rpc_ctrl),
+ SH_PFC_PIN_GROUP(rpc_data),
+ SH_PFC_PIN_GROUP(rpc_reset),
+ SH_PFC_PIN_GROUP(rpc_int),
+ SH_PFC_PIN_GROUP(rpc_wp),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(scif0_data),
"qspi1_data4",
};
+static const char * const rpc_groups[] = {
+ "rpc_clk1",
+ "rpc_clk2",
+ "rpc_ctrl",
+ "rpc_data",
+ "rpc_reset",
+ "rpc_int",
+ "rpc_wp",
+};
+
static const char * const scif_clk_groups[] = {
"scif_clk_a",
"scif_clk_b",
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
+ SH_PFC_FUNCTION(rpc),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
+/* - RPC -------------------------------------------------------------------- */
+static const unsigned int rpc_clk1_pins[] = {
+ /* Octal-SPI flash: C/SCLK */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int rpc_clk1_mux[] = {
+ QSPI0_SPCLK_MARK,
+};
+static const unsigned int rpc_clk2_pins[] = {
+ /* HyperFlash: CK, CK# */
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int rpc_clk2_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
+};
+static const unsigned int rpc_ctrl_pins[] = {
+ /* Octal-SPI flash: S#/CS, DQS */
+ /* HyperFlash: CS#, RDS */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
+};
+static const unsigned int rpc_ctrl_mux[] = {
+ QSPI0_SSL_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int rpc_data_pins[] = {
+ /* DQ[0:7] */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
+ RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+ RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int rpc_data_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+static const unsigned int rpc_reset_pins[] = {
+ /* RPC_RESET# */
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int rpc_reset_mux[] = {
+ RPC_RESET_N_MARK,
+};
+static const unsigned int rpc_int_pins[] = {
+ /* RPC_INT# */
+ RCAR_GP_PIN(5, 14),
+};
+static const unsigned int rpc_int_mux[] = {
+ RPC_INT_N_MARK,
+};
+static const unsigned int rpc_wp_pins[] = {
+ /* RPC_WP# */
+ RCAR_GP_PIN(5, 13),
+};
+static const unsigned int rpc_wp_mux[] = {
+ RPC_WP_N_MARK,
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
+ SH_PFC_PIN_GROUP(rpc_clk1),
+ SH_PFC_PIN_GROUP(rpc_clk2),
+ SH_PFC_PIN_GROUP(rpc_ctrl),
+ SH_PFC_PIN_GROUP(rpc_data),
+ SH_PFC_PIN_GROUP(rpc_reset),
+ SH_PFC_PIN_GROUP(rpc_int),
+ SH_PFC_PIN_GROUP(rpc_wp),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
"qspi1_data4",
};
+static const char * const rpc_groups[] = {
+ "rpc_clk1",
+ "rpc_clk2",
+ "rpc_ctrl",
+ "rpc_data",
+ "rpc_reset",
+ "rpc_int",
+ "rpc_wp",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
+ SH_PFC_FUNCTION(rpc),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
+extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
/**
* struct atlas7_pad_conf - Atlas7 Pad Configuration
- * @id The ID of this Pad.
+ * @id: The ID of this Pad.
* @type: The type of this Pad.
* @mux_reg: The mux register offset.
* This register contains the mux.
.ad_ctrl_bit = adb, \
}
-/**
+/*
* struct atlas7_pad_status - Atlas7 Pad status
*/
struct atlas7_pad_status {
struct atlas7_gpio_bank banks[];
};
-/**
- * @dev: a pointer back to containing device
- * @virtbase: the offset to the controller in virtual memory
- */
struct atlas7_pmx {
struct device *dev;
struct pinctrl_dev *pctl;
* refer to A7DA IO Summary - CS-314158-DD-4E.xls
*/
-/*Pads in IOC RTC & TOP */
+/* Pads in IOC RTC & TOP */
static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
/* RTC PADs */
PINCTRL_PIN(0, "rtc_gpio_0"),
/**
* struct atlas7_pull_info - Atlas7 Pad pull info
- * @type:The type of this Pad.
- * @mask:The mas value of this pin's pull bits.
- * @v2s: The map of pull register value to pull status.
- * @s2v: The map of pull status to pull register value.
+ * @pad_type: The type of this Pad.
+ * @mask: The mas value of this pin's pull bits.
+ * @v2s: The map of pull register value to pull status.
+ * @s2v: The map of pull status to pull register value.
*/
struct atlas7_pull_info {
u8 pad_type;
* @type: The type of this Pad.
* @mask: The mask value of this pin's pull bits.
* @imval: The immediate value of drives trength register.
+ * @reserved: Reserved space
*/
struct atlas7_ds_info {
u8 type;
arch_initcall(atlas7_pinmux_init);
-/**
+/*
* The Following is GPIO Code
*/
static inline struct
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
-#define HWSPINLOCK_TIMEOUT 5 /* msec */
+#define HWSPNLCK_TIMEOUT 1000 /* usec */
static const char * const stm32_gpio_functions[] = {
"gpio", "af0", "af1",
struct stm32_gpio_bank {
void __iomem *base;
struct clk *clk;
+ struct reset_control *rstc;
spinlock_t lock;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range range;
.direction_output = stm32_gpio_direction_output,
.to_irq = stm32_gpio_to_irq,
.get_direction = stm32_gpio_get_direction,
+ .set_config = gpiochip_generic_config,
};
static void stm32_gpio_irq_trigger(struct irq_data *d)
* to avoid overriding.
*/
spin_lock_irqsave(&pctl->irqmux_lock, flags);
- if (pctl->hwlock)
- ret = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
- if (ret) {
- dev_err(pctl->dev, "Can't get hwspinlock\n");
- goto unlock;
+ if (pctl->hwlock) {
+ ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
+ HWSPNLCK_TIMEOUT);
+ if (ret) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
}
if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
irq_data->hwirq);
ret = -EBUSY;
if (pctl->hwlock)
- hwspin_unlock(pctl->hwlock);
+ hwspin_unlock_in_atomic(pctl->hwlock);
goto unlock;
} else {
pctl->irqmux_map |= BIT(irq_data->hwirq);
regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
if (pctl->hwlock)
- hwspin_unlock(pctl->hwlock);
+ hwspin_unlock_in_atomic(pctl->hwlock);
unlock:
spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
- if (pctl->hwlock)
- err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
-
- if (err) {
- dev_err(pctl->dev, "Can't get hwspinlock\n");
- goto unlock;
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
+ HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
}
val = readl_relaxed(bank->base + alt_offset);
writel_relaxed(val, bank->base + STM32_GPIO_MODER);
if (pctl->hwlock)
- hwspin_unlock(pctl->hwlock);
+ hwspin_unlock_in_atomic(pctl->hwlock);
stm32_gpio_backup_mode(bank, pin, mode, alt);
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
- if (pctl->hwlock)
- err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
-
- if (err) {
- dev_err(pctl->dev, "Can't get hwspinlock\n");
- goto unlock;
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
+ HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
}
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
if (pctl->hwlock)
- hwspin_unlock(pctl->hwlock);
+ hwspin_unlock_in_atomic(pctl->hwlock);
stm32_gpio_backup_driving(bank, offset, drive);
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
- if (pctl->hwlock)
- err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
-
- if (err) {
- dev_err(pctl->dev, "Can't get hwspinlock\n");
- goto unlock;
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
+ HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
}
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
if (pctl->hwlock)
- hwspin_unlock(pctl->hwlock);
+ hwspin_unlock_in_atomic(pctl->hwlock);
stm32_gpio_backup_speed(bank, offset, speed);
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
- if (pctl->hwlock)
- err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
-
- if (err) {
- dev_err(pctl->dev, "Can't get hwspinlock\n");
- goto unlock;
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
+ HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
}
val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
if (pctl->hwlock)
- hwspin_unlock(pctl->hwlock);
+ hwspin_unlock_in_atomic(pctl->hwlock);
stm32_gpio_backup_bias(bank, offset, bias);
struct stm32_gpio_bank *bank;
int offset, ret = 0;
- range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
+ range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
if (!range) {
dev_err(pctl->dev, "No gpio range defined.\n");
return -EINVAL;
ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
break;
default:
- ret = -EINVAL;
+ ret = -ENOTSUPP;
}
return ret;
int i, ret;
for (i = 0; i < num_configs; i++) {
+ mutex_lock(&pctldev->mutex);
ret = stm32_pconf_parse_conf(pctldev, g->pin,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
+ mutex_unlock(&pctldev->mutex);
if (ret < 0)
return ret;
return 0;
}
+static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ int i, ret;
+
+ for (i = 0; i < num_configs; i++) {
+ ret = stm32_pconf_parse_conf(pctldev, pin,
+ pinconf_to_config_param(configs[i]),
+ pinconf_to_config_argument(configs[i]));
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned int pin)
}
}
-
static const struct pinconf_ops stm32_pconf_ops = {
.pin_config_group_get = stm32_pconf_group_get,
.pin_config_group_set = stm32_pconf_group_set,
+ .pin_config_set = stm32_pconf_set,
.pin_config_dbg_show = stm32_pconf_dbg_show,
};
struct of_phandle_args args;
struct device *dev = pctl->dev;
struct resource res;
- struct reset_control *rstc;
int npins = STM32_GPIO_PINS_PER_BANK;
int bank_nr, err;
- rstc = of_reset_control_get_exclusive(np, NULL);
- if (!IS_ERR(rstc))
- reset_control_deassert(rstc);
+ if (!IS_ERR(bank->rstc))
+ reset_control_deassert(bank->rstc);
if (of_address_to_resource(np, 0, &res))
return -ENODEV;
if (IS_ERR(bank->base))
return PTR_ERR(bank->base);
- bank->clk = of_clk_get_by_name(np, NULL);
- if (IS_ERR(bank->clk)) {
- dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
- return PTR_ERR(bank->clk);
- }
-
err = clk_prepare(bank->clk);
if (err) {
dev_err(dev, "failed to prepare clk (%d)\n", err);
if (!pctl->banks)
return -ENOMEM;
+ i = 0;
+ for_each_available_child_of_node(np, child) {
+ struct stm32_gpio_bank *bank = &pctl->banks[i];
+
+ if (of_property_read_bool(child, "gpio-controller")) {
+ bank->rstc = of_reset_control_get_exclusive(child,
+ NULL);
+ if (PTR_ERR(bank->rstc) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ bank->clk = of_clk_get_by_name(child, NULL);
+ if (IS_ERR(bank->clk)) {
+ if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
+ dev_err(dev,
+ "failed to get clk (%ld)\n",
+ PTR_ERR(bank->clk));
+ return PTR_ERR(bank->clk);
+ }
+ i++;
+ }
+ }
+
for_each_available_child_of_node(np, child) {
if (of_property_read_bool(child, "gpio-controller")) {
ret = stm32_gpiolib_register_bank(pctl, child);
.sfsel_bit = 10, \
.schmitt_bit = schmitt_b, \
.drvtype_bit = 13, \
- .drv_reg = -1, \
.parked_bitmask = 0
#define drive_pex_l5_clkreq_n_pgg0 \
* Support for configuration of IO Delay module found on Texas Instruments SoCs
* such as DRA7
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Andy Teng <andy.teng@mediatek.com>
+ *
+ */
+
+#ifndef __MT6779_PINFUNC_H
+#define __MT6779_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1)
+#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2)
+#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3)
+#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4)
+#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5)
+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6)
+#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7)
+
+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1)
+#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2)
+#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3)
+#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4)
+#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5)
+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6)
+#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7)
+
+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1)
+#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2)
+#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3)
+#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4)
+#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5)
+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6)
+
+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1)
+#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2)
+#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3)
+#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4)
+#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5)
+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6)
+
+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1)
+#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2)
+#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3)
+#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4)
+#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5)
+#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
+#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7)
+
+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1)
+#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2)
+#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3)
+#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4)
+#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5)
+#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
+#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7)
+
+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1)
+#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2)
+#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3)
+#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4)
+#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5)
+#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
+#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7)
+
+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1)
+#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2)
+#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3)
+#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4)
+#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5)
+#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
+#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7)
+
+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1)
+#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2)
+#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3)
+#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4)
+#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5)
+#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6)
+#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7)
+
+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1)
+#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9) | 2)
+#define PINMUX_GPIO9__FUNC_SRCLKENAI1 (MTK_PIN_NO(9) | 3)
+#define PINMUX_GPIO9__FUNC_UTXD1 (MTK_PIN_NO(9) | 4)
+#define PINMUX_GPIO9__FUNC_I2S0_BCK (MTK_PIN_NO(9) | 5)
+#define PINMUX_GPIO9__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(9) | 6)
+#define PINMUX_GPIO9__FUNC_USB_DRVVBUS (MTK_PIN_NO(9) | 7)
+
+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define PINMUX_GPIO10__FUNC_MSDC1_CLK_A (MTK_PIN_NO(10) | 1)
+#define PINMUX_GPIO10__FUNC_TP_URXD1_AO (MTK_PIN_NO(10) | 2)
+#define PINMUX_GPIO10__FUNC_I2S1_LRCK (MTK_PIN_NO(10) | 3)
+#define PINMUX_GPIO10__FUNC_UCTS0 (MTK_PIN_NO(10) | 4)
+#define PINMUX_GPIO10__FUNC_DMIC1_CLK (MTK_PIN_NO(10) | 5)
+#define PINMUX_GPIO10__FUNC_KPCOL2 (MTK_PIN_NO(10) | 6)
+#define PINMUX_GPIO10__FUNC_SCL8 (MTK_PIN_NO(10) | 7)
+
+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define PINMUX_GPIO11__FUNC_MSDC1_CMD_A (MTK_PIN_NO(11) | 1)
+#define PINMUX_GPIO11__FUNC_TP_UTXD1_AO (MTK_PIN_NO(11) | 2)
+#define PINMUX_GPIO11__FUNC_I2S1_DO (MTK_PIN_NO(11) | 3)
+#define PINMUX_GPIO11__FUNC_URTS0 (MTK_PIN_NO(11) | 4)
+#define PINMUX_GPIO11__FUNC_DMIC1_DAT (MTK_PIN_NO(11) | 5)
+#define PINMUX_GPIO11__FUNC_KPROW2 (MTK_PIN_NO(11) | 6)
+#define PINMUX_GPIO11__FUNC_SDA8 (MTK_PIN_NO(11) | 7)
+
+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define PINMUX_GPIO12__FUNC_MSDC1_DAT3_A (MTK_PIN_NO(12) | 1)
+#define PINMUX_GPIO12__FUNC_TP_URXD2_AO (MTK_PIN_NO(12) | 2)
+#define PINMUX_GPIO12__FUNC_I2S1_MCK (MTK_PIN_NO(12) | 3)
+#define PINMUX_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 4)
+#define PINMUX_GPIO12__FUNC_DMIC_CLK (MTK_PIN_NO(12) | 5)
+#define PINMUX_GPIO12__FUNC_ANT_SEL9 (MTK_PIN_NO(12) | 6)
+#define PINMUX_GPIO12__FUNC_SCL9 (MTK_PIN_NO(12) | 7)
+
+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define PINMUX_GPIO13__FUNC_MSDC1_DAT0_A (MTK_PIN_NO(13) | 1)
+#define PINMUX_GPIO13__FUNC_TP_UTXD2_AO (MTK_PIN_NO(13) | 2)
+#define PINMUX_GPIO13__FUNC_I2S1_BCK (MTK_PIN_NO(13) | 3)
+#define PINMUX_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 4)
+#define PINMUX_GPIO13__FUNC_DMIC_DAT (MTK_PIN_NO(13) | 5)
+#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 6)
+#define PINMUX_GPIO13__FUNC_SDA9 (MTK_PIN_NO(13) | 7)
+
+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define PINMUX_GPIO14__FUNC_MSDC1_DAT2_A (MTK_PIN_NO(14) | 1)
+#define PINMUX_GPIO14__FUNC_PWM_3 (MTK_PIN_NO(14) | 2)
+#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 3)
+#define PINMUX_GPIO14__FUNC_MD_INT0 (MTK_PIN_NO(14) | 4)
+#define PINMUX_GPIO14__FUNC_PTA_RXD (MTK_PIN_NO(14) | 5)
+#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 6)
+
+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define PINMUX_GPIO15__FUNC_MSDC1_DAT1_A (MTK_PIN_NO(15) | 1)
+#define PINMUX_GPIO15__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(15) | 2)
+#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 3)
+#define PINMUX_GPIO15__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(15) | 4)
+#define PINMUX_GPIO15__FUNC_PTA_TXD (MTK_PIN_NO(15) | 5)
+#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 6)
+
+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 1)
+#define PINMUX_GPIO16__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(16) | 2)
+#define PINMUX_GPIO16__FUNC_MFG_EJTAG_TRSTN (MTK_PIN_NO(16) | 3)
+#define PINMUX_GPIO16__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(16) | 4)
+#define PINMUX_GPIO16__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(16) | 5)
+#define PINMUX_GPIO16__FUNC_PWM_2 (MTK_PIN_NO(16) | 6)
+#define PINMUX_GPIO16__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(16) | 7)
+
+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define PINMUX_GPIO17__FUNC_SPI0_A_MI (MTK_PIN_NO(17) | 1)
+#define PINMUX_GPIO17__FUNC_SCP_SPI0_MI (MTK_PIN_NO(17) | 2)
+#define PINMUX_GPIO17__FUNC_MFG_EJTAG_TDO (MTK_PIN_NO(17) | 3)
+#define PINMUX_GPIO17__FUNC_DPI_HSYNC (MTK_PIN_NO(17) | 4)
+#define PINMUX_GPIO17__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(17) | 5)
+#define PINMUX_GPIO17__FUNC_DFD_TDO (MTK_PIN_NO(17) | 6)
+#define PINMUX_GPIO17__FUNC_JTDO_SEL1 (MTK_PIN_NO(17) | 7)
+
+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define PINMUX_GPIO18__FUNC_SPI0_A_MO (MTK_PIN_NO(18) | 1)
+#define PINMUX_GPIO18__FUNC_SCP_SPI0_MO (MTK_PIN_NO(18) | 2)
+#define PINMUX_GPIO18__FUNC_MFG_EJTAG_TDI (MTK_PIN_NO(18) | 3)
+#define PINMUX_GPIO18__FUNC_DPI_VSYNC (MTK_PIN_NO(18) | 4)
+#define PINMUX_GPIO18__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(18) | 5)
+#define PINMUX_GPIO18__FUNC_DFD_TDI (MTK_PIN_NO(18) | 6)
+#define PINMUX_GPIO18__FUNC_JTDI_SEL1 (MTK_PIN_NO(18) | 7)
+
+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define PINMUX_GPIO19__FUNC_SPI0_A_CSB (MTK_PIN_NO(19) | 1)
+#define PINMUX_GPIO19__FUNC_SCP_SPI0_CS (MTK_PIN_NO(19) | 2)
+#define PINMUX_GPIO19__FUNC_MFG_EJTAG_TMS (MTK_PIN_NO(19) | 3)
+#define PINMUX_GPIO19__FUNC_DPI_DE (MTK_PIN_NO(19) | 4)
+#define PINMUX_GPIO19__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(19) | 5)
+#define PINMUX_GPIO19__FUNC_DFD_TMS (MTK_PIN_NO(19) | 6)
+#define PINMUX_GPIO19__FUNC_JTMS_SEL1 (MTK_PIN_NO(19) | 7)
+
+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define PINMUX_GPIO20__FUNC_SPI0_A_CLK (MTK_PIN_NO(20) | 1)
+#define PINMUX_GPIO20__FUNC_SCP_SPI0_CK (MTK_PIN_NO(20) | 2)
+#define PINMUX_GPIO20__FUNC_MFG_EJTAG_TCK (MTK_PIN_NO(20) | 3)
+#define PINMUX_GPIO20__FUNC_DPI_CK (MTK_PIN_NO(20) | 4)
+#define PINMUX_GPIO20__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(20) | 5)
+#define PINMUX_GPIO20__FUNC_DFD_TCK_XI (MTK_PIN_NO(20) | 6)
+#define PINMUX_GPIO20__FUNC_JTCK_SEL1 (MTK_PIN_NO(20) | 7)
+
+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define PINMUX_GPIO21__FUNC_PWM_0 (MTK_PIN_NO(21) | 1)
+#define PINMUX_GPIO21__FUNC_CMFLASH0 (MTK_PIN_NO(21) | 2)
+#define PINMUX_GPIO21__FUNC_CMVREF2 (MTK_PIN_NO(21) | 3)
+#define PINMUX_GPIO21__FUNC_CLKM0 (MTK_PIN_NO(21) | 4)
+#define PINMUX_GPIO21__FUNC_ANT_SEL9 (MTK_PIN_NO(21) | 5)
+#define PINMUX_GPIO21__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(21) | 6)
+#define PINMUX_GPIO21__FUNC_DBG_MON_A27 (MTK_PIN_NO(21) | 7)
+
+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define PINMUX_GPIO22__FUNC_PWM_1 (MTK_PIN_NO(22) | 1)
+#define PINMUX_GPIO22__FUNC_CMFLASH1 (MTK_PIN_NO(22) | 2)
+#define PINMUX_GPIO22__FUNC_CMVREF3 (MTK_PIN_NO(22) | 3)
+#define PINMUX_GPIO22__FUNC_CLKM1 (MTK_PIN_NO(22) | 4)
+#define PINMUX_GPIO22__FUNC_ANT_SEL10 (MTK_PIN_NO(22) | 5)
+#define PINMUX_GPIO22__FUNC_DBG_MON_A28 (MTK_PIN_NO(22) | 7)
+
+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define PINMUX_GPIO23__FUNC_PWM_2 (MTK_PIN_NO(23) | 1)
+#define PINMUX_GPIO23__FUNC_CMFLASH2 (MTK_PIN_NO(23) | 2)
+#define PINMUX_GPIO23__FUNC_CMVREF0 (MTK_PIN_NO(23) | 3)
+#define PINMUX_GPIO23__FUNC_CLKM2 (MTK_PIN_NO(23) | 4)
+#define PINMUX_GPIO23__FUNC_ANT_SEL11 (MTK_PIN_NO(23) | 5)
+#define PINMUX_GPIO23__FUNC_DBG_MON_A29 (MTK_PIN_NO(23) | 7)
+
+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define PINMUX_GPIO24__FUNC_PWM_0 (MTK_PIN_NO(24) | 1)
+#define PINMUX_GPIO24__FUNC_CMFLASH3 (MTK_PIN_NO(24) | 2)
+#define PINMUX_GPIO24__FUNC_CMVREF1 (MTK_PIN_NO(24) | 3)
+#define PINMUX_GPIO24__FUNC_CLKM3 (MTK_PIN_NO(24) | 4)
+#define PINMUX_GPIO24__FUNC_ANT_SEL12 (MTK_PIN_NO(24) | 5)
+#define PINMUX_GPIO24__FUNC_DBG_MON_A30 (MTK_PIN_NO(24) | 7)
+
+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1)
+#define PINMUX_GPIO25__FUNC_UCTS0 (MTK_PIN_NO(25) | 2)
+#define PINMUX_GPIO25__FUNC_SCL8 (MTK_PIN_NO(25) | 3)
+#define PINMUX_GPIO25__FUNC_CMVREF4 (MTK_PIN_NO(25) | 4)
+#define PINMUX_GPIO25__FUNC_I2S0_LRCK (MTK_PIN_NO(25) | 5)
+#define PINMUX_GPIO25__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(25) | 6)
+#define PINMUX_GPIO25__FUNC_DBG_MON_A31 (MTK_PIN_NO(25) | 7)
+
+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define PINMUX_GPIO26__FUNC_PWM_0 (MTK_PIN_NO(26) | 1)
+#define PINMUX_GPIO26__FUNC_URTS0 (MTK_PIN_NO(26) | 2)
+#define PINMUX_GPIO26__FUNC_SDA8 (MTK_PIN_NO(26) | 3)
+#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 4)
+#define PINMUX_GPIO26__FUNC_I2S0_DI (MTK_PIN_NO(26) | 5)
+#define PINMUX_GPIO26__FUNC_AGPS_SYNC (MTK_PIN_NO(26) | 6)
+#define PINMUX_GPIO26__FUNC_DBG_MON_A32 (MTK_PIN_NO(26) | 7)
+
+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define PINMUX_GPIO27__FUNC_AP_GOOD (MTK_PIN_NO(27) | 1)
+
+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define PINMUX_GPIO28__FUNC_SCL5 (MTK_PIN_NO(28) | 1)
+
+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define PINMUX_GPIO29__FUNC_SDA5 (MTK_PIN_NO(29) | 1)
+
+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define PINMUX_GPIO30__FUNC_I2S1_MCK (MTK_PIN_NO(30) | 1)
+#define PINMUX_GPIO30__FUNC_I2S3_MCK (MTK_PIN_NO(30) | 2)
+#define PINMUX_GPIO30__FUNC_I2S2_MCK (MTK_PIN_NO(30) | 3)
+#define PINMUX_GPIO30__FUNC_DPI_D0 (MTK_PIN_NO(30) | 4)
+#define PINMUX_GPIO30__FUNC_SPI4_MI (MTK_PIN_NO(30) | 5)
+#define PINMUX_GPIO30__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(30) | 6)
+
+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define PINMUX_GPIO31__FUNC_I2S1_BCK (MTK_PIN_NO(31) | 1)
+#define PINMUX_GPIO31__FUNC_I2S3_BCK (MTK_PIN_NO(31) | 2)
+#define PINMUX_GPIO31__FUNC_I2S2_BCK (MTK_PIN_NO(31) | 3)
+#define PINMUX_GPIO31__FUNC_DPI_D1 (MTK_PIN_NO(31) | 4)
+#define PINMUX_GPIO31__FUNC_SPI4_CSB (MTK_PIN_NO(31) | 5)
+#define PINMUX_GPIO31__FUNC_CONN_MCU_TDO (MTK_PIN_NO(31) | 6)
+
+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define PINMUX_GPIO32__FUNC_I2S1_LRCK (MTK_PIN_NO(32) | 1)
+#define PINMUX_GPIO32__FUNC_I2S3_LRCK (MTK_PIN_NO(32) | 2)
+#define PINMUX_GPIO32__FUNC_I2S2_LRCK (MTK_PIN_NO(32) | 3)
+#define PINMUX_GPIO32__FUNC_DPI_D2 (MTK_PIN_NO(32) | 4)
+#define PINMUX_GPIO32__FUNC_SPI4_MO (MTK_PIN_NO(32) | 5)
+#define PINMUX_GPIO32__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 6)
+
+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define PINMUX_GPIO33__FUNC_I2S2_DI (MTK_PIN_NO(33) | 1)
+#define PINMUX_GPIO33__FUNC_I2S0_DI (MTK_PIN_NO(33) | 2)
+#define PINMUX_GPIO33__FUNC_I2S5_DO (MTK_PIN_NO(33) | 3)
+#define PINMUX_GPIO33__FUNC_DPI_D3 (MTK_PIN_NO(33) | 4)
+#define PINMUX_GPIO33__FUNC_SPI4_CLK (MTK_PIN_NO(33) | 5)
+#define PINMUX_GPIO33__FUNC_CONN_MCU_TMS (MTK_PIN_NO(33) | 6)
+
+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define PINMUX_GPIO34__FUNC_I2S1_DO (MTK_PIN_NO(34) | 1)
+#define PINMUX_GPIO34__FUNC_I2S3_DO (MTK_PIN_NO(34) | 2)
+#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3)
+#define PINMUX_GPIO34__FUNC_DPI_D4 (MTK_PIN_NO(34) | 4)
+#define PINMUX_GPIO34__FUNC_AGPS_SYNC (MTK_PIN_NO(34) | 5)
+#define PINMUX_GPIO34__FUNC_CONN_MCU_TCK (MTK_PIN_NO(34) | 6)
+
+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define PINMUX_GPIO35__FUNC_TDM_LRCK (MTK_PIN_NO(35) | 1)
+#define PINMUX_GPIO35__FUNC_I2S1_LRCK (MTK_PIN_NO(35) | 2)
+#define PINMUX_GPIO35__FUNC_I2S5_LRCK (MTK_PIN_NO(35) | 3)
+#define PINMUX_GPIO35__FUNC_DPI_D5 (MTK_PIN_NO(35) | 4)
+#define PINMUX_GPIO35__FUNC_SPI5_A_MO (MTK_PIN_NO(35) | 5)
+#define PINMUX_GPIO35__FUNC_IO_JTAG_TDI (MTK_PIN_NO(35) | 6)
+#define PINMUX_GPIO35__FUNC_PWM_2 (MTK_PIN_NO(35) | 7)
+
+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define PINMUX_GPIO36__FUNC_TDM_BCK (MTK_PIN_NO(36) | 1)
+#define PINMUX_GPIO36__FUNC_I2S1_BCK (MTK_PIN_NO(36) | 2)
+#define PINMUX_GPIO36__FUNC_I2S5_BCK (MTK_PIN_NO(36) | 3)
+#define PINMUX_GPIO36__FUNC_DPI_D6 (MTK_PIN_NO(36) | 4)
+#define PINMUX_GPIO36__FUNC_SPI5_A_CSB (MTK_PIN_NO(36) | 5)
+#define PINMUX_GPIO36__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(36) | 6)
+#define PINMUX_GPIO36__FUNC_SRCLKENAI1 (MTK_PIN_NO(36) | 7)
+
+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define PINMUX_GPIO37__FUNC_TDM_MCK (MTK_PIN_NO(37) | 1)
+#define PINMUX_GPIO37__FUNC_I2S1_MCK (MTK_PIN_NO(37) | 2)
+#define PINMUX_GPIO37__FUNC_I2S5_MCK (MTK_PIN_NO(37) | 3)
+#define PINMUX_GPIO37__FUNC_DPI_D7 (MTK_PIN_NO(37) | 4)
+#define PINMUX_GPIO37__FUNC_SPI5_A_MI (MTK_PIN_NO(37) | 5)
+#define PINMUX_GPIO37__FUNC_IO_JTAG_TCK (MTK_PIN_NO(37) | 6)
+#define PINMUX_GPIO37__FUNC_SRCLKENAI0 (MTK_PIN_NO(37) | 7)
+
+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define PINMUX_GPIO38__FUNC_TDM_DATA0 (MTK_PIN_NO(38) | 1)
+#define PINMUX_GPIO38__FUNC_I2S2_DI (MTK_PIN_NO(38) | 2)
+#define PINMUX_GPIO38__FUNC_I2S5_DO (MTK_PIN_NO(38) | 3)
+#define PINMUX_GPIO38__FUNC_DPI_D8 (MTK_PIN_NO(38) | 4)
+#define PINMUX_GPIO38__FUNC_SPI5_A_CLK (MTK_PIN_NO(38) | 5)
+#define PINMUX_GPIO38__FUNC_IO_JTAG_TDO (MTK_PIN_NO(38) | 6)
+#define PINMUX_GPIO38__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(38) | 7)
+
+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define PINMUX_GPIO39__FUNC_TDM_DATA1 (MTK_PIN_NO(39) | 1)
+#define PINMUX_GPIO39__FUNC_I2S1_DO (MTK_PIN_NO(39) | 2)
+#define PINMUX_GPIO39__FUNC_I2S2_DI2 (MTK_PIN_NO(39) | 3)
+#define PINMUX_GPIO39__FUNC_DPI_D9 (MTK_PIN_NO(39) | 4)
+#define PINMUX_GPIO39__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(39) | 5)
+#define PINMUX_GPIO39__FUNC_IO_JTAG_TMS (MTK_PIN_NO(39) | 6)
+#define PINMUX_GPIO39__FUNC_IDDIG (MTK_PIN_NO(39) | 7)
+
+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define PINMUX_GPIO40__FUNC_TDM_DATA2 (MTK_PIN_NO(40) | 1)
+#define PINMUX_GPIO40__FUNC_SCL9 (MTK_PIN_NO(40) | 2)
+#define PINMUX_GPIO40__FUNC_PWM_3 (MTK_PIN_NO(40) | 3)
+#define PINMUX_GPIO40__FUNC_DPI_D10 (MTK_PIN_NO(40) | 4)
+#define PINMUX_GPIO40__FUNC_SRCLKENAI0 (MTK_PIN_NO(40) | 5)
+#define PINMUX_GPIO40__FUNC_DAP_MD32_SWD (MTK_PIN_NO(40) | 6)
+#define PINMUX_GPIO40__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 7)
+
+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define PINMUX_GPIO41__FUNC_TDM_DATA3 (MTK_PIN_NO(41) | 1)
+#define PINMUX_GPIO41__FUNC_SDA9 (MTK_PIN_NO(41) | 2)
+#define PINMUX_GPIO41__FUNC_PWM_1 (MTK_PIN_NO(41) | 3)
+#define PINMUX_GPIO41__FUNC_DPI_D11 (MTK_PIN_NO(41) | 4)
+#define PINMUX_GPIO41__FUNC_CLKM1 (MTK_PIN_NO(41) | 5)
+#define PINMUX_GPIO41__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(41) | 6)
+
+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define PINMUX_GPIO42__FUNC_DISP_PWM (MTK_PIN_NO(42) | 1)
+
+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define PINMUX_GPIO43__FUNC_DSI_TE (MTK_PIN_NO(43) | 1)
+
+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define PINMUX_GPIO44__FUNC_LCM_RST (MTK_PIN_NO(44) | 1)
+
+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define PINMUX_GPIO45__FUNC_SCL6 (MTK_PIN_NO(45) | 1)
+#define PINMUX_GPIO45__FUNC_SCP_SCL0 (MTK_PIN_NO(45) | 2)
+#define PINMUX_GPIO45__FUNC_SCP_SCL1 (MTK_PIN_NO(45) | 3)
+#define PINMUX_GPIO45__FUNC_SCL_6306 (MTK_PIN_NO(45) | 4)
+
+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define PINMUX_GPIO46__FUNC_SDA6 (MTK_PIN_NO(46) | 1)
+#define PINMUX_GPIO46__FUNC_SCP_SDA0 (MTK_PIN_NO(46) | 2)
+#define PINMUX_GPIO46__FUNC_SCP_SDA1 (MTK_PIN_NO(46) | 3)
+#define PINMUX_GPIO46__FUNC_SDA_6306 (MTK_PIN_NO(46) | 4)
+
+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define PINMUX_GPIO47__FUNC_SPI1_A_MI (MTK_PIN_NO(47) | 1)
+#define PINMUX_GPIO47__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(47) | 2)
+#define PINMUX_GPIO47__FUNC_KPCOL2 (MTK_PIN_NO(47) | 3)
+#define PINMUX_GPIO47__FUNC_MD_URXD0 (MTK_PIN_NO(47) | 4)
+#define PINMUX_GPIO47__FUNC_CONN_UART0_RXD (MTK_PIN_NO(47) | 5)
+#define PINMUX_GPIO47__FUNC_SSPM_URXD_AO (MTK_PIN_NO(47) | 6)
+#define PINMUX_GPIO47__FUNC_DBG_MON_B32 (MTK_PIN_NO(47) | 7)
+
+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define PINMUX_GPIO48__FUNC_SPI1_A_CSB (MTK_PIN_NO(48) | 1)
+#define PINMUX_GPIO48__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(48) | 2)
+#define PINMUX_GPIO48__FUNC_KPROW2 (MTK_PIN_NO(48) | 3)
+#define PINMUX_GPIO48__FUNC_MD_UTXD0 (MTK_PIN_NO(48) | 4)
+#define PINMUX_GPIO48__FUNC_CONN_UART0_TXD (MTK_PIN_NO(48) | 5)
+#define PINMUX_GPIO48__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(48) | 6)
+#define PINMUX_GPIO48__FUNC_DBG_MON_B31 (MTK_PIN_NO(48) | 7)
+
+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define PINMUX_GPIO49__FUNC_SPI1_A_MO (MTK_PIN_NO(49) | 1)
+#define PINMUX_GPIO49__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(49) | 2)
+#define PINMUX_GPIO49__FUNC_UCTS0 (MTK_PIN_NO(49) | 3)
+#define PINMUX_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 4)
+#define PINMUX_GPIO49__FUNC_PWM_1 (MTK_PIN_NO(49) | 5)
+#define PINMUX_GPIO49__FUNC_TP_URXD2_AO (MTK_PIN_NO(49) | 6)
+#define PINMUX_GPIO49__FUNC_DBG_MON_B30 (MTK_PIN_NO(49) | 7)
+
+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define PINMUX_GPIO50__FUNC_SPI1_A_CLK (MTK_PIN_NO(50) | 1)
+#define PINMUX_GPIO50__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(50) | 2)
+#define PINMUX_GPIO50__FUNC_URTS0 (MTK_PIN_NO(50) | 3)
+#define PINMUX_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 4)
+#define PINMUX_GPIO50__FUNC_WIFI_TXD (MTK_PIN_NO(50) | 5)
+#define PINMUX_GPIO50__FUNC_TP_UTXD2_AO (MTK_PIN_NO(50) | 6)
+#define PINMUX_GPIO50__FUNC_DBG_MON_B29 (MTK_PIN_NO(50) | 7)
+
+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 1)
+
+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 1)
+
+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define PINMUX_GPIO53__FUNC_URXD0 (MTK_PIN_NO(53) | 1)
+#define PINMUX_GPIO53__FUNC_UTXD0 (MTK_PIN_NO(53) | 2)
+#define PINMUX_GPIO53__FUNC_MD_URXD0 (MTK_PIN_NO(53) | 3)
+#define PINMUX_GPIO53__FUNC_MD_URXD1 (MTK_PIN_NO(53) | 4)
+#define PINMUX_GPIO53__FUNC_SSPM_URXD_AO (MTK_PIN_NO(53) | 5)
+#define PINMUX_GPIO53__FUNC_CONN_UART0_RXD (MTK_PIN_NO(53) | 7)
+
+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define PINMUX_GPIO54__FUNC_UTXD0 (MTK_PIN_NO(54) | 1)
+#define PINMUX_GPIO54__FUNC_URXD0 (MTK_PIN_NO(54) | 2)
+#define PINMUX_GPIO54__FUNC_MD_UTXD0 (MTK_PIN_NO(54) | 3)
+#define PINMUX_GPIO54__FUNC_MD_UTXD1 (MTK_PIN_NO(54) | 4)
+#define PINMUX_GPIO54__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(54) | 5)
+#define PINMUX_GPIO54__FUNC_WIFI_TXD (MTK_PIN_NO(54) | 6)
+#define PINMUX_GPIO54__FUNC_CONN_UART0_TXD (MTK_PIN_NO(54) | 7)
+
+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define PINMUX_GPIO55__FUNC_SCL3 (MTK_PIN_NO(55) | 1)
+#define PINMUX_GPIO55__FUNC_SCP_SCL0 (MTK_PIN_NO(55) | 2)
+#define PINMUX_GPIO55__FUNC_SCP_SCL1 (MTK_PIN_NO(55) | 3)
+#define PINMUX_GPIO55__FUNC_SCL_6306 (MTK_PIN_NO(55) | 4)
+
+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define PINMUX_GPIO56__FUNC_SDA3 (MTK_PIN_NO(56) | 1)
+#define PINMUX_GPIO56__FUNC_SCP_SDA0 (MTK_PIN_NO(56) | 2)
+#define PINMUX_GPIO56__FUNC_SCP_SDA1 (MTK_PIN_NO(56) | 3)
+#define PINMUX_GPIO56__FUNC_SDA_6306 (MTK_PIN_NO(56) | 4)
+
+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define PINMUX_GPIO57__FUNC_KPROW1 (MTK_PIN_NO(57) | 1)
+#define PINMUX_GPIO57__FUNC_PWM_1 (MTK_PIN_NO(57) | 2)
+#define PINMUX_GPIO57__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(57) | 3)
+#define PINMUX_GPIO57__FUNC_CLKM1 (MTK_PIN_NO(57) | 4)
+#define PINMUX_GPIO57__FUNC_IDDIG (MTK_PIN_NO(57) | 5)
+#define PINMUX_GPIO57__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(57) | 6)
+#define PINMUX_GPIO57__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(57) | 7)
+
+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define PINMUX_GPIO58__FUNC_KPROW0 (MTK_PIN_NO(58) | 1)
+#define PINMUX_GPIO58__FUNC_DBG_MON_B28 (MTK_PIN_NO(58) | 7)
+
+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define PINMUX_GPIO59__FUNC_KPCOL0 (MTK_PIN_NO(59) | 1)
+#define PINMUX_GPIO59__FUNC_DBG_MON_B27 (MTK_PIN_NO(59) | 7)
+
+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define PINMUX_GPIO60__FUNC_KPCOL1 (MTK_PIN_NO(60) | 1)
+#define PINMUX_GPIO60__FUNC_PWM_2 (MTK_PIN_NO(60) | 2)
+#define PINMUX_GPIO60__FUNC_UCTS1 (MTK_PIN_NO(60) | 3)
+#define PINMUX_GPIO60__FUNC_CLKM2 (MTK_PIN_NO(60) | 4)
+#define PINMUX_GPIO60__FUNC_USB_DRVVBUS (MTK_PIN_NO(60) | 5)
+#define PINMUX_GPIO60__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(60) | 7)
+
+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define PINMUX_GPIO61__FUNC_SCL1 (MTK_PIN_NO(61) | 1)
+#define PINMUX_GPIO61__FUNC_SCP_SCL0 (MTK_PIN_NO(61) | 2)
+#define PINMUX_GPIO61__FUNC_SCP_SCL1 (MTK_PIN_NO(61) | 3)
+
+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define PINMUX_GPIO62__FUNC_SDA1 (MTK_PIN_NO(62) | 1)
+#define PINMUX_GPIO62__FUNC_SCP_SDA0 (MTK_PIN_NO(62) | 2)
+#define PINMUX_GPIO62__FUNC_SCP_SDA1 (MTK_PIN_NO(62) | 3)
+
+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define PINMUX_GPIO63__FUNC_SPI2_MI (MTK_PIN_NO(63) | 1)
+#define PINMUX_GPIO63__FUNC_SCP_SPI2_MI (MTK_PIN_NO(63) | 2)
+#define PINMUX_GPIO63__FUNC_KPCOL2 (MTK_PIN_NO(63) | 3)
+#define PINMUX_GPIO63__FUNC_MRG_DI (MTK_PIN_NO(63) | 4)
+#define PINMUX_GPIO63__FUNC_MD_URXD0 (MTK_PIN_NO(63) | 5)
+#define PINMUX_GPIO63__FUNC_CONN_UART0_RXD (MTK_PIN_NO(63) | 6)
+#define PINMUX_GPIO63__FUNC_DBG_MON_B26 (MTK_PIN_NO(63) | 7)
+
+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define PINMUX_GPIO64__FUNC_SPI2_CSB (MTK_PIN_NO(64) | 1)
+#define PINMUX_GPIO64__FUNC_SCP_SPI2_CS (MTK_PIN_NO(64) | 2)
+#define PINMUX_GPIO64__FUNC_KPROW2 (MTK_PIN_NO(64) | 3)
+#define PINMUX_GPIO64__FUNC_MRG_SYNC (MTK_PIN_NO(64) | 4)
+#define PINMUX_GPIO64__FUNC_MD_UTXD0 (MTK_PIN_NO(64) | 5)
+#define PINMUX_GPIO64__FUNC_CONN_UART0_TXD (MTK_PIN_NO(64) | 6)
+#define PINMUX_GPIO64__FUNC_DBG_MON_B25 (MTK_PIN_NO(64) | 7)
+
+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define PINMUX_GPIO65__FUNC_SPI2_MO (MTK_PIN_NO(65) | 1)
+#define PINMUX_GPIO65__FUNC_SCP_SPI2_MO (MTK_PIN_NO(65) | 2)
+#define PINMUX_GPIO65__FUNC_SCP_SDA1 (MTK_PIN_NO(65) | 3)
+#define PINMUX_GPIO65__FUNC_MRG_DO (MTK_PIN_NO(65) | 4)
+#define PINMUX_GPIO65__FUNC_MD_URXD1 (MTK_PIN_NO(65) | 5)
+#define PINMUX_GPIO65__FUNC_PWM_3 (MTK_PIN_NO(65) | 6)
+
+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define PINMUX_GPIO66__FUNC_SPI2_CLK (MTK_PIN_NO(66) | 1)
+#define PINMUX_GPIO66__FUNC_SCP_SPI2_CK (MTK_PIN_NO(66) | 2)
+#define PINMUX_GPIO66__FUNC_SCP_SCL1 (MTK_PIN_NO(66) | 3)
+#define PINMUX_GPIO66__FUNC_MRG_CLK (MTK_PIN_NO(66) | 4)
+#define PINMUX_GPIO66__FUNC_MD_UTXD1 (MTK_PIN_NO(66) | 5)
+#define PINMUX_GPIO66__FUNC_WIFI_TXD (MTK_PIN_NO(66) | 6)
+
+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define PINMUX_GPIO67__FUNC_I2S3_LRCK (MTK_PIN_NO(67) | 1)
+#define PINMUX_GPIO67__FUNC_I2S1_LRCK (MTK_PIN_NO(67) | 2)
+#define PINMUX_GPIO67__FUNC_URXD1 (MTK_PIN_NO(67) | 3)
+#define PINMUX_GPIO67__FUNC_PCM0_SYNC (MTK_PIN_NO(67) | 4)
+#define PINMUX_GPIO67__FUNC_I2S5_LRCK (MTK_PIN_NO(67) | 5)
+#define PINMUX_GPIO67__FUNC_ANT_SEL9 (MTK_PIN_NO(67) | 6)
+#define PINMUX_GPIO67__FUNC_DBG_MON_B10 (MTK_PIN_NO(67) | 7)
+
+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define PINMUX_GPIO68__FUNC_I2S3_DO (MTK_PIN_NO(68) | 1)
+#define PINMUX_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 2)
+#define PINMUX_GPIO68__FUNC_UTXD1 (MTK_PIN_NO(68) | 3)
+#define PINMUX_GPIO68__FUNC_PCM0_DO (MTK_PIN_NO(68) | 4)
+#define PINMUX_GPIO68__FUNC_I2S5_DO (MTK_PIN_NO(68) | 5)
+#define PINMUX_GPIO68__FUNC_ANT_SEL10 (MTK_PIN_NO(68) | 6)
+#define PINMUX_GPIO68__FUNC_DBG_MON_B9 (MTK_PIN_NO(68) | 7)
+
+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define PINMUX_GPIO69__FUNC_I2S3_MCK (MTK_PIN_NO(69) | 1)
+#define PINMUX_GPIO69__FUNC_I2S1_MCK (MTK_PIN_NO(69) | 2)
+#define PINMUX_GPIO69__FUNC_URTS1 (MTK_PIN_NO(69) | 3)
+#define PINMUX_GPIO69__FUNC_AGPS_SYNC (MTK_PIN_NO(69) | 4)
+#define PINMUX_GPIO69__FUNC_I2S5_MCK (MTK_PIN_NO(69) | 5)
+#define PINMUX_GPIO69__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 6)
+#define PINMUX_GPIO69__FUNC_DBG_MON_B8 (MTK_PIN_NO(69) | 7)
+
+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define PINMUX_GPIO70__FUNC_I2S0_DI (MTK_PIN_NO(70) | 1)
+#define PINMUX_GPIO70__FUNC_I2S2_DI (MTK_PIN_NO(70) | 2)
+#define PINMUX_GPIO70__FUNC_KPCOL2 (MTK_PIN_NO(70) | 3)
+#define PINMUX_GPIO70__FUNC_PCM0_DI (MTK_PIN_NO(70) | 4)
+#define PINMUX_GPIO70__FUNC_I2S2_DI2 (MTK_PIN_NO(70) | 5)
+#define PINMUX_GPIO70__FUNC_ANT_SEL11 (MTK_PIN_NO(70) | 6)
+#define PINMUX_GPIO70__FUNC_DBG_MON_B7 (MTK_PIN_NO(70) | 7)
+
+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define PINMUX_GPIO71__FUNC_I2S3_BCK (MTK_PIN_NO(71) | 1)
+#define PINMUX_GPIO71__FUNC_I2S1_BCK (MTK_PIN_NO(71) | 2)
+#define PINMUX_GPIO71__FUNC_KPROW2 (MTK_PIN_NO(71) | 3)
+#define PINMUX_GPIO71__FUNC_PCM0_CLK (MTK_PIN_NO(71) | 4)
+#define PINMUX_GPIO71__FUNC_I2S5_BCK (MTK_PIN_NO(71) | 5)
+#define PINMUX_GPIO71__FUNC_ANT_SEL12 (MTK_PIN_NO(71) | 6)
+#define PINMUX_GPIO71__FUNC_DBG_MON_B6 (MTK_PIN_NO(71) | 7)
+
+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define PINMUX_GPIO72__FUNC_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 1)
+#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 2)
+
+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define PINMUX_GPIO73__FUNC_BPI_BUS18_PA_VM1 (MTK_PIN_NO(73) | 1)
+#define PINMUX_GPIO73__FUNC_CONN_MIPI5_SCLK (MTK_PIN_NO(73) | 2)
+#define PINMUX_GPIO73__FUNC_MIPI5_SCLK (MTK_PIN_NO(73) | 3)
+
+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define PINMUX_GPIO74__FUNC_BPI_BUS17_PA_VM0 (MTK_PIN_NO(74) | 1)
+#define PINMUX_GPIO74__FUNC_CONN_MIPI5_SDATA (MTK_PIN_NO(74) | 2)
+#define PINMUX_GPIO74__FUNC_MIPI5_SDATA (MTK_PIN_NO(74) | 3)
+
+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define PINMUX_GPIO75__FUNC_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 1)
+#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 2)
+#define PINMUX_GPIO75__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(75) | 3)
+
+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define PINMUX_GPIO76__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(76) | 1)
+
+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define PINMUX_GPIO77__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(77) | 1)
+
+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define PINMUX_GPIO78__FUNC_BPI_BUS7 (MTK_PIN_NO(78) | 1)
+#define PINMUX_GPIO78__FUNC_DBG_MON_B24 (MTK_PIN_NO(78) | 7)
+
+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define PINMUX_GPIO79__FUNC_BPI_BUS6 (MTK_PIN_NO(79) | 1)
+#define PINMUX_GPIO79__FUNC_DBG_MON_B23 (MTK_PIN_NO(79) | 7)
+
+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define PINMUX_GPIO80__FUNC_BPI_BUS8 (MTK_PIN_NO(80) | 1)
+#define PINMUX_GPIO80__FUNC_DBG_MON_B22 (MTK_PIN_NO(80) | 7)
+
+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define PINMUX_GPIO81__FUNC_BPI_BUS9 (MTK_PIN_NO(81) | 1)
+#define PINMUX_GPIO81__FUNC_DBG_MON_B21 (MTK_PIN_NO(81) | 7)
+
+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define PINMUX_GPIO82__FUNC_BPI_BUS10 (MTK_PIN_NO(82) | 1)
+#define PINMUX_GPIO82__FUNC_DBG_MON_B20 (MTK_PIN_NO(82) | 7)
+
+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define PINMUX_GPIO83__FUNC_BPI_BUS11 (MTK_PIN_NO(83) | 1)
+#define PINMUX_GPIO83__FUNC_DBG_MON_B19 (MTK_PIN_NO(83) | 7)
+
+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define PINMUX_GPIO84__FUNC_BPI_BUS12 (MTK_PIN_NO(84) | 1)
+#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS12 (MTK_PIN_NO(84) | 2)
+
+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define PINMUX_GPIO85__FUNC_BPI_BUS13 (MTK_PIN_NO(85) | 1)
+#define PINMUX_GPIO85__FUNC_CONN_BPI_BUS13 (MTK_PIN_NO(85) | 2)
+
+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define PINMUX_GPIO86__FUNC_BPI_BUS14 (MTK_PIN_NO(86) | 1)
+#define PINMUX_GPIO86__FUNC_CONN_BPI_BUS14 (MTK_PIN_NO(86) | 2)
+
+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define PINMUX_GPIO87__FUNC_BPI_BUS15 (MTK_PIN_NO(87) | 1)
+#define PINMUX_GPIO87__FUNC_CONN_BPI_BUS15 (MTK_PIN_NO(87) | 2)
+
+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define PINMUX_GPIO88__FUNC_BPI_BUS16 (MTK_PIN_NO(88) | 1)
+#define PINMUX_GPIO88__FUNC_CONN_BPI_BUS16 (MTK_PIN_NO(88) | 2)
+
+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define PINMUX_GPIO89__FUNC_BPI_BUS5 (MTK_PIN_NO(89) | 1)
+#define PINMUX_GPIO89__FUNC_DBG_MON_B18 (MTK_PIN_NO(89) | 7)
+
+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define PINMUX_GPIO90__FUNC_BPI_BUS4 (MTK_PIN_NO(90) | 1)
+#define PINMUX_GPIO90__FUNC_DBG_MON_B17 (MTK_PIN_NO(90) | 7)
+
+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define PINMUX_GPIO91__FUNC_BPI_BUS3 (MTK_PIN_NO(91) | 1)
+
+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define PINMUX_GPIO92__FUNC_BPI_BUS2 (MTK_PIN_NO(92) | 1)
+#define PINMUX_GPIO92__FUNC_DBG_MON_B16 (MTK_PIN_NO(92) | 7)
+
+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define PINMUX_GPIO93__FUNC_BPI_BUS1 (MTK_PIN_NO(93) | 1)
+
+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define PINMUX_GPIO94__FUNC_BPI_BUS0 (MTK_PIN_NO(94) | 1)
+#define PINMUX_GPIO94__FUNC_DBG_MON_B15 (MTK_PIN_NO(94) | 7)
+
+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define PINMUX_GPIO95__FUNC_MIPI0_SDATA (MTK_PIN_NO(95) | 1)
+
+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define PINMUX_GPIO96__FUNC_MIPI0_SCLK (MTK_PIN_NO(96) | 1)
+
+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define PINMUX_GPIO97__FUNC_MIPI1_SDATA (MTK_PIN_NO(97) | 1)
+
+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define PINMUX_GPIO98__FUNC_MIPI1_SCLK (MTK_PIN_NO(98) | 1)
+
+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define PINMUX_GPIO99__FUNC_MIPI2_SCLK (MTK_PIN_NO(99) | 1)
+#define PINMUX_GPIO99__FUNC_DBG_MON_B14 (MTK_PIN_NO(99) | 7)
+
+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define PINMUX_GPIO100__FUNC_MIPI2_SDATA (MTK_PIN_NO(100) | 1)
+#define PINMUX_GPIO100__FUNC_DBG_MON_B13 (MTK_PIN_NO(100) | 7)
+
+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define PINMUX_GPIO101__FUNC_MIPI3_SCLK (MTK_PIN_NO(101) | 1)
+#define PINMUX_GPIO101__FUNC_DBG_MON_B12 (MTK_PIN_NO(101) | 7)
+
+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define PINMUX_GPIO102__FUNC_MIPI3_SDATA (MTK_PIN_NO(102) | 1)
+#define PINMUX_GPIO102__FUNC_DBG_MON_B11 (MTK_PIN_NO(102) | 7)
+
+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define PINMUX_GPIO103__FUNC_MIPI4_SCLK (MTK_PIN_NO(103) | 1)
+#define PINMUX_GPIO103__FUNC_CONN_MIPI4_SCLK (MTK_PIN_NO(103) | 2)
+
+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define PINMUX_GPIO104__FUNC_MIPI4_SDATA (MTK_PIN_NO(104) | 1)
+#define PINMUX_GPIO104__FUNC_CONN_MIPI4_SDATA (MTK_PIN_NO(104) | 2)
+
+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define PINMUX_GPIO105__FUNC_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 1)
+#define PINMUX_GPIO105__FUNC_CONN_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 2)
+
+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define PINMUX_GPIO106__FUNC_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 1)
+#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 2)
+
+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define PINMUX_GPIO107__FUNC_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 1)
+#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 2)
+
+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define PINMUX_GPIO108__FUNC_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 1)
+#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 2)
+
+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define PINMUX_GPIO109__FUNC_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 1)
+#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 2)
+
+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define PINMUX_GPIO110__FUNC_SCL4 (MTK_PIN_NO(110) | 1)
+
+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define PINMUX_GPIO111__FUNC_SDA4 (MTK_PIN_NO(111) | 1)
+
+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define PINMUX_GPIO112__FUNC_SCL2 (MTK_PIN_NO(112) | 1)
+
+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define PINMUX_GPIO113__FUNC_SDA2 (MTK_PIN_NO(113) | 1)
+
+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define PINMUX_GPIO114__FUNC_CLKM0 (MTK_PIN_NO(114) | 1)
+#define PINMUX_GPIO114__FUNC_SPI3_MI (MTK_PIN_NO(114) | 2)
+#define PINMUX_GPIO114__FUNC_DBG_MON_B5 (MTK_PIN_NO(114) | 7)
+
+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define PINMUX_GPIO115__FUNC_CLKM1 (MTK_PIN_NO(115) | 1)
+#define PINMUX_GPIO115__FUNC_SPI3_CSB (MTK_PIN_NO(115) | 2)
+#define PINMUX_GPIO115__FUNC_DBG_MON_B4 (MTK_PIN_NO(115) | 7)
+
+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define PINMUX_GPIO116__FUNC_CMMCLK0 (MTK_PIN_NO(116) | 1)
+#define PINMUX_GPIO116__FUNC_DBG_MON_B3 (MTK_PIN_NO(116) | 7)
+
+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define PINMUX_GPIO117__FUNC_CMMCLK1 (MTK_PIN_NO(117) | 1)
+#define PINMUX_GPIO117__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(117) | 2)
+#define PINMUX_GPIO117__FUNC_DBG_MON_B2 (MTK_PIN_NO(117) | 7)
+
+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define PINMUX_GPIO118__FUNC_CLKM2 (MTK_PIN_NO(118) | 1)
+#define PINMUX_GPIO118__FUNC_SPI3_MO (MTK_PIN_NO(118) | 2)
+#define PINMUX_GPIO118__FUNC_DBG_MON_B1 (MTK_PIN_NO(118) | 7)
+
+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define PINMUX_GPIO119__FUNC_CLKM3 (MTK_PIN_NO(119) | 1)
+#define PINMUX_GPIO119__FUNC_SPI3_CLK (MTK_PIN_NO(119) | 2)
+#define PINMUX_GPIO119__FUNC_DBG_MON_B0 (MTK_PIN_NO(119) | 7)
+
+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define PINMUX_GPIO120__FUNC_CMMCLK2 (MTK_PIN_NO(120) | 1)
+#define PINMUX_GPIO120__FUNC_CLKM2 (MTK_PIN_NO(120) | 2)
+#define PINMUX_GPIO120__FUNC_ANT_SEL12 (MTK_PIN_NO(120) | 6)
+#define PINMUX_GPIO120__FUNC_TP_UCTS2_AO (MTK_PIN_NO(120) | 7)
+
+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define PINMUX_GPIO121__FUNC_CMMCLK3 (MTK_PIN_NO(121) | 1)
+#define PINMUX_GPIO121__FUNC_CLKM3 (MTK_PIN_NO(121) | 2)
+#define PINMUX_GPIO121__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(121) | 3)
+#define PINMUX_GPIO121__FUNC_ANT_SEL11 (MTK_PIN_NO(121) | 6)
+#define PINMUX_GPIO121__FUNC_TP_URTS2_AO (MTK_PIN_NO(121) | 7)
+
+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define PINMUX_GPIO122__FUNC_CMVREF1 (MTK_PIN_NO(122) | 1)
+#define PINMUX_GPIO122__FUNC_PCM0_SYNC (MTK_PIN_NO(122) | 2)
+#define PINMUX_GPIO122__FUNC_SRCLKENAI1 (MTK_PIN_NO(122) | 3)
+#define PINMUX_GPIO122__FUNC_AGPS_SYNC (MTK_PIN_NO(122) | 4)
+#define PINMUX_GPIO122__FUNC_PWM_1 (MTK_PIN_NO(122) | 5)
+#define PINMUX_GPIO122__FUNC_ANT_SEL9 (MTK_PIN_NO(122) | 6)
+#define PINMUX_GPIO122__FUNC_TP_UCTS1_AO (MTK_PIN_NO(122) | 7)
+
+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define PINMUX_GPIO123__FUNC_PCM0_DI (MTK_PIN_NO(123) | 2)
+#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 3)
+#define PINMUX_GPIO123__FUNC_VPU_UDI_NTRST (MTK_PIN_NO(123) | 4)
+#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 5)
+#define PINMUX_GPIO123__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(123) | 6)
+
+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define PINMUX_GPIO124__FUNC_CMVREF2 (MTK_PIN_NO(124) | 1)
+#define PINMUX_GPIO124__FUNC_PCM0_CLK (MTK_PIN_NO(124) | 2)
+#define PINMUX_GPIO124__FUNC_MD_INT0 (MTK_PIN_NO(124) | 3)
+#define PINMUX_GPIO124__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(124) | 4)
+#define PINMUX_GPIO124__FUNC_PWM_2 (MTK_PIN_NO(124) | 5)
+#define PINMUX_GPIO124__FUNC_ANT_SEL10 (MTK_PIN_NO(124) | 6)
+#define PINMUX_GPIO124__FUNC_TP_URTS1_AO (MTK_PIN_NO(124) | 7)
+
+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define PINMUX_GPIO125__FUNC_CMVREF3 (MTK_PIN_NO(125) | 1)
+#define PINMUX_GPIO125__FUNC_PCM0_DO (MTK_PIN_NO(125) | 2)
+#define PINMUX_GPIO125__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(125) | 3)
+#define PINMUX_GPIO125__FUNC_VPU_UDI_TMS (MTK_PIN_NO(125) | 4)
+#define PINMUX_GPIO125__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(125) | 5)
+#define PINMUX_GPIO125__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(125) | 6)
+
+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define PINMUX_GPIO126__FUNC_CMVREF4 (MTK_PIN_NO(126) | 1)
+#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 2)
+#define PINMUX_GPIO126__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(126) | 6)
+
+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define PINMUX_GPIO127__FUNC_CMVREF0 (MTK_PIN_NO(127) | 1)
+#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 2)
+#define PINMUX_GPIO127__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(127) | 6)
+
+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define PINMUX_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1)
+#define PINMUX_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2)
+#define PINMUX_GPIO128__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(128) | 3)
+#define PINMUX_GPIO128__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(128) | 4)
+#define PINMUX_GPIO128__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(128) | 5)
+#define PINMUX_GPIO128__FUNC_LVTS_FOUT (MTK_PIN_NO(128) | 6)
+#define PINMUX_GPIO128__FUNC_DBG_MON_A3 (MTK_PIN_NO(128) | 7)
+
+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define PINMUX_GPIO129__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(129) | 1)
+#define PINMUX_GPIO129__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(129) | 2)
+#define PINMUX_GPIO129__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(129) | 3)
+#define PINMUX_GPIO129__FUNC_CONN_DSP_JCK (MTK_PIN_NO(129) | 4)
+#define PINMUX_GPIO129__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(129) | 5)
+#define PINMUX_GPIO129__FUNC_LVTS_SDO (MTK_PIN_NO(129) | 6)
+#define PINMUX_GPIO129__FUNC_DBG_MON_A4 (MTK_PIN_NO(129) | 7)
+
+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define PINMUX_GPIO130__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(130) | 1)
+#define PINMUX_GPIO130__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(130) | 2)
+#define PINMUX_GPIO130__FUNC_LVTS_26M (MTK_PIN_NO(130) | 6)
+#define PINMUX_GPIO130__FUNC_DBG_MON_A5 (MTK_PIN_NO(130) | 7)
+
+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define PINMUX_GPIO131__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(131) | 1)
+#define PINMUX_GPIO131__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(131) | 2)
+#define PINMUX_GPIO131__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(131) | 3)
+#define PINMUX_GPIO131__FUNC_CONN_DSP_JDI (MTK_PIN_NO(131) | 4)
+#define PINMUX_GPIO131__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(131) | 5)
+#define PINMUX_GPIO131__FUNC_LVTS_SCK (MTK_PIN_NO(131) | 6)
+#define PINMUX_GPIO131__FUNC_DBG_MON_A0 (MTK_PIN_NO(131) | 7)
+
+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define PINMUX_GPIO132__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(132) | 1)
+#define PINMUX_GPIO132__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(132) | 2)
+#define PINMUX_GPIO132__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(132) | 3)
+#define PINMUX_GPIO132__FUNC_CONN_DSP_JMS (MTK_PIN_NO(132) | 4)
+#define PINMUX_GPIO132__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(132) | 5)
+#define PINMUX_GPIO132__FUNC_LVTS_SDI (MTK_PIN_NO(132) | 6)
+#define PINMUX_GPIO132__FUNC_DBG_MON_A1 (MTK_PIN_NO(132) | 7)
+
+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define PINMUX_GPIO133__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(133) | 1)
+#define PINMUX_GPIO133__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(133) | 2)
+#define PINMUX_GPIO133__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(133) | 3)
+#define PINMUX_GPIO133__FUNC_CONN_DSP_JDO (MTK_PIN_NO(133) | 4)
+#define PINMUX_GPIO133__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(133) | 5)
+#define PINMUX_GPIO133__FUNC_LVTS_SCF (MTK_PIN_NO(133) | 6)
+#define PINMUX_GPIO133__FUNC_DBG_MON_A2 (MTK_PIN_NO(133) | 7)
+
+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define PINMUX_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1)
+#define PINMUX_GPIO134__FUNC_PCM1_CLK (MTK_PIN_NO(134) | 2)
+#define PINMUX_GPIO134__FUNC_SPI5_B_MI (MTK_PIN_NO(134) | 3)
+#define PINMUX_GPIO134__FUNC_UDI_TCK (MTK_PIN_NO(134) | 4)
+#define PINMUX_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 5)
+#define PINMUX_GPIO134__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(134) | 6)
+#define PINMUX_GPIO134__FUNC_JTCK_SEL3 (MTK_PIN_NO(134) | 7)
+
+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define PINMUX_GPIO135__FUNC_MSDC1_CMD (MTK_PIN_NO(135) | 1)
+#define PINMUX_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 2)
+#define PINMUX_GPIO135__FUNC_SPI5_B_CSB (MTK_PIN_NO(135) | 3)
+#define PINMUX_GPIO135__FUNC_UDI_TMS (MTK_PIN_NO(135) | 4)
+#define PINMUX_GPIO135__FUNC_CONN_DSP_JMS (MTK_PIN_NO(135) | 5)
+#define PINMUX_GPIO135__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(135) | 6)
+#define PINMUX_GPIO135__FUNC_JTMS_SEL3 (MTK_PIN_NO(135) | 7)
+
+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define PINMUX_GPIO136__FUNC_MSDC1_DAT3 (MTK_PIN_NO(136) | 1)
+#define PINMUX_GPIO136__FUNC_PCM1_DI (MTK_PIN_NO(136) | 2)
+#define PINMUX_GPIO136__FUNC_SPI5_B_MO (MTK_PIN_NO(136) | 3)
+#define PINMUX_GPIO136__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(136) | 4)
+#define PINMUX_GPIO136__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(136) | 5)
+#define PINMUX_GPIO136__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(136) | 6)
+
+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define PINMUX_GPIO137__FUNC_MSDC1_DAT0 (MTK_PIN_NO(137) | 1)
+#define PINMUX_GPIO137__FUNC_PCM1_DO0 (MTK_PIN_NO(137) | 2)
+#define PINMUX_GPIO137__FUNC_SPI5_B_CLK (MTK_PIN_NO(137) | 3)
+#define PINMUX_GPIO137__FUNC_UDI_TDI (MTK_PIN_NO(137) | 4)
+#define PINMUX_GPIO137__FUNC_CONN_DSP_JDI (MTK_PIN_NO(137) | 5)
+#define PINMUX_GPIO137__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(137) | 6)
+#define PINMUX_GPIO137__FUNC_JTDI_SEL3 (MTK_PIN_NO(137) | 7)
+
+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define PINMUX_GPIO138__FUNC_MSDC1_DAT2 (MTK_PIN_NO(138) | 1)
+#define PINMUX_GPIO138__FUNC_PCM1_DO2 (MTK_PIN_NO(138) | 2)
+#define PINMUX_GPIO138__FUNC_ANT_SEL11 (MTK_PIN_NO(138) | 3)
+#define PINMUX_GPIO138__FUNC_UDI_NTRST (MTK_PIN_NO(138) | 4)
+#define PINMUX_GPIO138__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(138) | 5)
+#define PINMUX_GPIO138__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(138) | 6)
+#define PINMUX_GPIO138__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(138) | 7)
+
+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define PINMUX_GPIO139__FUNC_MSDC1_DAT1 (MTK_PIN_NO(139) | 1)
+#define PINMUX_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 2)
+#define PINMUX_GPIO139__FUNC_ANT_SEL12 (MTK_PIN_NO(139) | 3)
+#define PINMUX_GPIO139__FUNC_UDI_TDO (MTK_PIN_NO(139) | 4)
+#define PINMUX_GPIO139__FUNC_CONN_DSP_JDO (MTK_PIN_NO(139) | 5)
+#define PINMUX_GPIO139__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(139) | 6)
+#define PINMUX_GPIO139__FUNC_JTDO_SEL3 (MTK_PIN_NO(139) | 7)
+
+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define PINMUX_GPIO140__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(140) | 1)
+#define PINMUX_GPIO140__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(140) | 2)
+#define PINMUX_GPIO140__FUNC_ADSP_URXD0 (MTK_PIN_NO(140) | 3)
+#define PINMUX_GPIO140__FUNC_SCL_6306 (MTK_PIN_NO(140) | 4)
+#define PINMUX_GPIO140__FUNC_PTA_RXD (MTK_PIN_NO(140) | 5)
+#define PINMUX_GPIO140__FUNC_SSPM_URXD_AO (MTK_PIN_NO(140) | 6)
+
+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define PINMUX_GPIO141__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(141) | 1)
+#define PINMUX_GPIO141__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(141) | 2)
+#define PINMUX_GPIO141__FUNC_ADSP_UTXD0 (MTK_PIN_NO(141) | 3)
+#define PINMUX_GPIO141__FUNC_SDA_6306 (MTK_PIN_NO(141) | 4)
+#define PINMUX_GPIO141__FUNC_PTA_TXD (MTK_PIN_NO(141) | 5)
+#define PINMUX_GPIO141__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(141) | 6)
+
+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define PINMUX_GPIO142__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(142) | 1)
+#define PINMUX_GPIO142__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(142) | 2)
+
+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(143) | 1)
+#define PINMUX_GPIO143__FUNC_DBG_MON_A9 (MTK_PIN_NO(143) | 7)
+
+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define PINMUX_GPIO144__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(144) | 1)
+#define PINMUX_GPIO144__FUNC_AUD_CLK_MISO (MTK_PIN_NO(144) | 2)
+#define PINMUX_GPIO144__FUNC_I2S2_MCK (MTK_PIN_NO(144) | 3)
+#define PINMUX_GPIO144__FUNC_UDI_TCK (MTK_PIN_NO(144) | 5)
+#define PINMUX_GPIO144__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(144) | 6)
+#define PINMUX_GPIO144__FUNC_DBG_MON_A10 (MTK_PIN_NO(144) | 7)
+
+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define PINMUX_GPIO145__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(145) | 1)
+#define PINMUX_GPIO145__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(145) | 2)
+#define PINMUX_GPIO145__FUNC_I2S2_BCK (MTK_PIN_NO(145) | 3)
+#define PINMUX_GPIO145__FUNC_UDI_TMS (MTK_PIN_NO(145) | 5)
+#define PINMUX_GPIO145__FUNC_DBG_MON_A11 (MTK_PIN_NO(145) | 7)
+
+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define PINMUX_GPIO146__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(146) | 1)
+#define PINMUX_GPIO146__FUNC_I2S2_DI2 (MTK_PIN_NO(146) | 3)
+#define PINMUX_GPIO146__FUNC_UDI_TDO (MTK_PIN_NO(146) | 5)
+#define PINMUX_GPIO146__FUNC_DBG_MON_A14 (MTK_PIN_NO(146) | 7)
+
+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define PINMUX_GPIO147__FUNC_ANT_SEL0 (MTK_PIN_NO(147) | 1)
+#define PINMUX_GPIO147__FUNC_PWM_3 (MTK_PIN_NO(147) | 2)
+
+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define PINMUX_GPIO148__FUNC_ANT_SEL1 (MTK_PIN_NO(148) | 1)
+#define PINMUX_GPIO148__FUNC_SPI0_B_MI (MTK_PIN_NO(148) | 2)
+#define PINMUX_GPIO148__FUNC_SSPM_URXD_AO (MTK_PIN_NO(148) | 3)
+#define PINMUX_GPIO148__FUNC_TP_UCTS2_AO (MTK_PIN_NO(148) | 5)
+#define PINMUX_GPIO148__FUNC_CLKM0 (MTK_PIN_NO(148) | 6)
+
+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define PINMUX_GPIO149__FUNC_ANT_SEL2 (MTK_PIN_NO(149) | 1)
+#define PINMUX_GPIO149__FUNC_SPI0_B_CSB (MTK_PIN_NO(149) | 2)
+#define PINMUX_GPIO149__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(149) | 3)
+#define PINMUX_GPIO149__FUNC_TP_URTS2_AO (MTK_PIN_NO(149) | 5)
+#define PINMUX_GPIO149__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(149) | 6)
+
+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define PINMUX_GPIO150__FUNC_ANT_SEL3 (MTK_PIN_NO(150) | 1)
+#define PINMUX_GPIO150__FUNC_SPI0_B_MO (MTK_PIN_NO(150) | 2)
+#define PINMUX_GPIO150__FUNC_UCTS1 (MTK_PIN_NO(150) | 3)
+#define PINMUX_GPIO150__FUNC_TP_UCTS1_AO (MTK_PIN_NO(150) | 5)
+#define PINMUX_GPIO150__FUNC_IDDIG (MTK_PIN_NO(150) | 6)
+#define PINMUX_GPIO150__FUNC_SCL9 (MTK_PIN_NO(150) | 7)
+
+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define PINMUX_GPIO151__FUNC_ANT_SEL4 (MTK_PIN_NO(151) | 1)
+#define PINMUX_GPIO151__FUNC_SPI0_B_CLK (MTK_PIN_NO(151) | 2)
+#define PINMUX_GPIO151__FUNC_URTS1 (MTK_PIN_NO(151) | 3)
+#define PINMUX_GPIO151__FUNC_TP_URTS1_AO (MTK_PIN_NO(151) | 5)
+#define PINMUX_GPIO151__FUNC_USB_DRVVBUS (MTK_PIN_NO(151) | 6)
+#define PINMUX_GPIO151__FUNC_SDA9 (MTK_PIN_NO(151) | 7)
+
+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define PINMUX_GPIO152__FUNC_ANT_SEL5 (MTK_PIN_NO(152) | 1)
+#define PINMUX_GPIO152__FUNC_SPI1_B_MI (MTK_PIN_NO(152) | 2)
+#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 3)
+#define PINMUX_GPIO152__FUNC_TP_URXD1_AO (MTK_PIN_NO(152) | 5)
+#define PINMUX_GPIO152__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(152) | 6)
+#define PINMUX_GPIO152__FUNC_SCL8 (MTK_PIN_NO(152) | 7)
+
+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define PINMUX_GPIO153__FUNC_ANT_SEL6 (MTK_PIN_NO(153) | 1)
+#define PINMUX_GPIO153__FUNC_SPI1_B_CSB (MTK_PIN_NO(153) | 2)
+#define PINMUX_GPIO153__FUNC_SRCLKENAI0 (MTK_PIN_NO(153) | 3)
+#define PINMUX_GPIO153__FUNC_PWM_0 (MTK_PIN_NO(153) | 4)
+#define PINMUX_GPIO153__FUNC_TP_UTXD1_AO (MTK_PIN_NO(153) | 5)
+#define PINMUX_GPIO153__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(153) | 6)
+#define PINMUX_GPIO153__FUNC_SDA8 (MTK_PIN_NO(153) | 7)
+
+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define PINMUX_GPIO154__FUNC_ANT_SEL7 (MTK_PIN_NO(154) | 1)
+#define PINMUX_GPIO154__FUNC_SPI1_B_MO (MTK_PIN_NO(154) | 2)
+#define PINMUX_GPIO154__FUNC_SRCLKENAI1 (MTK_PIN_NO(154) | 3)
+#define PINMUX_GPIO154__FUNC_TP_URXD2_AO (MTK_PIN_NO(154) | 5)
+#define PINMUX_GPIO154__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(154) | 6)
+
+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define PINMUX_GPIO155__FUNC_ANT_SEL8 (MTK_PIN_NO(155) | 1)
+#define PINMUX_GPIO155__FUNC_SPI1_B_CLK (MTK_PIN_NO(155) | 2)
+#define PINMUX_GPIO155__FUNC_MD_INT0 (MTK_PIN_NO(155) | 3)
+#define PINMUX_GPIO155__FUNC_TP_UTXD2_AO (MTK_PIN_NO(155) | 5)
+#define PINMUX_GPIO155__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(155) | 6)
+#define PINMUX_GPIO155__FUNC_DBG_MON_A15 (MTK_PIN_NO(155) | 7)
+
+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define PINMUX_GPIO156__FUNC_CONN_TOP_CLK (MTK_PIN_NO(156) | 1)
+#define PINMUX_GPIO156__FUNC_AUXIF_CLK0 (MTK_PIN_NO(156) | 2)
+#define PINMUX_GPIO156__FUNC_DBG_MON_A16 (MTK_PIN_NO(156) | 7)
+
+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define PINMUX_GPIO157__FUNC_CONN_TOP_DATA (MTK_PIN_NO(157) | 1)
+#define PINMUX_GPIO157__FUNC_AUXIF_ST0 (MTK_PIN_NO(157) | 2)
+#define PINMUX_GPIO157__FUNC_DBG_MON_A17 (MTK_PIN_NO(157) | 7)
+
+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define PINMUX_GPIO158__FUNC_CONN_HRST_B (MTK_PIN_NO(158) | 1)
+#define PINMUX_GPIO158__FUNC_DBG_MON_A18 (MTK_PIN_NO(158) | 7)
+
+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define PINMUX_GPIO159__FUNC_CONN_WB_PTA (MTK_PIN_NO(159) | 1)
+#define PINMUX_GPIO159__FUNC_DBG_MON_A19 (MTK_PIN_NO(159) | 7)
+
+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define PINMUX_GPIO160__FUNC_CONN_BT_CLK (MTK_PIN_NO(160) | 1)
+#define PINMUX_GPIO160__FUNC_AUXIF_CLK1 (MTK_PIN_NO(160) | 2)
+#define PINMUX_GPIO160__FUNC_DBG_MON_A20 (MTK_PIN_NO(160) | 7)
+
+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define PINMUX_GPIO161__FUNC_CONN_BT_DATA (MTK_PIN_NO(161) | 1)
+#define PINMUX_GPIO161__FUNC_AUXIF_ST1 (MTK_PIN_NO(161) | 2)
+#define PINMUX_GPIO161__FUNC_DBG_MON_A21 (MTK_PIN_NO(161) | 7)
+
+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define PINMUX_GPIO162__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(162) | 1)
+#define PINMUX_GPIO162__FUNC_DBG_MON_A22 (MTK_PIN_NO(162) | 7)
+
+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define PINMUX_GPIO163__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(163) | 1)
+#define PINMUX_GPIO163__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(163) | 2)
+#define PINMUX_GPIO163__FUNC_DBG_MON_A23 (MTK_PIN_NO(163) | 7)
+
+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define PINMUX_GPIO164__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(164) | 1)
+#define PINMUX_GPIO164__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(164) | 2)
+#define PINMUX_GPIO164__FUNC_DBG_MON_A24 (MTK_PIN_NO(164) | 7)
+
+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define PINMUX_GPIO165__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(165) | 1)
+#define PINMUX_GPIO165__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(165) | 2)
+#define PINMUX_GPIO165__FUNC_DBG_MON_A25 (MTK_PIN_NO(165) | 7)
+
+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define PINMUX_GPIO166__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(166) | 1)
+#define PINMUX_GPIO166__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(166) | 2)
+#define PINMUX_GPIO166__FUNC_DBG_MON_A26 (MTK_PIN_NO(166) | 7)
+
+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define PINMUX_GPIO167__FUNC_MSDC0_CMD (MTK_PIN_NO(167) | 1)
+
+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define PINMUX_GPIO168__FUNC_MSDC0_DAT0 (MTK_PIN_NO(168) | 1)
+
+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define PINMUX_GPIO169__FUNC_MSDC0_DAT2 (MTK_PIN_NO(169) | 1)
+
+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define PINMUX_GPIO170__FUNC_MSDC0_DAT4 (MTK_PIN_NO(170) | 1)
+
+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define PINMUX_GPIO171__FUNC_MSDC0_DAT6 (MTK_PIN_NO(171) | 1)
+
+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define PINMUX_GPIO172__FUNC_MSDC0_DAT1 (MTK_PIN_NO(172) | 1)
+
+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define PINMUX_GPIO173__FUNC_MSDC0_DAT5 (MTK_PIN_NO(173) | 1)
+
+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define PINMUX_GPIO174__FUNC_MSDC0_DAT7 (MTK_PIN_NO(174) | 1)
+
+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define PINMUX_GPIO175__FUNC_MSDC0_DSL (MTK_PIN_NO(175) | 1)
+#define PINMUX_GPIO175__FUNC_ANT_SEL9 (MTK_PIN_NO(175) | 2)
+
+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define PINMUX_GPIO176__FUNC_MSDC0_CLK (MTK_PIN_NO(176) | 1)
+#define PINMUX_GPIO176__FUNC_ANT_SEL10 (MTK_PIN_NO(176) | 2)
+
+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define PINMUX_GPIO177__FUNC_MSDC0_DAT3 (MTK_PIN_NO(177) | 1)
+
+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define PINMUX_GPIO178__FUNC_MSDC0_RSTB (MTK_PIN_NO(178) | 1)
+
+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define PINMUX_GPIO179__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(179) | 1)
+
+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define PINMUX_GPIO180__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(180) | 1)
+
+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define PINMUX_GPIO181__FUNC_SRCLKENA0 (MTK_PIN_NO(181) | 1)
+
+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define PINMUX_GPIO182__FUNC_SRCLKENA1 (MTK_PIN_NO(182) | 1)
+
+#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define PINMUX_GPIO183__FUNC_WATCHDOG (MTK_PIN_NO(183) | 1)
+
+#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(184) | 1)
+#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(184) | 2)
+
+#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)
+#define PINMUX_GPIO185__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(185) | 1)
+
+#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)
+#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(186) | 1)
+#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(186) | 2)
+
+#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)
+#define PINMUX_GPIO187__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(187) | 1)
+
+#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)
+#define PINMUX_GPIO188__FUNC_RTC32K_CK (MTK_PIN_NO(188) | 1)
+
+#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)
+#define PINMUX_GPIO189__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(189) | 1)
+#define PINMUX_GPIO189__FUNC_I2S1_MCK (MTK_PIN_NO(189) | 3)
+#define PINMUX_GPIO189__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(189) | 6)
+
+#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)
+#define PINMUX_GPIO190__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(190) | 1)
+#define PINMUX_GPIO190__FUNC_I2S1_BCK (MTK_PIN_NO(190) | 3)
+#define PINMUX_GPIO190__FUNC_DBG_MON_A6 (MTK_PIN_NO(190) | 7)
+
+#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)
+#define PINMUX_GPIO191__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(191) | 1)
+#define PINMUX_GPIO191__FUNC_I2S1_LRCK (MTK_PIN_NO(191) | 3)
+#define PINMUX_GPIO191__FUNC_DBG_MON_A7 (MTK_PIN_NO(191) | 7)
+
+#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)
+#define PINMUX_GPIO192__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(192) | 1)
+#define PINMUX_GPIO192__FUNC_I2S1_DO (MTK_PIN_NO(192) | 3)
+#define PINMUX_GPIO192__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(192) | 6)
+#define PINMUX_GPIO192__FUNC_DBG_MON_A8 (MTK_PIN_NO(192) | 7)
+
+#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)
+#define PINMUX_GPIO193__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(193) | 1)
+#define PINMUX_GPIO193__FUNC_VOW_DAT_MISO (MTK_PIN_NO(193) | 2)
+#define PINMUX_GPIO193__FUNC_I2S2_LRCK (MTK_PIN_NO(193) | 3)
+#define PINMUX_GPIO193__FUNC_UDI_TDI (MTK_PIN_NO(193) | 5)
+#define PINMUX_GPIO193__FUNC_DBG_MON_A12 (MTK_PIN_NO(193) | 7)
+
+#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)
+#define PINMUX_GPIO194__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(194) | 1)
+#define PINMUX_GPIO194__FUNC_VOW_CLK_MISO (MTK_PIN_NO(194) | 2)
+#define PINMUX_GPIO194__FUNC_I2S2_DI (MTK_PIN_NO(194) | 3)
+#define PINMUX_GPIO194__FUNC_UDI_NTRST (MTK_PIN_NO(194) | 5)
+#define PINMUX_GPIO194__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(194) | 6)
+#define PINMUX_GPIO194__FUNC_DBG_MON_A13 (MTK_PIN_NO(194) | 7)
+
+#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)
+#define PINMUX_GPIO195__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(195) | 3)
+#define PINMUX_GPIO195__FUNC_VPU_UDI_TCK (MTK_PIN_NO(195) | 4)
+#define PINMUX_GPIO195__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(195) | 5)
+#define PINMUX_GPIO195__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(195) | 6)
+
+#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)
+#define PINMUX_GPIO196__FUNC_CMMCLK4 (MTK_PIN_NO(196) | 1)
+#define PINMUX_GPIO196__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(196) | 3)
+#define PINMUX_GPIO196__FUNC_VPU_UDI_TDI (MTK_PIN_NO(196) | 4)
+#define PINMUX_GPIO196__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(196) | 5)
+#define PINMUX_GPIO196__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(196) | 6)
+
+#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0)
+#define PINMUX_GPIO197__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(197) | 3)
+#define PINMUX_GPIO197__FUNC_VPU_UDI_TDO (MTK_PIN_NO(197) | 4)
+#define PINMUX_GPIO197__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(197) | 5)
+#define PINMUX_GPIO197__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(197) | 6)
+
+#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0)
+#define PINMUX_GPIO198__FUNC_SCL7 (MTK_PIN_NO(198) | 1)
+
+#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define PINMUX_GPIO199__FUNC_SDA7 (MTK_PIN_NO(199) | 1)
+
+#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define PINMUX_GPIO200__FUNC_URXD1 (MTK_PIN_NO(200) | 1)
+#define PINMUX_GPIO200__FUNC_ADSP_URXD0 (MTK_PIN_NO(200) | 2)
+#define PINMUX_GPIO200__FUNC_TP_URXD1_AO (MTK_PIN_NO(200) | 3)
+#define PINMUX_GPIO200__FUNC_SSPM_URXD_AO (MTK_PIN_NO(200) | 4)
+#define PINMUX_GPIO200__FUNC_TP_URXD2_AO (MTK_PIN_NO(200) | 5)
+#define PINMUX_GPIO200__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(200) | 6)
+
+#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define PINMUX_GPIO201__FUNC_UTXD1 (MTK_PIN_NO(201) | 1)
+#define PINMUX_GPIO201__FUNC_ADSP_UTXD0 (MTK_PIN_NO(201) | 2)
+#define PINMUX_GPIO201__FUNC_TP_UTXD1_AO (MTK_PIN_NO(201) | 3)
+#define PINMUX_GPIO201__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(201) | 4)
+#define PINMUX_GPIO201__FUNC_TP_UTXD2_AO (MTK_PIN_NO(201) | 5)
+#define PINMUX_GPIO201__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(201) | 6)
+
+#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define PINMUX_GPIO202__FUNC_PWM_3 (MTK_PIN_NO(202) | 1)
+#define PINMUX_GPIO202__FUNC_CLKM3 (MTK_PIN_NO(202) | 2)
+
+#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+
+#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+
+#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+
+#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+
+#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+
+#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+
+#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+
+#endif /* __MT6779-PINFUNC_H */
#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
-#define AM33XX_PADCONF(pa, dir, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux))
+#define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux)
/*
* Macros to allow using the offset from the padconf physical address
projects / mirror_ubuntu-jammy-kernel.git / commitdiff