obj-y += e1000.o
# Hardware support
-obj-i386-y = pckbd.o dma.o
+obj-i386-y = dma.o
obj-i386-y += vga.o
obj-i386-y += mc146818rtc.o i8259.o pc.o
obj-i386-y += cirrus_vga.o apic.o ioapic.o piix_pci.o
obj-ppc-y = ppc.o
obj-ppc-y += vga.o dma.o
# PREP target
-obj-ppc-y += pckbd.o i8259.o mc146818rtc.o
+obj-ppc-y += i8259.o mc146818rtc.o
obj-ppc-y += ppc_prep.o
# OldWorld PowerMac
obj-ppc-y += ppc_oldworld.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
obj-mips-y += dma.o vga.o i8259.o
obj-mips-y += g364fb.o jazz_led.o
-obj-mips-y += gt64xxx.o pckbd.o mc146818rtc.o
+obj-mips-y += gt64xxx.o mc146818rtc.o
obj-mips-y += piix4.o cirrus_vga.o
obj-microblaze-y = petalogix_s3adsp1800_mmu.o
obj-cris-y += etraxfs_ser.o
ifeq ($(TARGET_ARCH), sparc64)
-obj-sparc-y = sun4u.o pckbd.o apb_pci.o
+obj-sparc-y = sun4u.o apb_pci.o
obj-sparc-y += vga.o
obj-sparc-y += mc146818rtc.o
obj-sparc-y += cirrus_vga.o
rtc_set_memory(s, 0x39, val);
}
-void ioport_set_a20(int enable)
+static void handle_a20_line_change(void *opaque, int irq, int level)
{
- /* XXX: send to all CPUs ? */
- cpu_x86_set_a20(first_cpu, enable);
-}
-
-int ioport_get_a20(void)
-{
- return ((first_cpu->a20_mask >> 20) & 1);
-}
-
-static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
-{
- ioport_set_a20((val >> 1) & 1);
- /* XXX: bit 0 is fast reset */
-}
+ CPUState *cpu = opaque;
-static uint32_t ioport92_read(void *opaque, uint32_t addr)
-{
- return ioport_get_a20() << 1;
+ /* XXX: send to all CPUs ? */
+ cpu_x86_set_a20(cpu, level);
}
/***********************************************************/
int i;
DriveInfo *fd[MAX_FD];
PITState *pit;
+ qemu_irq *a20_line;
+ ISADevice *i8042;
register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
qemu_register_boot_set(pc_boot_set, *rtc_state);
- register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
- register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
-
pit = pit_init(0x40, isa_reserve_irq(0));
pcspk_init(pit);
if (!no_hpet) {
}
}
- isa_create_simple("i8042");
+ a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
+ i8042 = isa_create_simple("i8042");
+ i8042_setup_a20_line(i8042, a20_line);
+ vmmouse_init(i8042);
+
DMA_init(0);
for(i = 0; i < MAX_FD; i++) {
#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
#define KBD_MODE_RFU 0x80
+/* Output Port Bits */
+#define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
+#define KBD_OUT_A20 0x02 /* x86 only */
+#define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
+#define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
+
/* Mouse Commands */
#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
uint8_t status;
uint8_t mode;
+ uint8_t outport;
/* Bitmask of devices with data available. */
uint8_t pending;
void *kbd;
qemu_irq irq_kbd;
qemu_irq irq_mouse;
+ qemu_irq *a20_out;
target_phys_addr_t mask;
} KBDState;
irq_kbd_level = 0;
irq_mouse_level = 0;
s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
+ s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
if (s->pending) {
s->status |= KBD_STAT_OBF;
+ s->outport |= KBD_OUT_OBF;
/* kbd data takes priority over aux data. */
if (s->pending == KBD_PENDING_AUX) {
s->status |= KBD_STAT_MOUSE_OBF;
+ s->outport |= KBD_OUT_MOUSE_OBF;
if (s->mode & KBD_MODE_MOUSE_INT)
irq_mouse_level = 1;
} else {
ps2_queue(s->kbd, b);
}
+static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ KBDState *s = opaque;
+
+ s->outport = val;
+ if (s->a20_out) {
+ qemu_set_irq(*s->a20_out, (val >> 1) & 1);
+ }
+ if (!(val & 1)) {
+ qemu_system_reset_request();
+ }
+}
+
+static uint32_t ioport92_read(void *opaque, uint32_t addr)
+{
+ KBDState *s = opaque;
+
+ return s->outport;
+}
+
static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
{
KBDState *s = opaque;
kbd_queue(s, 0x00, 0);
break;
case KBD_CCMD_READ_OUTPORT:
- /* XXX: check that */
-#ifdef TARGET_I386
- val = 0x01 | (ioport_get_a20() << 1);
-#else
- val = 0x01;
-#endif
- if (s->status & KBD_STAT_OBF)
- val |= 0x10;
- if (s->status & KBD_STAT_MOUSE_OBF)
- val |= 0x20;
- kbd_queue(s, val, 0);
+ kbd_queue(s, s->outport, 0);
break;
-#ifdef TARGET_I386
case KBD_CCMD_ENABLE_A20:
- ioport_set_a20(1);
+ if (s->a20_out) {
+ qemu_irq_raise(*s->a20_out);
+ }
+ s->outport |= KBD_OUT_A20;
break;
case KBD_CCMD_DISABLE_A20:
- ioport_set_a20(0);
+ if (s->a20_out) {
+ qemu_irq_lower(*s->a20_out);
+ }
+ s->outport &= ~KBD_OUT_A20;
break;
-#endif
case KBD_CCMD_RESET:
qemu_system_reset_request();
break;
kbd_queue(s, val, 1);
break;
case KBD_CCMD_WRITE_OUTPORT:
-#ifdef TARGET_I386
- ioport_set_a20((val >> 1) & 1);
-#endif
- if (!(val & 1)) {
- qemu_system_reset_request();
- }
+ ioport92_write(s, 0, val);
break;
case KBD_CCMD_WRITE_MOUSE:
ps2_write_mouse(s->mouse, val);
s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
+ s->outport = KBD_OUT_RESET | KBD_OUT_A20;
}
static const VMStateDescription vmstate_kbd = {
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
-#ifdef TARGET_I386
- vmmouse_init(s->mouse);
-#endif
qemu_register_reset(kbd_reset, s);
}
KBDState kbd;
} ISAKBDState;
+void i8042_isa_mouse_fake_event(void *opaque)
+{
+ ISADevice *dev = opaque;
+ KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
+
+ ps2_mouse_fake_event(s->mouse);
+}
+
+void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out)
+{
+ KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
+
+ s->a20_out = a20_out;
+}
+
static const VMStateDescription vmstate_kbd_isa = {
.name = "pckbd",
.version_id = 3,
register_ioport_write(0x60, 1, 1, kbd_write_data, s);
register_ioport_read(0x64, 1, 1, kbd_read_status, s);
register_ioport_write(0x64, 1, 1, kbd_write_command, s);
+ register_ioport_read(0x92, 1, 1, ioport92_read, s);
+ register_ioport_write(0x92, 1, 1, ioport92_write, s);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
-#ifdef TARGET_I386
- vmmouse_init(s->mouse);
-#endif
qemu_register_reset(kbd_reset, s);
return 0;
}
projects / qemu.git / commitdiff