drm/i915/display: Move feature test macros to intel_display_device.h

It makes sense to keep the display feature test macros centralized
within the display code.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230523195609.73627-7-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index d1d11581d85dc6fbd95b4e1e724659ad685412d8..2aa82cbdf1c5396aef9b5608ff8a66cb451c0518 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -31,6 +31,45 @@ struct drm_i915_private;
        func(overlay_needs_physical); \
        func(supports_tv);
 
+#define HAS_ASYNC_FLIPS(i915)          (DISPLAY_VER(i915) >= 5)
+#define HAS_CDCLK_CRAWL(i915)          (DISPLAY_INFO(i915)->has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(i915)         (DISPLAY_INFO(i915)->has_cdclk_squash)
+#define HAS_CUR_FBC(i915)              (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
+#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
+#define HAS_DDI(i915)                  (DISPLAY_INFO(i915)->has_ddi)
+#define HAS_DISPLAY(i915)              (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
+#define HAS_DMC(i915)                  (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
+#define HAS_DOUBLE_BUFFERED_M_N(i915)  (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
+#define HAS_DP_MST(i915)               (DISPLAY_INFO(i915)->has_dp_mst)
+#define HAS_DP20(i915)                 (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
+#define HAS_DPT(i915)                  (DISPLAY_VER(i915) >= 13)
+#define HAS_DSB(i915)                  (DISPLAY_INFO(i915)->has_dsb)
+#define HAS_DSC(__i915)                        (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
+#define HAS_FBC(i915)                  (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
+#define HAS_FPGA_DBG_UNCLAIMED(i915)   (DISPLAY_INFO(i915)->has_fpga_dbg)
+#define HAS_FW_BLC(i915)               (DISPLAY_VER(i915) > 2)
+#define HAS_GMBUS_IRQ(i915)            (DISPLAY_VER(i915) >= 4)
+#define HAS_GMBUS_BURST_READ(i915)     (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
+#define HAS_GMCH(i915)                 (DISPLAY_INFO(i915)->has_gmch)
+#define HAS_HW_SAGV_WM(i915)           (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
+#define HAS_IPC(i915)                  (DISPLAY_INFO(i915)->has_ipc)
+#define HAS_IPS(i915)                  (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
+#define HAS_LSPCON(i915)               (IS_DISPLAY_VER(i915, 9, 10))
+#define HAS_MBUS_JOINING(i915)         (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
+#define HAS_MSO(i915)                  (DISPLAY_VER(i915) >= 12)
+#define HAS_OVERLAY(i915)              (DISPLAY_INFO(i915)->has_overlay)
+#define HAS_PSR(i915)                  (DISPLAY_INFO(i915)->has_psr)
+#define HAS_PSR_HW_TRACKING(i915)      (DISPLAY_INFO(i915)->has_psr_hw_tracking)
+#define HAS_PSR2_SEL_FETCH(i915)       (DISPLAY_VER(i915) >= 12)
+#define HAS_SAGV(i915)                 (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
+#define HAS_TRANSCODER(i915, trans)    ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
+                                         BIT(trans)) != 0)
+#define HAS_VRR(i915)                  (DISPLAY_VER(i915) >= 11)
+#define INTEL_NUM_PIPES(i915)          (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
+#define I915_HAS_HOTPLUG(i915)         (DISPLAY_INFO(i915)->has_hotplug)
+#define OVERLAY_NEEDS_PHYSICAL(i915)   (DISPLAY_INFO(i915)->overlay_needs_physical)
+#define SUPPORTS_TV(i915)              (DISPLAY_INFO(i915)->supports_tv)
+
 struct intel_display_runtime_info {
        struct {
                u16 ver;

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dbdecf1ee24feb4e8f649f818565d317788845c2..e9c403def9c93d6aa2095fc8773cc5d922af8d77 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -785,10 +785,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
        ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
 })
 
-#define HAS_OVERLAY(dev_priv)           (DISPLAY_INFO(dev_priv)->has_overlay)
-#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
-               (DISPLAY_INFO(dev_priv)->overlay_needs_physical)
-
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(dev_priv)    (IS_I830(dev_priv) || IS_I845G(dev_priv))
 
@@ -799,41 +795,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                   \
        (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 
-#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
-#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
-                                       IS_GEMINILAKE(dev_priv) || \
-                                       IS_KABYLAKE(dev_priv))
-
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
  */
 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
                                         !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev_priv)          (DISPLAY_INFO(dev_priv)->supports_tv)
-#define I915_HAS_HOTPLUG(dev_priv)     (DISPLAY_INFO(dev_priv)->has_hotplug)
-
-#define HAS_FW_BLC(dev_priv)   (DISPLAY_VER(dev_priv) > 2)
-#define HAS_FBC(dev_priv)      (DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask != 0)
-#define HAS_CUR_FBC(dev_priv)  (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
-
-#define HAS_DPT(dev_priv)      (DISPLAY_VER(dev_priv) >= 13)
-
-#define HAS_IPS(dev_priv)      (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 
-#define HAS_DP_MST(dev_priv)   (DISPLAY_INFO(dev_priv)->has_dp_mst)
-#define HAS_DP20(dev_priv)     (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
-
-#define HAS_DOUBLE_BUFFERED_M_N(dev_priv)      (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
-
-#define HAS_CDCLK_CRAWL(dev_priv)       (DISPLAY_INFO(dev_priv)->has_cdclk_crawl)
-#define HAS_CDCLK_SQUASH(dev_priv)      (DISPLAY_INFO(dev_priv)->has_cdclk_squash)
-#define HAS_DDI(dev_priv)               (DISPLAY_INFO(dev_priv)->has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (DISPLAY_INFO(dev_priv)->has_fpga_dbg)
-#define HAS_PSR(dev_priv)               (DISPLAY_INFO(dev_priv)->has_psr)
-#define HAS_PSR_HW_TRACKING(dev_priv) \
-       (DISPLAY_INFO(dev_priv)->has_psr_hw_tracking)
-#define HAS_PSR2_SEL_FETCH(dev_priv)    (DISPLAY_VER(dev_priv) >= 12)
-#define HAS_TRANSCODER(dev_priv, trans)         ((DISPLAY_RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 
 #define HAS_RC6(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6)
 #define HAS_RC6p(dev_priv)              (INTEL_INFO(dev_priv)->has_rc6p)
@@ -841,11 +808,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_RPS(dev_priv)      (INTEL_INFO(dev_priv)->has_rps)
 
-#define HAS_DMC(dev_priv)      (DISPLAY_RUNTIME_INFO(dev_priv)->has_dmc)
-#define HAS_DSB(dev_priv)      (DISPLAY_INFO(dev_priv)->has_dsb)
-#define HAS_DSC(__i915)                (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
-#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-
 #define HAS_HECI_PXP(dev_priv) \
        (INTEL_INFO(dev_priv)->has_heci_pxp)
 
@@ -854,8 +816,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
 
-#define HAS_MSO(i915)          (DISPLAY_VER(i915) >= 12)
-
 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 
@@ -872,9 +832,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  */
 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 
-#define HAS_IPC(dev_priv)              (DISPLAY_INFO(dev_priv)->has_ipc)
-#define HAS_SAGV(dev_priv)             (DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv))
-
 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
 
@@ -892,12 +849,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)    (INTEL_INFO(dev_priv)->has_global_mocs)
 
-#define HAS_GMCH(dev_priv) (DISPLAY_INFO(dev_priv)->has_gmch)
-
 #define HAS_GMD_ID(i915)       (INTEL_INFO(i915)->has_gmd_id)
 
-#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
-
 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
 
 /* DPF == dynamic parity feature */
@@ -905,14 +858,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
                                 2 : HAS_L3_DPF(dev_priv))
 
-#define INTEL_NUM_PIPES(dev_priv) (hweight8(DISPLAY_RUNTIME_INFO(dev_priv)->pipe_mask))
-
-#define HAS_DISPLAY(dev_priv) (DISPLAY_RUNTIME_INFO(dev_priv)->pipe_mask != 0)
-
-#define HAS_VRR(i915)  (DISPLAY_VER(i915) >= 11)
-
-#define HAS_ASYNC_FLIPS(i915)          (DISPLAY_VER(i915) >= 5)
-
 /* Only valid when HAS_DISPLAY() is true */
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
        (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),         \
@@ -922,11 +867,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
        (INTEL_INFO(dev_priv)->has_guc_deprivilege)
 
-#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
-                                             IS_ALDERLAKE_S(dev_priv))
-
-#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
-
 #define HAS_3D_PIPELINE(i915)  (INTEL_INFO(i915)->has_3d_pipeline)
 
 #define HAS_ONE_EU_PER_FUSE_BIT(i915)  (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)