drm/amdgpu: Update pitch on page flips without DC as well

DC already handles this correctly since amdgpu minor version 31. Bump
the minor version again so that xf86-video-amdgpu can take advantage of
this working without DC as well now.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e9046922fe940c201a2cce5a33b17226b0887aac..35d44c3473d782ed4437286e61bea329d1e224aa 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -79,9 +79,10 @@
  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
+ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
  */
 #define KMS_DRIVER_MAJOR       3
-#define KMS_DRIVER_MINOR       33
+#define KMS_DRIVER_MINOR       34
 #define KMS_DRIVER_PATCHLEVEL  0
 
 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 1ffd1963e765b94013d5e2dbbaa459f1be477724..645550e7caf5183cf193bb4fb8afaf04a7d02405 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -236,6 +236,7 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
                                int crtc_id, u64 crtc_base, bool async)
 {
        struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
        u32 tmp;
 
        /* flip at hsync for async, default is vsync */
@@ -243,6 +244,9 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
        tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
                            GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
        WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+       /* update pitch */
+       WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+              fb->pitches[0] / fb->format->cpp[0]);
        /* update the primary scanout address */
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(crtc_base));

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 9e0782b540665ae816c5e1012fe35f85ada4867c..d9f470632b2ca1682a7c64c8004e2eb9a33a1849 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -254,6 +254,7 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
                                int crtc_id, u64 crtc_base, bool async)
 {
        struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
        u32 tmp;
 
        /* flip immediate for async, default is vsync */
@@ -261,6 +262,9 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
        tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
                            GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
        WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+       /* update pitch */
+       WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+              fb->pitches[0] / fb->format->cpp[0]);
        /* update the scanout addresses */
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(crtc_base));

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 4bf453e07dca775aa017d185618ba9b7b81aaedf..3eb2e74292697325c7539efea0755b2970494115 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -191,10 +191,14 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
                               int crtc_id, u64 crtc_base, bool async)
 {
        struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
 
        /* flip at hsync for async, default is vsync */
        WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
               GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
+       /* update pitch */
+       WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+              fb->pitches[0] / fb->format->cpp[0]);
        /* update the scanout addresses */
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(crtc_base));

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index b23418ca8f6ae7bbf9773131b21baf3cb3f4a273..a16c5e9e610e766ebd55c3f90b3ab68df0e96dcf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -184,10 +184,14 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev,
                               int crtc_id, u64 crtc_base, bool async)
 {
        struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
 
        /* flip at hsync for async, default is vsync */
        WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
               GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
+       /* update pitch */
+       WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+              fb->pitches[0] / fb->format->cpp[0]);
        /* update the primary scanout addresses */
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(crtc_base));