drm/i915: Move swizzle_bit under i915_ggtt

The HW performs swizzling as part of its fence tiling inside the Global
GTT. We already do the probing of the HW settings from the GGTT setup,
complete the picture by storing the information as part of the GGTT. The
primary benefit is the consistency of our probe routines do not break
the i915_ggtt encapsulation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191016143234.4075-2-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index dc2a83ce44d52537ad5b491238c427cff8c85129..1fa592d82af539319140dcf94ca66416862f0425 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -348,9 +348,9 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
                args->stride = 0;
        } else {
                if (args->tiling_mode == I915_TILING_X)
-                       args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_x;
+                       args->swizzle_mode = to_i915(dev)->ggtt.bit_6_swizzle_x;
                else
-                       args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_y;
+                       args->swizzle_mode = to_i915(dev)->ggtt.bit_6_swizzle_y;
 
                /* Hide bit 17 swizzling from the user.  This prevents old Mesa
                 * from aborting the application on sw fallbacks to bit 17,
@@ -421,10 +421,10 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 
        switch (args->tiling_mode) {
        case I915_TILING_X:
-               args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
+               args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_x;
                break;
        case I915_TILING_Y:
-               args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
+               args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_y;
                break;
        default:
        case I915_TILING_NONE:

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index cfa52c525691c3ec6d613b2d101dd955aa365aee..65d4dbf919996a1442ee199cf8f2662f173605cf 100644 (file)
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -357,10 +357,10 @@ static int igt_partial_tiling(void *arg)
                tile.tiling = tiling;
                switch (tiling) {
                case I915_TILING_X:
-                       tile.swizzle = i915->mm.bit_6_swizzle_x;
+                       tile.swizzle = i915->ggtt.bit_6_swizzle_x;
                        break;
                case I915_TILING_Y:
-                       tile.swizzle = i915->mm.bit_6_swizzle_y;
+                       tile.swizzle = i915->ggtt.bit_6_swizzle_y;
                        break;
                }
 
@@ -474,10 +474,10 @@ static int igt_smoke_tiling(void *arg)
                        break;
 
                case I915_TILING_X:
-                       tile.swizzle = i915->mm.bit_6_swizzle_x;
+                       tile.swizzle = i915->ggtt.bit_6_swizzle_x;
                        break;
                case I915_TILING_Y:
-                       tile.swizzle = i915->mm.bit_6_swizzle_y;
+                       tile.swizzle = i915->ggtt.bit_6_swizzle_y;
                        break;
                }
 

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a541b6ae534fa76593c69ed9459a092d3c409945..ada57eee914a5023a341768f3b6d3187f3ea9908 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1660,9 +1660,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
        wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
        seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
-                  swizzle_string(dev_priv->mm.bit_6_swizzle_x));
+                  swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
        seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
-                  swizzle_string(dev_priv->mm.bit_6_swizzle_y));
+                  swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
 
        if (IS_GEN_RANGE(dev_priv, 3, 4)) {
                seq_printf(m, "DDC = 0x%08x\n",

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f6aee1e01a7fafb6fffc24f877c24c70f6068ee7..88956f37d96c59ee74b697994589aba8ccaabcff 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -695,11 +695,6 @@ struct i915_gem_mm {
         */
        struct workqueue_struct *userptr_wq;
 
-       /** Bit 6 swizzling required for X tiling */
-       u32 bit_6_swizzle_x;
-       /** Bit 6 swizzling required for Y tiling */
-       u32 bit_6_swizzle_y;
-
        /* shrinker accounting, also useful for userland debugging */
        u64 shrink_memory;
        u32 shrink_count;
@@ -2014,9 +2009,9 @@ i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
 /* i915_gem_tiling.c */
 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 {
-       struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+       struct drm_i915_private *i915 = to_i915(obj->base.dev);
 
-       return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
+       return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
                i915_gem_object_is_tiled(obj);
 }
 

diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 83b450d9ce84adac28e1db6a24713b4477d88862..321189e1b0f2990b64793cd720fa1e28740e32c6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -564,14 +564,15 @@ void i915_gem_restore_fences(struct i915_ggtt *ggtt)
 
 /**
  * detect_bit_6_swizzle - detect bit 6 swizzling pattern
- * @i915: i915 device private
+ * @ggtt: Global GGTT
  *
  * Detects bit 6 swizzling of address lookup between IGD access and CPU
  * access through main memory.
  */
-static void detect_bit_6_swizzle(struct drm_i915_private *i915)
+static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 {
-       struct intel_uncore *uncore = &i915->uncore;
+       struct intel_uncore *uncore = ggtt->vm.gt->uncore;
+       struct drm_i915_private *i915 = ggtt->vm.i915;
        u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
        u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
@@ -733,8 +734,8 @@ static void detect_bit_6_swizzle(struct drm_i915_private *i915)
                swizzle_y = I915_BIT_6_SWIZZLE_NONE;
        }
 
-       i915->mm.bit_6_swizzle_x = swizzle_x;
-       i915->mm.bit_6_swizzle_y = swizzle_y;
+       i915->ggtt.bit_6_swizzle_x = swizzle_x;
+       i915->ggtt.bit_6_swizzle_y = swizzle_y;
 }
 
 /*
@@ -843,7 +844,7 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
        INIT_LIST_HEAD(&ggtt->userfault_list);
        intel_wakeref_auto_init(&ggtt->userfault_wakeref, uncore->rpm);
 
-       detect_bit_6_swizzle(i915);
+       detect_bit_6_swizzle(ggtt);
 
        if (INTEL_GEN(i915) >= 7 &&
            !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
@@ -878,7 +879,7 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
        struct intel_uncore *uncore = gt->uncore;
 
        if (INTEL_GEN(i915) < 5 ||
-           i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+           i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
                return;
 
        intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 0a18fdfe63ff0c5f1622f8c35171e8a207af3a8a..f074f1de66e87e138ffb1735b2244b00693cdad5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -411,6 +411,11 @@ struct i915_ggtt {
 
        int mtrr;
 
+       /** Bit 6 swizzling required for X tiling */
+       u32 bit_6_swizzle_x;
+       /** Bit 6 swizzling required for Y tiling */
+       u32 bit_6_swizzle_y;
+
        u32 pin_bias;
 
        unsigned int num_fences;