staging: spmi: hisi-spmi-controller: adjust whitespaces at defines

Some defines are not aligned with tab=8, which is the
style defined on Linux. Adjust them.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/4a3799b40379dbc3abcbd08827977247ccc26dcb.1597647359.git.mchehab+huawei@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/hikey9xx/hisi-spmi-controller.c b/drivers/staging/hikey9xx/hisi-spmi-controller.c
index 99cf757d76fe59b90a8594c4188f1a39e5f189a9..7fae267a60628ef71d1fef8a7bd3af58e3e6efd0 100644 (file)
--- a/drivers/staging/hikey9xx/hisi-spmi-controller.c
+++ b/drivers/staging/hikey9xx/hisi-spmi-controller.c
@@ -18,10 +18,10 @@
 /*
  * SPMI register addr
  */
-#define SPMI_CHANNEL_OFFSET                                    0x0300
-#define SPMI_SLAVE_OFFSET                                              0x20
+#define SPMI_CHANNEL_OFFSET                            0x0300
+#define SPMI_SLAVE_OFFSET                              0x20
 
-#define SPMI_APB_SPMI_CMD_BASE_ADDR                            0x0100
+#define SPMI_APB_SPMI_CMD_BASE_ADDR                    0x0100
 
 #define SPMI_APB_SPMI_WDATA0_BASE_ADDR                 0x0104
 #define SPMI_APB_SPMI_WDATA1_BASE_ADDR                 0x0108
@@ -35,21 +35,21 @@
 #define SPMI_APB_SPMI_RDATA2_BASE_ADDR                 0x020c
 #define SPMI_APB_SPMI_RDATA3_BASE_ADDR                 0x0210
 
-#define SPMI_PER_DATAREG_BYTE                                  4
+#define SPMI_PER_DATAREG_BYTE                          4
 /*
  * SPMI cmd register
  */
-#define SPMI_APB_SPMI_CMD_EN                                           BIT(31)
+#define SPMI_APB_SPMI_CMD_EN                           BIT(31)
 #define SPMI_APB_SPMI_CMD_TYPE_OFFSET                  24
 #define SPMI_APB_SPMI_CMD_LENGTH_OFFSET                        20
-#define SPMI_APB_SPMI_CMD_SLAVEID_OFFSET                       16
-#define SPMI_APB_SPMI_CMD_ADDR_OFFSET                          0
 
 #define bswap_32(X)   \
     ((((u32)(X) & 0xff000000) >> 24) | \
      (((u32)(X) & 0x00ff0000) >> 8) | \
      (((u32)(X) & 0x0000ff00) << 8) | \
      (((u32)(X) & 0x000000ff) << 24))
+#define SPMI_APB_SPMI_CMD_SLAVEID_OFFSET               16
+#define SPMI_APB_SPMI_CMD_ADDR_OFFSET                  0
 
 /* Command Opcodes */
 
@@ -70,15 +70,15 @@ enum spmi_controller_cmd_op_code {
 /*
  * SPMI status register
  */
-#define SPMI_APB_TRANS_DONE                                            BIT(0)
-#define SPMI_APB_TRANS_FAIL                                            BIT(2)
+#define SPMI_APB_TRANS_DONE                    BIT(0)
+#define SPMI_APB_TRANS_FAIL                    BIT(2)
 
 /* Command register fields */
 #define SPMI_CONTROLLER_CMD_MAX_BYTE_COUNT     16
 
 /* Maximum number of support PMIC peripherals */
 #define SPMI_CONTROLLER_TIMEOUT_US             1000
-#define SPMI_CONTROLLER_MAX_TRANS_BYTES        (16)
+#define SPMI_CONTROLLER_MAX_TRANS_BYTES                16
 
 /*
  * @base base address of the PMIC Arbiter core registers.
@@ -114,8 +114,10 @@ static int spmi_controller_wait_for_done(struct spmi_controller_dev *ctrl_dev,
 {
        u32 status = 0;
        u32 timeout = SPMI_CONTROLLER_TIMEOUT_US;
-       u32 offset = SPMI_APB_SPMI_STATUS_BASE_ADDR + SPMI_CHANNEL_OFFSET * ctrl_dev->channel
-               + SPMI_SLAVE_OFFSET * sid;
+       u32 offset;
+
+       offset  = SPMI_APB_SPMI_STATUS_BASE_ADDR;
+       offset += SPMI_CHANNEL_OFFSET * ctrl_dev->channel + SPMI_SLAVE_OFFSET * sid;
 
        while (timeout--) {
                status = readl(base + offset);