drm/amd/display: Cache edp config in dc link

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0144c98fd0d5e1b545a51e55b45c1b79d96cbbdf..d621237e923e08a2eb4e93838e764ddb78b5d8b2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2258,6 +2258,8 @@ static void retrieve_link_cap(struct dc_link *link)
                DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
        link->dpcd_caps.panel_mode_edp =
                edp_config_cap.bits.ALT_SCRAMBLER_RESET;
+       link->dpcd_caps.dpcd_display_control_capable =
+               edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
 
        link->test_pattern_enabled = false;
        link->compliance_test_state.raw = 0;

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 928d2a0501eb47f5abd7c853de9f02cae5321238..bd8b1ba22df8b99ef3c5fe5b519dae4aa50a1e52 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -760,6 +760,7 @@ struct dpcd_caps {
 
        bool allow_invalid_MSA_timing_param;
        bool panel_mode_edp;
+       bool dpcd_display_control_capable;
 };
 
 struct dc_link_status {
@@ -834,7 +835,6 @@ struct dc_link {
        struct dpcd_caps dpcd_caps;
        unsigned short chip_caps;
        unsigned int dpcd_sink_count;
-
        enum edp_revision edp_revision;
        bool psr_enabled;