ARM64: dts: meson: bump mali450 clk to 744MHz

The Mali-450 IP can run up to 744MHz, bump the frequency using
the GP0 PLL clock.

Cc: Michal Lazo <michal.lazo@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index cac72acb85b1a60d521414b2c8f62c842c42b997..562c26a0ba333ed2989351f1d854b0a20fcab042 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -247,14 +247,17 @@
                 * MALI_0 and MALI_1 muxed to a single clock by a glitch
                 * free mux to safely change frequency while running.
                 */
-               assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+               assigned-clocks = <&clkc CLKID_GP0_PLL>,
+                                 <&clkc CLKID_MALI_0_SEL>,
                                  <&clkc CLKID_MALI_0>,
                                  <&clkc CLKID_MALI>; /* Glitch free mux */
-               assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+               assigned-clock-parents = <0>, /* Do Nothing */
+                                        <&clkc CLKID_GP0_PLL>,
                                         <0>, /* Do Nothing */
                                         <&clkc CLKID_MALI_0>;
-               assigned-clock-rates = <0>, /* Do Nothing */
-                                      <666666666>,
+               assigned-clock-rates = <744000000>,
+                                      <0>, /* Do Nothing */
+                                      <744000000>,
                                       <0>; /* Do Nothing */
        };
 };

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
index f825506cdf64f00c8c9c2248fbd2f2ba958231bd..eb327664a4d8c38c196b7cec2dbbe5e5ac2c147f 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
@@ -29,14 +29,17 @@
                 * MALI_0 and MALI_1 muxed to a single clock by a glitch
                 * free mux to safely change frequency while running.
                 */
-               assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+               assigned-clocks = <&clkc CLKID_GP0_PLL>,
+                                 <&clkc CLKID_MALI_0_SEL>,
                                  <&clkc CLKID_MALI_0>,
                                  <&clkc CLKID_MALI>; /* Glitch free mux */
-               assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+               assigned-clock-parents = <0>, /* Do Nothing */
+                                        <&clkc CLKID_GP0_PLL>,
                                         <0>, /* Do Nothing */
                                         <&clkc CLKID_MALI_0>;
-               assigned-clock-rates = <0>, /* Do Nothing */
-                                      <666666666>,
+               assigned-clock-rates = <744000000>,
+                                      <0>, /* Do Nothing */
+                                      <744000000>,
                                       <0>; /* Do Nothing */
        };
 };