amd-xgbe: Prepare for more fine grained cache coherency controls

In prep for setting fine grained read and write DMA cache coherency
controls, allow specific values to be used to set the cache coherency
registers.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
index e7b68043d6277b433fbe7141d4994023eae10523..dc098832e0fee43fc4ba8a459074ca55569ecbad 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
@@ -127,34 +127,6 @@
 #define DMA_DSR1                       0x3024
 
 /* DMA register entry bit positions and sizes */
-#define DMA_AXIARCR_DRC_INDEX          0
-#define DMA_AXIARCR_DRC_WIDTH          4
-#define DMA_AXIARCR_DRD_INDEX          4
-#define DMA_AXIARCR_DRD_WIDTH          2
-#define DMA_AXIARCR_TEC_INDEX          8
-#define DMA_AXIARCR_TEC_WIDTH          4
-#define DMA_AXIARCR_TED_INDEX          12
-#define DMA_AXIARCR_TED_WIDTH          2
-#define DMA_AXIARCR_THC_INDEX          16
-#define DMA_AXIARCR_THC_WIDTH          4
-#define DMA_AXIARCR_THD_INDEX          20
-#define DMA_AXIARCR_THD_WIDTH          2
-#define DMA_AXIAWCR_DWC_INDEX          0
-#define DMA_AXIAWCR_DWC_WIDTH          4
-#define DMA_AXIAWCR_DWD_INDEX          4
-#define DMA_AXIAWCR_DWD_WIDTH          2
-#define DMA_AXIAWCR_RPC_INDEX          8
-#define DMA_AXIAWCR_RPC_WIDTH          4
-#define DMA_AXIAWCR_RPD_INDEX          12
-#define DMA_AXIAWCR_RPD_WIDTH          2
-#define DMA_AXIAWCR_RHC_INDEX          16
-#define DMA_AXIAWCR_RHC_WIDTH          4
-#define DMA_AXIAWCR_RHD_INDEX          20
-#define DMA_AXIAWCR_RHD_WIDTH          2
-#define DMA_AXIAWCR_TDC_INDEX          24
-#define DMA_AXIAWCR_TDC_WIDTH          4
-#define DMA_AXIAWCR_TDD_INDEX          28
-#define DMA_AXIAWCR_TDD_WIDTH          2
 #define DMA_ISR_MACIS_INDEX            17
 #define DMA_ISR_MACIS_WIDTH            1
 #define DMA_ISR_MTLIS_INDEX            16

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index b05393f0ff0aa2386abf0207897a32378f24460d..98da24964f1f7e3234f68faa718e3ab69bd13904 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -2146,27 +2146,8 @@ static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
 
 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
 {
-       unsigned int arcache, awcache;
-
-       arcache = 0;
-       XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
-       XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
-       XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
-       XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
-       XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
-       XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
-       XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
-
-       awcache = 0;
-       XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
-       XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
-       XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
-       XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
-       XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
-       XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
-       XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
-       XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
-       XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
+       XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr);
+       XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr);
 }
 
 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
index f0c2e88a5037b6e80beae0365d4b7de33056d713..1e73768875684f11b47f3667997c97ea9e360498 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -327,9 +327,8 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 
        /* Set the DMA coherency values */
        pdata->coherent = 1;
-       pdata->axdomain = XGBE_DMA_OS_AXDOMAIN;
-       pdata->arcache = XGBE_DMA_OS_ARCACHE;
-       pdata->awcache = XGBE_DMA_OS_AWCACHE;
+       pdata->arcr = XGBE_DMA_OS_ARCR;
+       pdata->awcr = XGBE_DMA_OS_AWCR;
 
        /* Set the maximum channels and queues */
        reg = XP_IOREAD(pdata, XP_PROP_1);

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-platform.c b/drivers/net/ethernet/amd/xgbe/xgbe-platform.c
index 84d4c51cab8c352bcff37647b46649a131fd38ca..d0f3dfb88202966d315d4ec5bf20b7f8fcf02abe 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-platform.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-platform.c
@@ -448,13 +448,11 @@ static int xgbe_platform_probe(struct platform_device *pdev)
        }
        pdata->coherent = (attr == DEV_DMA_COHERENT);
        if (pdata->coherent) {
-               pdata->axdomain = XGBE_DMA_OS_AXDOMAIN;
-               pdata->arcache = XGBE_DMA_OS_ARCACHE;
-               pdata->awcache = XGBE_DMA_OS_AWCACHE;
+               pdata->arcr = XGBE_DMA_OS_ARCR;
+               pdata->awcr = XGBE_DMA_OS_AWCR;
        } else {
-               pdata->axdomain = XGBE_DMA_SYS_AXDOMAIN;
-               pdata->arcache = XGBE_DMA_SYS_ARCACHE;
-               pdata->awcache = XGBE_DMA_SYS_AWCACHE;
+               pdata->arcr = XGBE_DMA_SYS_ARCR;
+               pdata->awcr = XGBE_DMA_SYS_AWCR;
        }
 
        /* Set the maximum fifo amounts */

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index 7b50469c77a0eff1acd94a2f35b047c5d46bf4ce..46780aa74301e1e061b141bf0840883b498a5dea 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -164,14 +164,12 @@
 #define XGBE_DMA_STOP_TIMEOUT  1
 
 /* DMA cache settings - Outer sharable, write-back, write-allocate */
-#define XGBE_DMA_OS_AXDOMAIN   0x2
-#define XGBE_DMA_OS_ARCACHE    0xb
-#define XGBE_DMA_OS_AWCACHE    0xf
+#define XGBE_DMA_OS_ARCR       0x002b2b2b
+#define XGBE_DMA_OS_AWCR       0x2f2f2f2f
 
 /* DMA cache settings - System, no caches used */
-#define XGBE_DMA_SYS_AXDOMAIN  0x3
-#define XGBE_DMA_SYS_ARCACHE   0x0
-#define XGBE_DMA_SYS_AWCACHE   0x0
+#define XGBE_DMA_SYS_ARCR      0x00303030
+#define XGBE_DMA_SYS_AWCR      0x30303030
 
 /* DMA channel interrupt modes */
 #define XGBE_IRQ_MODE_EDGE     0
@@ -1007,9 +1005,8 @@ struct xgbe_prv_data {
 
        /* AXI DMA settings */
        unsigned int coherent;
-       unsigned int axdomain;
-       unsigned int arcache;
-       unsigned int awcache;
+       unsigned int arcr;
+       unsigned int awcr;
 
        /* Service routine support */
        struct workqueue_struct *dev_workqueue;