PCI: rockchip: Use u32 variable to access 32-bit registers

BugLink: https://bugs.launchpad.net/bugs/2036075
commit 8962b2cb39119cbda4fc69a1f83957824f102f81 upstream.

Previously u16 variables were used to access 32-bit registers, this
resulted in not all of the data being read from the registers. Also
the left shift of more than 16-bits would result in moving data out
of the variable. Use u32 variables to access 32-bit registers

Link: https://lore.kernel.org/r/20230418074700.1083505-10-rick.wertenbroek@gmail.com
Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
Tested-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index 0186cc13d71e9343b05854b1570ac87d8b1b0d30..f914075a8d3df175232c34826e83834cfbc64256 100644 (file)
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -314,15 +314,15 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
 {
        struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
        struct rockchip_pcie *rockchip = &ep->rockchip;
-       u16 flags;
+       u32 flags;
 
        flags = rockchip_pcie_read(rockchip,
                                   ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
                                   ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
        flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
        flags |=
-          ((multi_msg_cap << 1) <<  ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
-          PCI_MSI_FLAGS_64BIT;
+          (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
+          (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET);
        flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
        rockchip_pcie_write(rockchip, flags,
                            ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
@@ -334,7 +334,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
 {
        struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
        struct rockchip_pcie *rockchip = &ep->rockchip;
-       u16 flags;
+       u32 flags;
 
        flags = rockchip_pcie_read(rockchip,
                                   ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
@@ -395,7 +395,7 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
                                         u8 interrupt_num)
 {
        struct rockchip_pcie *rockchip = &ep->rockchip;
-       u16 flags, mme, data, data_mask;
+       u32 flags, mme, data, data_mask;
        u8 msi_count;
        u64 pci_addr, pci_addr_mask = 0xff;
 

diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index ffc68a3a5fee133d62b077f20bb5c569e7f922ae..8e92dc3339ecc7df87ef372437f3900815bb49eb 100644 (file)
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -225,6 +225,7 @@
 #define ROCKCHIP_PCIE_EP_CMD_STATUS                    0x4
 #define   ROCKCHIP_PCIE_EP_CMD_STATUS_IS               BIT(19)
 #define ROCKCHIP_PCIE_EP_MSI_CTRL_REG                  0x90
+#define   ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET            16
 #define   ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET         17
 #define   ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK           GENMASK(19, 17)
 #define   ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET         20