LAN8720 needs a reset of every clock enable. The reset needs
to be done at device level, due the flag PHY_RST_AFTER_CLK_EN.
So, add phy-handle by creating mdio child node inside fec.
This will eventually move the phy-reset-gpio which is defined
in fec node.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
phy-mode = "rmii";
+ phy-handle = <ð_phy>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <4000>;
+ reset-deassert-us = <4000>;
+ };
+ };
};
&gpmi {