clk: tegra: Add support for OSC_DIV fixed clocks

Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks
from the OSC pads.

This patch adds support for these clocks.

Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index c4faebd3276070c799c052616645880528b61262..17d8b252cd0a73650522fc057e60aa7b3cadf011 100644 (file)
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -46,6 +46,8 @@ enum clk_id {
        tegra_clk_clk_m,
        tegra_clk_clk_m_div2,
        tegra_clk_clk_m_div4,
+       tegra_clk_osc_div2,
+       tegra_clk_osc_div4,
        tegra_clk_clk_out_1,
        tegra_clk_clk_out_1_mux,
        tegra_clk_clk_out_2,

diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
index 7c6c8abfcde655620815cea83200d7e39328d1ba..990106391334cc6e2ed29da931be93f0edfeddeb 100644 (file)
--- a/drivers/clk/tegra/clk-tegra-fixed.c
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -48,6 +48,22 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
 
        osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
 
+       /* osc_div2 */
+       dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
+       if (dt_clk) {
+               clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
+                                               0, 1, 2);
+               *dt_clk = clk;
+       }
+
+       /* osc_div4 */
+       dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
+       if (dt_clk) {
+               clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
+                                               0, 1, 4);
+               *dt_clk = clk;
+       }
+
        dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
        if (!dt_clk)
                return 0;

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 4efcaaf51b3acf94a8389c7ed2a199f4fda3f747..d44cb8db0ef608c4c391beeeead814c39e58e677 100644 (file)
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -737,6 +737,8 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
        [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
        [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
        [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
+       [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
+       [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
        [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
        [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
        [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
@@ -817,6 +819,8 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
        { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
        { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
+       { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
+       { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
        { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
        { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
        { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index b3110d5b5a6cc4c5d29149108915a88be6645467..32f3dd1ccbadf3c77d3f6010fe215ebd2f490a99 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -862,6 +862,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
        [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
        [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
        [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
+       [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
+       [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
        [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
        [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
        [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
@@ -943,6 +945,8 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
        { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
        { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
+       { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
+       { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
        { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
        { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
        { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 762cd186f7141bff0f6181cdfd040af5019c1b8c..899d8ca68c4f100aa381c2c1a96d3482adfefeb0 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2373,6 +2373,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
        [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
        [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
        [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
+       [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
+       [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
        [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
        [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
        [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
@@ -2499,6 +2501,8 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
        { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
        { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
+       { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
+       { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
        { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
        { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
        { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index b20891489e11b6da5a46745b3b08a7dc31071023..7e62d9ae377c6f0780dd15cc6034d04e24d0ca78 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -583,6 +583,8 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
        { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
        { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
+       { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
+       { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
        { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
        { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
        { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
@@ -685,6 +687,8 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
        [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
        [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
        [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
+       [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
+       [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
        [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
        [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
        [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },