mmc: sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for...

SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms

Signed-off-by: Vincent Wan <vincent.wan@amd.com>
Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Tested-by: Vikram B <vikram.b@amd.com>
Tested-by: Raghavendra Swamy <raghavendra.swamy@amd.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f895ab07fcc2a43faaa8ac7aa841951e9b3fe17f..a743d5227eda10eca2f3b65097ea5c8b13388616 100644 (file)
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -915,10 +915,15 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
        struct mmc_data *data = cmd->data;
 
        if (data == NULL) {
+               if (host->quirks2 &
+                       SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
+                       sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
+               } else {
                /* clear Auto CMD settings for no data CMDs */
-               mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
-               sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
+                       mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
+                       sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
                                SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
+               }
                return;
        }
 

diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 931ac5e0545358bd2e5cfc9c06452cbcb4361df4..ae7f357b78c9c4257ddd2d3ce3d74729deafffc0 100644 (file)
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -102,6 +102,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_STOP_WITH_TC                      (1<<8)
 /* Controller does not support 64-bit DMA */
 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA                 (1<<9)
+/* need clear transfer mode register before send cmd */
+#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
 
        int irq;                /* Device IRQ */
        void __iomem *ioaddr;   /* Mapped address */