]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
drm/i915/gt: Use the RPM config register to determine clk frequencies
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 24 Apr 2020 16:28:05 +0000 (17:28 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 24 Apr 2020 18:10:17 +0000 (19:10 +0100)
For many configuration details within RC6 and RPS we are programming
intervals for the internal clocks. From gen11, these clocks are
configuration via the RPM_CONFIG and so for convenience, we would like
to convert to/from more natural units (ns).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200424162805.25920-2-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/Makefile
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
drivers/gpu/drm/i915/gt/intel_gt.c
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c [new file with mode: 0644]
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h [new file with mode: 0644]
drivers/gpu/drm/i915/gt/intel_gt_pm.c
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/gt/intel_rps.c
drivers/gpu/drm/i915/gt/selftest_rps.c
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_reg.h

index 6f112d8f80ca191d33a225fd4e6ecb1bd3f411fb..ce24a4ee95918849b91a7125c2a30e052a3a8833 100644 (file)
@@ -91,6 +91,7 @@ gt-y += \
        gt/intel_ggtt.o \
        gt/intel_ggtt_fencing.o \
        gt/intel_gt.o \
+       gt/intel_gt_clock_utils.o \
        gt/intel_gt_irq.o \
        gt/intel_gt_pm.o \
        gt/intel_gt_pm_irq.o \
index aab30d908072dd4bc613afe523722e3f9edd3dbb..3d3ef62ed89f66e11be394068b15b62d4292470c 100644 (file)
@@ -10,6 +10,7 @@
 #include "debugfs_gt_pm.h"
 #include "i915_drv.h"
 #include "intel_gt.h"
+#include "intel_gt_clock_utils.h"
 #include "intel_llc.h"
 #include "intel_rc6.h"
 #include "intel_rps.h"
@@ -268,7 +269,7 @@ static int frequency_show(struct seq_file *m, void *unused)
                           yesno(rpmodectl & GEN6_RP_ENABLE));
                seq_printf(m, "SW control enabled: %s\n",
                           yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
-                                 GEN6_RP_MEDIA_SW_MODE));
+                                GEN6_RP_MEDIA_SW_MODE));
 
                vlv_punit_get(i915);
                freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
@@ -300,8 +301,9 @@ static int frequency_show(struct seq_file *m, void *unused)
                u32 rp_state_cap;
                u32 rpmodectl, rpinclimit, rpdeclimit;
                u32 rpstat, cagf, reqf;
-               u32 rpupei, rpcurup, rpprevup;
-               u32 rpdownei, rpcurdown, rpprevdown;
+               u32 rpcurupei, rpcurup, rpprevup;
+               u32 rpcurdownei, rpcurdown, rpprevdown;
+               u32 rpupei, rpupt, rpdownei, rpdownt;
                u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
                int max_freq;
 
@@ -337,9 +339,16 @@ static int frequency_show(struct seq_file *m, void *unused)
                rpupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
                rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
                rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
-               rpdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
+               rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
                rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
                rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
+
+               rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
+               rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
+
+               rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
+               rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
+
                cagf = intel_rps_read_actual_frequency(rps);
 
                intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
@@ -372,7 +381,7 @@ static int frequency_show(struct seq_file *m, void *unused)
                           yesno(rpmodectl & GEN6_RP_ENABLE));
                seq_printf(m, "SW control enabled: %s\n",
                           yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
-                                 GEN6_RP_MEDIA_SW_MODE));
+                                GEN6_RP_MEDIA_SW_MODE));
 
                seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
                           pm_ier, pm_imr, pm_mask);
@@ -394,23 +403,35 @@ static int frequency_show(struct seq_file *m, void *unused)
                seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
                seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
                seq_printf(m, "CAGF: %dMHz\n", cagf);
-               seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
-                          rpupei, GT_PM_INTERVAL_TO_US(i915, rpupei));
-               seq_printf(m, "RP CUR UP: %d (%dus)\n",
-                          rpcurup, GT_PM_INTERVAL_TO_US(i915, rpcurup));
-               seq_printf(m, "RP PREV UP: %d (%dus)\n",
-                          rpprevup, GT_PM_INTERVAL_TO_US(i915, rpprevup));
+               seq_printf(m, "RP CUR UP EI: %d (%dns)\n",
+                          rpcurupei,
+                          intel_gt_pm_interval_to_ns(gt, rpcurupei));
+               seq_printf(m, "RP CUR UP: %d (%dns)\n",
+                          rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
+               seq_printf(m, "RP PREV UP: %d (%dns)\n",
+                          rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
                seq_printf(m, "Up threshold: %d%%\n",
                           rps->power.up_threshold);
-
-               seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
-                          rpdownei, GT_PM_INTERVAL_TO_US(i915, rpdownei));
-               seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
-                          rpcurdown, GT_PM_INTERVAL_TO_US(i915, rpcurdown));
-               seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
-                          rpprevdown, GT_PM_INTERVAL_TO_US(i915, rpprevdown));
+               seq_printf(m, "RP UP EI: %d (%dns)\n",
+                          rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
+               seq_printf(m, "RP UP THRESHOLD: %d (%dns)\n",
+                          rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
+
+               seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n",
+                          rpcurdownei,
+                          intel_gt_pm_interval_to_ns(gt, rpcurdownei));
+               seq_printf(m, "RP CUR DOWN: %d (%dns)\n",
+                          rpcurdown,
+                          intel_gt_pm_interval_to_ns(gt, rpcurdown));
+               seq_printf(m, "RP PREV DOWN: %d (%dns)\n",
+                          rpprevdown,
+                          intel_gt_pm_interval_to_ns(gt, rpprevdown));
                seq_printf(m, "Down threshold: %d%%\n",
                           rps->power.down_threshold);
+               seq_printf(m, "RP DOWN EI: %d (%dns)\n",
+                          rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
+               seq_printf(m, "RP DOWN THRESHOLD: %d (%dns)\n",
+                          rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
 
                max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
                            rp_state_cap >> 16) & 0xff;
index 1c99cc72305a64bff72ab9eac46682f027e3f6b5..d9cf8194c99777e726bf4f7d0b36c2994c6e9fb6 100644 (file)
@@ -7,6 +7,7 @@
 #include "i915_drv.h"
 #include "intel_context.h"
 #include "intel_gt.h"
+#include "intel_gt_clock_utils.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_requests.h"
 #include "intel_mocs.h"
@@ -576,6 +577,8 @@ int intel_gt_init(struct intel_gt *gt)
         */
        intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 
+       intel_gt_init_clock_frequency(gt);
+
        err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
        if (err)
                goto out_fw;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
new file mode 100644 (file)
index 0000000..852a7d7
--- /dev/null
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt.h"
+#include "intel_gt_clock_utils.h"
+
+#define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
+#define MHZ_24 24000000 /* 24MHz, 83.333ns */
+#define MHZ_25 25000000 /* 25MHz, 80ns */
+
+static u32 read_clock_frequency(const struct intel_gt *gt)
+{
+       if (INTEL_GEN(gt->i915) >= 11) {
+               u32 config;
+
+               config = intel_uncore_read(gt->uncore, RPM_CONFIG0);
+               config &= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
+               config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+
+               switch (config) {
+               case 0: return MHZ_24;
+               case 1:
+               case 2: return MHZ_19_2;
+               default:
+               case 3: return MHZ_25;
+               }
+       } else if (INTEL_GEN(gt->i915) >= 9) {
+               if (IS_GEN9_LP(gt->i915))
+                       return MHZ_19_2;
+               else
+                       return MHZ_24;
+       } else {
+               return MHZ_25;
+       }
+}
+
+void intel_gt_init_clock_frequency(struct intel_gt *gt)
+{
+       /*
+        * Note that on gen11+, the clock frequency may be reconfigured.
+        * We do not, and we assume nobody else does.
+        */
+       gt->clock_frequency = read_clock_frequency(gt);
+       GT_TRACE(gt,
+                "Using clock frequency: %dkHz\n",
+                gt->clock_frequency / 1000);
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+void intel_gt_check_clock_frequency(const struct intel_gt *gt)
+{
+       if (gt->clock_frequency != read_clock_frequency(gt)) {
+               dev_err(gt->i915->drm.dev,
+                       "GT clock frequency changed, was %uHz, now %uHz!\n",
+                       gt->clock_frequency,
+                       read_clock_frequency(gt));
+       }
+}
+#endif
+
+static u64 div_u64_roundup(u64 nom, u32 den)
+{
+       return div_u64(nom + den - 1, den);
+}
+
+u32 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u32 count)
+{
+       return div_u64_roundup(mul_u32_u32(count, 1000 * 1000 * 1000),
+                              gt->clock_frequency);
+}
+
+u32 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u32 count)
+{
+       return intel_gt_clock_interval_to_ns(gt, 16 * count);
+}
+
+u32 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u32 ns)
+{
+       return div_u64_roundup(mul_u32_u32(gt->clock_frequency, ns),
+                              1000 * 1000 * 1000);
+}
+
+u32 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u32 ns)
+{
+       u32 val;
+
+       /*
+        * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
+        * 8300) freezing up around GPU hangs. Looks as if even
+        * scheduling/timer interrupts start misbehaving if the RPS
+        * EI/thresholds are "bad", leading to a very sluggish or even
+        * frozen machine.
+        */
+       val = DIV_ROUND_UP(intel_gt_ns_to_clock_interval(gt, ns), 16);
+       if (IS_GEN(gt->i915, 6))
+               val = roundup(val, 25);
+
+       return val;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h
new file mode 100644 (file)
index 0000000..f793c89
--- /dev/null
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_GT_CLOCK_UTILS_H__
+#define __INTEL_GT_CLOCK_UTILS_H__
+
+#include <linux/types.h>
+
+struct intel_gt;
+
+void intel_gt_init_clock_frequency(struct intel_gt *gt);
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+void intel_gt_check_clock_frequency(const struct intel_gt *gt);
+#else
+static inline void intel_gt_check_clock_frequency(const struct intel_gt *gt) {}
+#endif
+
+u32 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u32 count);
+u32 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u32 count);
+
+u32 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u32 ns);
+u32 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u32 ns);
+
+#endif /* __INTEL_GT_CLOCK_UTILS_H__ */
index 6bdb74892a1e3b06f36cdb86be2d9b77c3501188..4c4c74ef4f213820b5158d7d5ffdb1a5f418db5b 100644 (file)
@@ -12,6 +12,7 @@
 #include "intel_context.h"
 #include "intel_engine_pm.h"
 #include "intel_gt.h"
+#include "intel_gt_clock_utils.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_requests.h"
 #include "intel_llc.h"
@@ -138,6 +139,8 @@ static void gt_sanitize(struct intel_gt *gt, bool force)
        wakeref = intel_runtime_pm_get(gt->uncore->rpm);
        intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 
+       intel_gt_check_clock_frequency(gt);
+
        /*
         * As we have just resumed the machine and woken the device up from
         * deep PCI sleep (presumably D3_cold), assume the HW has been reset
index 96890dd12b5feaded292dd5afba837de028c7891..d02ccb735e24a9791958f0530efe8835c3e012f5 100644 (file)
@@ -61,6 +61,7 @@ struct intel_gt {
        struct list_head closed_vma;
        spinlock_t closed_lock; /* guards the list of closed_vma */
 
+       ktime_t last_init_time;
        struct intel_reset reset;
 
        /**
@@ -72,14 +73,12 @@ struct intel_gt {
         */
        intel_wakeref_t awake;
 
+       u32 clock_frequency;
+
        struct intel_llc llc;
        struct intel_rc6 rc6;
        struct intel_rps rps;
 
-       ktime_t last_init_time;
-
-       struct i915_vma *scratch;
-
        spinlock_t irq_lock;
        u32 gt_imr;
        u32 pm_ier;
@@ -97,6 +96,8 @@ struct intel_gt {
         * Reserved for exclusive use by the kernel.
         */
        struct i915_address_space *vm;
+
+       struct i915_vma *scratch;
 };
 
 enum intel_gt_scratch_field {
index ff088702c8739f658e00de7b3a6321fad85a1d59..2ce006e58b4a7f29338f4c3fa07a30c961d0a239 100644 (file)
@@ -8,6 +8,7 @@
 
 #include "i915_drv.h"
 #include "intel_gt.h"
+#include "intel_gt_clock_utils.h"
 #include "intel_gt_irq.h"
 #include "intel_gt_pm_irq.h"
 #include "intel_rps.h"
@@ -524,8 +525,8 @@ static u32 rps_limits(struct intel_rps *rps, u8 val)
 
 static void rps_set_power(struct intel_rps *rps, int new_power)
 {
-       struct intel_uncore *uncore = rps_to_uncore(rps);
-       struct drm_i915_private *i915 = rps_to_i915(rps);
+       struct intel_gt *gt = rps_to_gt(rps);
+       struct intel_uncore *uncore = gt->uncore;
        u32 threshold_up = 0, threshold_down = 0; /* in % */
        u32 ei_up = 0, ei_down = 0;
 
@@ -570,23 +571,25 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
        /* When byt can survive without system hang with dynamic
         * sw freq adjustments, this restriction can be lifted.
         */
-       if (IS_VALLEYVIEW(i915))
+       if (IS_VALLEYVIEW(gt->i915))
                goto skip_hw_write;
 
-       GT_TRACE(rps_to_gt(rps),
+       GT_TRACE(gt,
                 "changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n",
                 new_power, threshold_up, ei_up, threshold_down, ei_down);
 
-       set(uncore, GEN6_RP_UP_EI, GT_INTERVAL_FROM_US(i915, ei_up));
+       set(uncore, GEN6_RP_UP_EI,
+           intel_gt_ns_to_pm_interval(gt, ei_up * 1000));
        set(uncore, GEN6_RP_UP_THRESHOLD,
-           GT_INTERVAL_FROM_US(i915, ei_up * threshold_up / 100));
+           intel_gt_ns_to_pm_interval(gt, ei_up * threshold_up * 10));
 
-       set(uncore, GEN6_RP_DOWN_EI, GT_INTERVAL_FROM_US(i915, ei_down));
+       set(uncore, GEN6_RP_DOWN_EI,
+           intel_gt_ns_to_pm_interval(gt, ei_down * 1000));
        set(uncore, GEN6_RP_DOWN_THRESHOLD,
-           GT_INTERVAL_FROM_US(i915, ei_down * threshold_down / 100));
+           intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
 
        set(uncore, GEN6_RP_CONTROL,
-           (INTEL_GEN(i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
+           (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
            GEN6_RP_MEDIA_HW_NORMAL_MODE |
            GEN6_RP_MEDIA_IS_GFX |
            GEN6_RP_ENABLE |
@@ -923,11 +926,11 @@ static bool rps_reset(struct intel_rps *rps)
 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
 static bool gen9_rps_enable(struct intel_rps *rps)
 {
-       struct drm_i915_private *i915 = rps_to_i915(rps);
-       struct intel_uncore *uncore = rps_to_uncore(rps);
+       struct intel_gt *gt = rps_to_gt(rps);
+       struct intel_uncore *uncore = gt->uncore;
 
        /* Program defaults and thresholds for RPS */
-       if (IS_GEN(i915, 9))
+       if (IS_GEN(gt->i915, 9))
                intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
                                      GEN9_FREQUENCY(rps->rp1_freq));
 
@@ -1217,6 +1220,11 @@ void intel_rps_enable(struct intel_rps *rps)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        struct intel_uncore *uncore = rps_to_uncore(rps);
 
+       if (!HAS_RPS(i915))
+               return;
+
+       intel_gt_check_clock_frequency(rps_to_gt(rps));
+
        intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
        if (IS_CHERRYVIEW(i915))
                rps->enabled = chv_rps_enable(rps);
@@ -1753,7 +1761,7 @@ static u32 read_cagf(struct intel_rps *rps)
                freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
                vlv_punit_put(i915);
        } else {
-               freq = intel_uncore_read(rps_to_gt(rps)->uncore, GEN6_RPSTAT1);
+               freq = intel_uncore_read(rps_to_uncore(rps), GEN6_RPSTAT1);
        }
 
        return intel_rps_get_cagf(rps, freq);
@@ -1761,7 +1769,7 @@ static u32 read_cagf(struct intel_rps *rps)
 
 u32 intel_rps_read_actual_frequency(struct intel_rps *rps)
 {
-       struct intel_runtime_pm *rpm = rps_to_gt(rps)->uncore->rpm;
+       struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm;
        intel_wakeref_t wakeref;
        u32 freq = 0;
 
index 9d9c8e0aa2e704b2e594bf07150854f78356f0bc..e13cbcb82825f1540beb9d2315ce4ad940f9cc42 100644 (file)
@@ -9,6 +9,7 @@
 #include "intel_engine_heartbeat.h"
 #include "intel_engine_pm.h"
 #include "intel_gpu_commands.h"
+#include "intel_gt_clock_utils.h"
 #include "intel_gt_pm.h"
 #include "intel_rc6.h"
 #include "selftest_rps.h"
@@ -787,7 +788,8 @@ static int __rps_up_interrupt(struct intel_rps *rps,
        }
 
        timeout = intel_uncore_read(uncore, GEN6_RP_UP_EI);
-       timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
+       timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout);
+       timeout = DIV_ROUND_UP(timeout, 1000);
 
        sleep_for_ei(rps, timeout);
        GEM_BUG_ON(i915_request_completed(rq));
@@ -834,7 +836,8 @@ static int __rps_down_interrupt(struct intel_rps *rps,
        }
 
        timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
-       timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
+       timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout);
+       timeout = DIV_ROUND_UP(timeout, 1000);
 
        sleep_for_ei(rps, timeout);
 
index 2905bcff79cf69a87542980be04a29cd3f2bb4f5..037e9e0275b6486346a77f68a08514a439df303c 100644 (file)
@@ -32,6 +32,7 @@
 #include <drm/drm_debugfs.h>
 
 #include "gem/i915_gem_context.h"
+#include "gt/intel_gt_clock_utils.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_gt_requests.h"
 #include "gt/intel_reset.h"
@@ -926,21 +927,30 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
                seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
                seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
                seq_printf(m, "CAGF: %dMHz\n", cagf);
-               seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
-                          rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
-               seq_printf(m, "RP CUR UP: %d (%dus)\n",
-                          rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
-               seq_printf(m, "RP PREV UP: %d (%dus)\n",
-                          rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
+               seq_printf(m, "RP CUR UP EI: %d (%dns)\n",
+                          rpupei,
+                          intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei));
+               seq_printf(m, "RP CUR UP: %d (%dun)\n",
+                          rpcurup,
+                          intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup));
+               seq_printf(m, "RP PREV UP: %d (%dns)\n",
+                          rpprevup,
+                          intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup));
                seq_printf(m, "Up threshold: %d%%\n",
                           rps->power.up_threshold);
 
-               seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
-                          rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
-               seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
-                          rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
-               seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
-                          rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
+               seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n",
+                          rpdownei,
+                          intel_gt_pm_interval_to_ns(&dev_priv->gt,
+                                                     rpdownei));
+               seq_printf(m, "RP CUR DOWN: %d (%dns)\n",
+                          rpcurdown,
+                          intel_gt_pm_interval_to_ns(&dev_priv->gt,
+                                                     rpcurdown));
+               seq_printf(m, "RP PREV DOWN: %d (%dns)\n",
+                          rpprevdown,
+                          intel_gt_pm_interval_to_ns(&dev_priv->gt,
+                                                     rpprevdown));
                seq_printf(m, "Down threshold: %d%%\n",
                           rps->power.down_threshold);
 
index 4a1965467374dd4771fb0341baadf9f52fa64bdd..981b52aa5ed8486b5aa4dbf8e9a1dba245fa5743 100644 (file)
@@ -4015,31 +4015,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
 #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
 
-/*
- * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
- * 8300) freezing up around GPU hangs. Looks as if even
- * scheduling/timer interrupts start misbehaving if the RPS
- * EI/thresholds are "bad", leading to a very sluggish or even
- * frozen machine.
- */
-#define INTERVAL_1_28_US(us)   roundup(((us) * 100) >> 7, 25)
-#define INTERVAL_1_33_US(us)   (((us) * 3)   >> 2)
-#define INTERVAL_0_833_US(us)  (((us) * 6) / 5)
-#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
-                               (IS_GEN9_LP(dev_priv) ? \
-                               INTERVAL_0_833_US(us) : \
-                               INTERVAL_1_33_US(us)) : \
-                               INTERVAL_1_28_US(us))
-
-#define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
-#define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
-#define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
-#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
-                           (IS_GEN9_LP(dev_priv) ? \
-                           INTERVAL_0_833_TO_US(interval) : \
-                           INTERVAL_1_33_TO_US(interval)) : \
-                           INTERVAL_1_28_TO_US(interval))
-
 /*
  * Logical Context regs
  */