struct flexcan_regs __iomem *regs = priv->regs;
u32 iflag1, iflag2;
- iflag2 = priv->read(®s->iflag2) & priv->rx_mask2 &
- ~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
+ iflag2 = priv->read(®s->iflag2) & priv->rx_mask2;
iflag1 = priv->read(®s->iflag1) & priv->rx_mask1;
return (u64)iflag2 << 32 | iflag1;
disable_irq(dev->irq);
priv->write(priv->reg_ctrl_default, ®s->ctrl);
priv->write(priv->rx_mask1, ®s->imask1);
- priv->write(priv->rx_mask2, ®s->imask2);
+ priv->write(priv->rx_mask2 | FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), ®s->imask2);
enable_irq(dev->irq);
/* print chip status */
priv->tx_mb_idx = priv->mb_count - 1;
priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
- priv->rx_mask1 = 0;
- priv->rx_mask2 = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
-
priv->offload.mailbox_read = flexcan_mailbox_read;
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
imask = GENMASK_ULL(priv->offload.mb_last,
priv->offload.mb_first);
- priv->rx_mask1 |= imask;
- priv->rx_mask2 |= imask >> 32;
+ priv->rx_mask1 = imask;
+ priv->rx_mask2 = imask >> 32;
err = can_rx_offload_add_timestamp(dev, &priv->offload);
} else {
- priv->rx_mask1 |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
+ priv->rx_mask1 = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
err = can_rx_offload_add_fifo(dev, &priv->offload,
FLEXCAN_NAPI_WEIGHT);