target-mips: support CP0.Config4.AE bit

The read-only Config4.AE bit set denotes extended 10 bits ASID.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3e233ad639cde4f79eb70c51113ea4878406282a..2c4583931ca95b9021cc3bc19fc217c2d58f9c8d 100644 (file)
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -468,6 +468,7 @@ struct CPUMIPSState {
     int32_t CP0_Config4_rw_bitmask;
 #define CP0C4_M    31
 #define CP0C4_IE   29
+#define CP0C4_AE   28
 #define CP0C4_KScrExist 16
 #define CP0C4_MMUExtDef 14
 #define CP0C4_FTLBPageSize 8

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 01510b38b19cada6333a4024ded26281f6820bb9..bab52cb2549860fd6ed2febce9175052f6ea3319 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20302,7 +20302,8 @@ void cpu_state_reset(CPUMIPSState *env)
     if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
         env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
     }
-    env->CP0_EntryHi_ASID_mask = 0xff;
+    env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ?
+                                 0x3ff : 0xff;
     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
     /* vectored interrupts not implemented, timer on int 7,
        no performance counters. */