drm/i915: Show IPEIR and IPEHR in the engine dump

A useful bit of information for inspecting GPU stalls from
intel_engine_dump() are the error registers, IPEIR and IPEHR.

v2: Fixup gen changes in register offsets (Tvrtko)
v3: Old FADDR location as well
v4: Use I915_READ64_2x32

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171218123914.19027-1-chris@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 510e0bc3a377fbaf892ef5b3bb5bf8f36de146a2..b4807497e92dcc196a4affc98a27932420685d60 100644 (file)
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1757,6 +1757,24 @@ void intel_engine_dump(struct intel_engine_cs *engine,
        addr = intel_engine_get_last_batch_head(engine);
        drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
                   upper_32_bits(addr), lower_32_bits(addr));
+       if (INTEL_GEN(dev_priv) >= 8)
+               addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
+                                       RING_DMA_FADD_UDW(engine->mmio_base));
+       else if (INTEL_GEN(dev_priv) >= 4)
+               addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+       else
+               addr = I915_READ(DMA_FADD_I8XX);
+       drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
+                  upper_32_bits(addr), lower_32_bits(addr));
+       if (INTEL_GEN(dev_priv) >= 4) {
+               drm_printf(m, "\tIPEIR: 0x%08x\n",
+                          I915_READ(RING_IPEIR(engine->mmio_base)));
+               drm_printf(m, "\tIPEHR: 0x%08x\n",
+                          I915_READ(RING_IPEHR(engine->mmio_base)));
+       } else {
+               drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
+               drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
+       }
 
        if (HAS_EXECLISTS(dev_priv)) {
                const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];