drm/amd/display: Add function for dumping clk registers

[why]
Allow devs to check raw clk register values by dumping them on the log

[how]
Add clk register dump implementation

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Johnson Chen <johnson.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 8d4c0b209872babcafc72f31a1ed7ef0293ff2e7..789091f3bdc85ee96226388ca7776bf3953ab187 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -50,6 +50,7 @@
 #include "dc_dmub_srv.h"
 #include "link.h"
 #include "logger_types.h"
+
 #undef DC_LOGGER
 #define DC_LOGGER \
        clk_mgr->base.base.ctx->logger
@@ -417,9 +418,8 @@ bool dcn35_are_clock_states_equal(struct dc_clocks *a,
 }
 
 static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
-               struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
+               struct clk_mgr_dcn35 *clk_mgr)
 {
-
 }
 
 static struct clk_bw_params dcn35_bw_params = {
@@ -986,7 +986,6 @@ void dcn35_clk_mgr_construct(
                struct dccg *dccg)
 {
        struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
-       struct clk_log_info log_info = {0};
        clk_mgr->base.base.ctx = ctx;
        clk_mgr->base.base.funcs = &dcn35_funcs;
 
@@ -1039,7 +1038,7 @@ void dcn35_clk_mgr_construct(
                dcn35_bw_params.wm_table = ddr5_wm_table;
        }
        /* Saved clocks configured at boot for debug purposes */
-       dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
+       dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
 
        clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
        clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index fa9614bcb1605f6b75f116ca5387df338bc3dc4c..cbba39d251e5335d6e11604fc327b8ad31284aea 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -62,6 +62,25 @@ struct dcn3_clk_internal {
        uint32_t CLK4_CLK0_CURRENT_CNT; //fclk
 };
 
+struct dcn35_clk_internal {
+       int dummy;
+       uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
+       uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
+       uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
+       uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
+       uint32_t CLK1_CLK4_CURRENT_CNT; //dtbclk
+       //uint32_t CLK1_CLK5_CURRENT_CNT; //dpiaclk
+       //uint32_t CLK1_CLK6_CURRENT_CNT; //srdbgclk
+       uint32_t CLK1_CLK3_DS_CNTL;         //dcf_deep_sleep_divider
+       uint32_t CLK1_CLK3_ALLOW_DS;    //dcf_deep_sleep_allow
+
+       uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
+       uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
+       uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
+       uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
+       uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass
+};
+
 struct dcn301_clk_internal {
        int dummy;
        uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk