mmc: sdhci-cadence: Fix writing PHY delay

Add polling for ACK to be sure that data are written to PHY register.

Signed-off-by: Piotr Sroka <piotrs@cadence.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 07a27dcb42be783d62940f4d07f2b80e69acb047..84bdcc59c0240d3f6048f770bda683b436775685 100644 (file)
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -68,11 +68,12 @@ struct sdhci_cdns_priv {
        bool enhanced_strobe;
 };
 
-static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
-                                    u8 addr, u8 data)
+static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
+                                   u8 addr, u8 data)
 {
        void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
        u32 tmp;
+       int ret;
 
        tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
              (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
@@ -81,8 +82,14 @@ static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
        tmp |= SDHCI_CDNS_HRS04_WR;
        writel(tmp, reg);
 
+       ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
+       if (ret)
+               return ret;
+
        tmp &= ~SDHCI_CDNS_HRS04_WR;
        writel(tmp, reg);
+
+       return 0;
 }
 
 static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)